Combinational Logic Gates Research Articles

Fluorescent graphene oxide logic gates for discrimination of iron (3+) and iron (2+) in living cells by imaging

A combinational logic gate based on fluorescent graphene oxide has been reported to discriminate Fe(3+), Fe(2+) and their mixture in living cells by fluorescence imaging.

All-optical and combinational optoelectronic logic gates using chaotic synchronization of coupling-feedback semiconductor lasers and amplitude modulation

Chaotic synchronization of coupling-feedback semiconductor laser diodes is theoretically studied for optical logic gate applications. The constructions of the fundamental all-optical XNOR, NOR, NOT gates and combinatorial optoelectronic logic gate and their physical models are presented. The computational principles and methods are defined for these logic gates. Two laser diodes commonly driven by a monochromatic light beam become chaos. Chaotic synchronization between the two lasers is achieved by coupling-feedback. Based on the system and an external optical modulation method, the all-optical logic gates are performed for digit computation via the amplitude modulator modulating the coupling light to synchronize or un-synchronize two chaotic states. And the combinational optoelectronic logic gate is implemented for digit computation by modulating the amplitude of coupling light and the current to synchronize or un-synchronize two chaotic states. Lastly, the effect of resynchronization and reunsynchronization on logic output was analyzed numerically, in detail. Numerical simulations show the validity and feasibility of the methods.

Contributions to the evaluation of ensembles of combinational logic gates

This work presents an effective way for evaluating and validating ensembles of combinational CMOS gates and logic cell libraries. The major contributions include an innovative design methodology for such a kind of test vehicle, as well as a simple and flexible multi-operating mode circuit architecture. The resulting circuit is quite useful for cell library verification at different levels: in the EDA environment and on silicon prototyping. The proposed methodology can be applied for analysis taking into account the logic gate functionality, timing performance, power consumption and circuit operating impact of nanometer aging effects. Simulation results demonstrate the circuit operation, features and facilities described herein.

Superconductive combinational logic circuit using magnetically coupled SQUID array

In this paper, we propose the development of superconductive combinational logic circuits. One of the difficulties in designing superconductive single-flux-quantum (SFQ) digital circuits can be attributed to the fundamental nature of the SFQ circuits, in which all logic gates have latching functions and are based on sequential logic. The design of ultralow-power superconductive digital circuits can be facilitated by the development of superconductive combinational logic circuits in which the output is a function of only the present input. This is because superconductive combinational logic circuits do not require determination of the timing adjustment and clocking scheme. Moreover, semiconductor design tools can be used to design digital circuits because CMOS logic gates are based on combinational logic. The proposed superconductive combinational logic circuits comprise a magnetically coupled SQUID array. By adjusting the circuit parameters and coupling strengths between neighboring SQUIDs, fundamental combinational logic gates, including the AND, OR, and NOT gates, can be built. We have verified the accuracy of the operations of the fundamental logic gates by analog circuit simulations.

GERBANG LOGIKA BERBASIS PROGRAMMABLE LOGIC DEVICE (PLD)

In middle 1990, electronics industry had evolution in personal Computer, telephone cellular and high speed data communication equipment. To follow this development, electronics companies have designed and produce new product. One of these innovations is Programmable Logic Devices (PLD) technology. It is a technology to change function of IC digital logic using programming. Many of Programmable Logic Device (PLD) can be used to programming logic using single chip of integrated circuit (IC). Programmable Logic Devices (PLD) technology is applied using IC PAL 22V10 to design basic logic gate AND, OR, NOT and combinational logic gate NAND and NOR.

ホール移動制御を指向した人工核酸塩基群

In recent years, DNA has attracted much attention as a conductive biopolymer. Recent efforts to elucidate the mechanism of long-range hole transport in DNA has encouraged us in the view that DNA can be a good mediator for hole transport by the selection of an appropriate sequence. However, when natural DNA is used as a molecular wire, serious unavoidable oxidative degradation of G bases occurs. In addition, the hole transport in natural DNA is strongly influenced by the sequence and the transport distance. Of great importance in the realization of a real DNA wire is the molecular design of an artificial nucleobase that can effectively mediate hole transport and, at the same time, is not oxidatively decomposed. We now report on a protocol for designing an artifi-cial nucleobase that can act as an effective mediator for long-range hole transport without subsequent decomposition. Additionally, we also describe the applications of the artificial hole-transporting DNA to (i) combinational logic gates, (ii) drug-releasing systems, and (iii) genotyping biofilms on a gold electrode.

An Azacrowned Phthalimide as a Metal-Ion Sensitive and Solvatofluorochromic Fluorophore: Fluorescence Properties and a Mimic Integrated Logic Operation

Abstract The novel azacrowned phthalimide 1 has been prepared and its fluorescence properties have been investigated by addition of EtOH and Ag+. The phthalimide 1 showed appreciable solvatofluorochromism; its fluorescence maxima (λFL) appeared in the wavelength region between 458 (in Et2O) and 544 nm (in EtOH). In benzene, the phthalimide 1 gave off blue emission (λFL 466 nm) while it emitted green fluorescence (λFL 497 nm) upon addition of 250 mM of EtOH. Both the blue and the green emissions were quenched by Ag+. Potential logic operations of the phthalimide 1 were examined using fluorescence outputs at 450 (Out1) and 515 nm (Out2) and two input stimuli, EtOH (In1) and Ag+ (In2). The Out1 was on in the absence of these inputs while its intensity was reduced (off) by either or both of the inputs to serve as a NOR operator. The Out2 was off without the inputs; in contrast, the intensity of Out2 was enhanced (on) by In1. The enhanced Out2 was switched off by In2. The Out2, thus, corresponds to an INHIBIT operation responding to the input signals. The crowned phthalimide 1 mimics a two-input–two-output combinational logic gate with a single fluorophore and a single ion-sensing unit.

Demand-driven logic simulation using a network of loosely coupled processors

Logic simulation is used extensively in the design of digital systems for the purpose of studying the behaviour of circuits under various conditions and for verifying the required performance of circuits. There is considerable interest in methods which reduce the simulation time during the design process. In this paper, we investigate how this can be achieved by simulating the action of logic circuits using a network of loosely coupled processors. Circuits modelled as directed graphs comprising clocked sequential components and (unclocked) arbitrary combinational logic gates can be partitioned into separate tasks each consisting of a sequential component with an associated network of combinational components. We present cost functions for evaluating a task subject to probabilistic assumptions about the functioning of the circuits. The circuit evaluation method used in the simulation process is significant. We apply lazy evaluation, a demand-driven evaluation strategy in which signals in the circuit are evaluated on a 'need to do' basis, resulting in a considerable saving in circuit simulation time. We achieve distributed logic simulation using a network of workstations and show from experimental results that by using such a configuration, we essentially obtain a single computation engine which can be used to obtain speedups in circuit simulation when compared with uniprocessor simulation systems. Interprocess communications between tasks on different workstations proceed via remote procedure calls while local communications between tasks take place via shared memory. The method of partitioning used in the circuit model ensures that communications between tasks take place only at defined times in the simulation sequence.

Hardware realization of inverse kinematics for robot manipulators

For real-time processing of kinematic information required for intelligent robotic applications, a hardware realization of an inverse kinematics algorithm is a challenging task. This paper adopts an incremental unit computation method to accomplish the inverse kinematics of a three-axis articulated robot. This method starts from defining incremental units in joint and Cartesian spaces, which represent the position resolutions in each space. With this approach, calculation of the inverse Jacobian matrix can be realized through a simple combinational logic gate circuit. Furthermore, the incremental direct kinematics can be solved by using a digital differential analyzer (DDA) integrator. The hardware architecture to implement the algorithm is also described. Applying the hardware implemented by an erasable programmable logic device (EPLD) to the straight-line trajectory of an experimental robot, the authors have obtained an end-effector's maximum speed of 12.6 m/s.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Timing macromodels for CMOS static set/reset latches and their applications

Efficient timing macromodels for CMOS static NAND-type and NOR-type latches are developed, to compute analytically their signal timing under different input state transitions. The timing equations in the macromodels are derived from the effective dominant pole of the linearised large-signal equivalent circuit of a latch under the characteristic-waveform consideration. Through extensive comparisons with SPICE simulations, it is found that the macromodels have a maximum error of 22% for the total propagation delay times of the latches, with different device sizes, capacitive loads, device parameter variations, noncharacteristic-waveform input excitations and input-state transitions. When incorporated with the timing models of CMOS combinational logic gates, the macromodels can also be applied to characterise the signal timing of static sequential integrated circuits. Application examples on two CMOS clocked flip-flops and experimental verifications on a fabricated CMOS master-slave T flipflop are successfully made to confirm the accuracy and applicability of the developed macromodels. Reasonable accuracy, wide applicable ranges and CPU-time, and memory efficiency have made the macromodels very attractive in many CAD applications.

An Efficient Timing Model for CMOS Combinational Logic Gates

A new general timing model for CMOS combinational logic gates is proposed. In this model, the linearized large-signal equivalent circuit of a gate is first constructed. Then applying the dominant-pole-dominant-zero (DPDZ) method, the dominant pole of the equivalent circuit is calculated. Using this pole, the signal timing can be explicitly expressed. Comparisons between calculation results and simulation results are made and error analyses are performed. The worst-case error in characteristic-waveform timing can be confined to be within 35 percent for CMOS inverters, multi-input NOR gates or multi-input NAND gates with different device dimensions, capacitive loads, and device parameters. Better accuracy can be obtained for logic gates with commonly-used channel dimension or large capacitive load. For internal waveforms not deviating much from the characteristic waveforms, the worst-case error in signal timing is not substantially increased. Applying the proposed timing model in an experimental timing simulator, the signal timing can be analyzed accurately and efficiently with reduced CPU time and memory.