Combinational Research Articles

Analysis of fault tolerance capability of QCA circuit under regular clocking

ABSTRACT With significant progress in device scaling, current CMOS technology faces challenges such as low device density and increased power dissipation. Quantum-dot Cellular Automata (QCA) stands as one of the alternative nanotechnologies that proved viable to overcome these hurdles. The fundamental building block for implementing logic circuits is a QCA cell, which includes two vertically positioned electrons within four quantum dots. The majority gate and inverters are considered to be the fundamental primitives in QCA. On the other hand, clocking serves a crucial part in ensuring the correct synchronisation and information transmission within a circuit. Furthermore, regular clocking resolves fabrication pitfalls at the nanoscale and supports scalability. However, defects remain a concern in nanoscale circuit realisation. This research investigates the performance of logic circuits realised in regular clocking concerning the potentiality to tolerate faults. The circuits in both combinational and sequential logic are examined. For this purpose, the HDLQ and QCADesigner simulators are utilised. In accordance with the investigation, the performance of the circuits realised using zig–zag clocking is noteworthy, whereas the USE clock is noticed in a few cases.

Combinational Circuits Testing Based on Hsiao Codes with Self-Dual Check Functions

This paper investigates the features of using modified Hamming codes, which are also known as Hsiao codes. Self-checking digital devices are proposed to be implemented with calculations testing using two diagnostic signs. These signs indicate that the functions (there are functions that describe check bits) belong to the class of self-dual Boolean functions and also belong to the codewords of Hsiao codes (these are codes with an odd column of weights). The authors have established that all check functions can be self-dual for a certain number of the Hsiao codes’ data symbols. Such codes can be used in the synthesis of concurrent error-detection circuits by two diagnostic signs. The paper describes the structure of an organization for a concurrent error-detection circuit based on Hsiao codes with self-dual check functions. Some experimental results are presented on the synthesis of self-checking devices using the proposed methodology. The controllability of the structure and the number of test combinations both increased. Hsiao codes can be effectively used with self-dual check functions in the synthesis of self-checking digital devices.

IRF1 cooperates with ISGF3 or GAF to form innate immune de novo enhancers in macrophages.

Macrophages exposed to immune stimuli reprogram their epigenomes to alter their subsequent functions. Exposure to bacterial lipopolysaccharide (LPS) causes widespread nucleosome remodeling and the formation of thousands of de novo enhancers. We dissected the regulatory logic by which the network of interferon regulatory factors (IRFs) induces the opening of chromatin and the formation of de novo enhancers. We found that LPS-activated IRF3 mediated de novo enhancer formation indirectly by activating the type I interferon (IFN)-induced ISGF3. However, ISGF3 was generally needed to collaborate with IRF1, particularly where chromatin was less accessible. At these locations, IRF1 was required for the initial opening of chromatin, with ISGF3 extending accessibility and promoting the deposition of H3K4me1, marking poised enhancers. Because IRF1 expression depends on the transcription factor NF-κB, which is activated in infected but not bystander cells, IRF-regulated enhancers required activation of both the IRF3 and NF-κB branches of the innate immune signaling network. However, type II IFN (IFN-γ), which is typically produced by T cells, may also induce IRF1 expression through the STAT1 homodimer GAF. We showed that, upon IFN-γ stimulation, IRF1 was also responsible for opening inaccessible chromatin sites that could then be exploited by GAF to form de novo enhancers. Together, our results reveal how combinatorial logic gates of IRF1-ISGF3 or IRF1-GAF restrict immune epigenomic memory formation to macrophages exposed to pathogens or IFN-γ-secreting T cells but not bystander macrophages exposed transiently to type I IFN.

An Infinite Family of Connected 1-Factorisations of Complete 3-Uniform Hypergraphs

A connected 1-factorisation is a 1-factorisation of a hypergraph for which the union of each pair of distinct 1-factors is a connected hypergraph. A uniform 1-factorisation is a 1-factorisation of a hypergraph for which the union of each pair of distinct 1-factors is isomorphic to the same subhypergraph, and a uniform-connected 1-factorisation is a uniform 1-factorisation in which that subhypergraph is connected. Chen and Lu [Journal of Algebraic Combinatorics, 46(2) 475--497, 2017] describe a family of 1-factorisations of the complete 3-uniform hypergraph on $q+1$ vertices, where $q\equiv 2\pmod 3$ is a prime power. In this paper, we show that their construction yields a connected 1-factorisation only when $q=2,5,11$ or $q=2^p$ for some odd prime $p$, and a uniform 1-factorisation only for $q=2,5,8$ (each of these is a uniform-connected 1-factorisation).

The Importance of Pre-Anesthetic Evaluation in Patient Safety: A Systematic Review

Background: Pre-anesthetic evaluation is the initial stage of anesthesia procedures for patients. This evaluation involves elucidating the patient's medical history, determining patient readiness, screening for undisclosed disorders, and identifying risk factors. Safety measures help mitigate patient-related risks within medical environments. The aim of this study is to investigate the role of Pre-anesthetic evaluation in patient safety. Methods: The present study was a review conducted in the year 2024. Databases including PubMed, Direct Science, MEDLINE, Proquest, SID, Scopus, Google Scholar, Magiran, and library resources were searched using keywords such as Pre-anesthetic evaluation, pre-anesthetic visit, anesthesia clinic, patient safety, and their English equivalents. A logical combination of these keywords was performed using "OR," "AND," and "NOT" operators. The search was conducted in relevant articles from the year 2000 to January 2024. Results: Initially, 22,000 articles were screened, and ultimately, 16 relevant articles were used for preparing this paper. In all the reviewed articles, pre-anesthetic evaluation played a key role in patient safety. Conclusions: Studies indicate that pre-anesthetic evaluation is a key improver of surgical outcomes. These measures not only mitigate potential risks but also enhance surgical outcomes. Overall, pre-anesthetic evaluation has a direct correlation with patient safety, playing a significant role in postoperative improvement and elevating the quality of medical care.

A Study of the Optimal Logic Combinations of RO-Based PUFs on FPGAs to Maximize Identifiability.

One of the challenges that wireless sensor networks (WSNs) need to address is achieving security and privacy while keeping low power consumption at sensor nodes. Physically unclonable functions (PUFs) offer a challenge-response functionality that leverages the inherent variations in the manufacturing process of a device, making them an optimal solution for sensor node authentication in WSNs. Thus, identifiability is the fundamental property of any PUF. Consequently, it is necessary to design structures that optimize the PUF in terms of identifiability. This work studies different architectures of oscillators to analyze which ones exhibit the best properties to construct a RO-based PUF. For this purpose, Generalized Galois Ring Oscillators (GenGAROs) are used. A GenGARO is a novel type of oscillator formed by a combination of up to two input logical operations connected in cascade, where one input is the output of the previous operation and the other is the feedback signal. GenGAROs include some previously proposed oscillators as well as many new oscillator designs. Thus, the architecture of GenGAROs is analyzed to implement a GenGARO-PUF on an Artix-FPGA. With this purpose, an exhaustive study of logical operation combinations that optimize PUF performance in terms of identifiability has been conducted. From this, it has been observed that certain logic gates in specific positions within the oscillator contribute to constructing a PUF with good properties, and by applying certain constraints, any oscillator generated with these constraints can be used to construct a PUF with an equal error rate on the order of or below 10-11 using 100-bit responses. As a result, a design methodology for FPGA-based RO-PUFs has been developed, enabling the generation of multiple PUF primitives with high identifiability that other designers could exploit to implement RO-based PUFs with good properties.

The Prediction of Bond Strength Between Thin Steel Bars and Concrete Using an Adaptative Neuro-Fuzzy Inference System

In reinforced concrete, the solidary behaviour between steel and concrete means that tensile, compressive, bending, or torsional stresses are transferred from one material to another due to adhesion. Tests such as pull-out and beam tests, proposed by the EN:10080 standard, can be used to verify this behaviour; however, the difficulties inherent in destructive tests, as well as the non-linearity and number of variables involved in this issue, make it pertinent to use alternative methods. Using a database with experimental results from pull-out tests, the aim is to create an alternative technique to these tests. Hence, this work proposes the use of an Adaptive Neuro-Fuzzy Inference System (ANFIS) to predict the maximum adhesion load in pull-out tests. An ANFIS is a hybrid model made up of two techniques: Artificial Neural Networks (ANN) and Fuzzy Logic. The central idea in a Fuzzy Inference System is that the techniques work in parallel, with the neural network used to adjust fuzzy logic parameters. The combination of ANN and Fuzzy Logic is a useful approach to obtain the benefits of these systems in a single model, namely Neuro-Fuzzy. The Neuro-Fuzzy Inference System implemented in this work consists of four input variables: the surface of the bar, the diameter of the bar (ϕ), the compressive strength of the concrete (fc), and the length of the anchor (Ld). The output is the maximum adhesion force at the steel-concrete interface. The performance metrics obtained in this work will be evaluated against those obtained by other computational methods carried out earlier by our research group. The study indicates an alternative to the destructive tests that are widely carried out, overcoming their limitations considering the safety coefficients used in engineering.

Mental health among B2B salespeople: A morphological analysis

The intensely competitive landscape of B2B selling makes it highly susceptible to mental health issues (MHI) among the salespersons. MHI has a cascading impact on salespersons’ well-being, and ultimately on organizations’ performance and hence needs to be addressed as a priority. Despite a large body of knowledge on MHI in B2B sales, there is a lack of an integrated framework that could structure this knowledge for academic and managerial pursuits. This review addresses this gap by using morphological analysis (MA) to develop a framework that provides a systematic, modular, tabular-visual representation of MHI literature in B2B sales. Drawing on this framework, we develop a conceptual model that delineates key variables and allows their logical mapping and combination. Collectively, the MA framework and the model serve as a useful toolkit for academics and practitioners. They help to cultivate a clearer understanding of the state-of-the-art on MHI in terms of causal factors, manifestations, boundary conditions, coping resources, mitigation strategies, and theoretical orientation. They also facilitate the development of novel, interesting, and complex research questions for further empirical testing. Addressing these questions will contribute to theory building in support of creating and/or refining managerial strategies and organizational policies to address MHI among B2B salespersons more effectively.

DNA Nanolock-Based Logic Gate-Directed Reciprocal Feedback for Stepwise Cell Typing and Combination Treatment.

To achieve accurate molecular diagnosis and early-stage intervention of disease on demand, there is an urgent need for the monitoring of multiple biomarkers and multipath information acquisition in living cells. The DNA combinatorial logic gate is an appropriate strategy for providing a systematic proof of concept with comprehensive information and function. Herein, a modular DNA logic gate nanomachine is designed for sufficient multistep reciprocal cell identification and therapy via the iteration of simple logic operations. In this logic gate system, this main module is constructed by G-quadruplex-locked gold nanocages (AuNCs), serving dual functions of drug encapsulation and cell recognition. The logic system is composed of OR, XNOR, AND, and NOR gates employing two intracellular disease biomarkers (microRNA 21 and microRNA 155) as inputs and the fluorescence signal of doxorubicin (Dox) as an output. The output signals of the four logic gates are iterated to process the imaging analysis data from the complex matrix in the living cell. Via positive and negative reciprocal feedback, the series circuit of different gates enables different functions, including the preliminary screening and the distinction of the cell type. Through the mutual preliminary screening and further proof, this logic system achieves accurate identification of cells, controlled drug release, and photothermal treatment using the AuNC as a photothermal transducer. This DNA logic system broadens the applications of the biocomputing system in disease screening and logic-controlled treatment fields.

Using a discrete global grid system for a scalable, interoperable, and reproducible system of land-use mapping

ABSTRACT An accurate and timely land-use map of an area is a valuable geospatial dataset. Making one requires assembling heterogeneous geospatial input data. This becomes computationally expensive as the number of inputs grow or the combinational classification logic becomes more convoluted. We present as a solution an analytical framework based on a DGGS. This provides a spatial data structure that: facilitates horizontal scaling; improves geospatial data interoperability; and makes classified geospatial data easier to reproduce. We demonstrate a benchmark of land-use assignment with a DGGS against the vector and raster geospatial data models. Significant performance benefits are apparent over the vector case, while performance is equivalent to raster. Yet a DGGS has other compelling benefits that makes it more convenient to use in the domain of land-use assignment than the raster data model.

Self-Rectifying Self-Selecting Memory Having Bi-Layer Stacked Dual Functional Material for Logic-in-Memory

Recently, a 3D cross-point array (3DXP) consisting of phase-change random-access-memory (PCRAM) and ovonic threshold switching (OTS) selector has been reported as a memory solution for next-generation Compute-Express-Link (CXL) interconnect technology due to nonvolatile characteristics and high scalability1. Neverthless, a 3DXP has been faced limitations in implementing a vertically-stacked high-density memory array due to the high aspect ratio of the serial connection of two devices (i.e., PCRAM and OTS selector) and the thermal disturbance (TDB) problem between adjacent cells by using phase change materials. To oevrcome these limitations, self-selecting memory having polarity-induced threshold voltage (Vth) shift in chalcogenide-based dual functional material (DFM) has been proposed, presenting dual functions of selector and memory2–5. However, several problems should be improved such as the complex composition ratio of DFM, the electroforming process at high voltage, the intrinsic drift phenomenon by atomic rearrangements of pure chalcogenide materials, and the bi-directional current flow in the prograimming process (i.e., set and reset). In addtion, the CPU and GPU overload can be dramatically reduced when combinational logic gates (i.e., 16 Boolean logics) were implemented in the CXL expander via logic-in-memory.In this study, for the first time, we designed self-rectifying self-selecting memory (SR-SSM) having bi-layer stacked DFM for logic-in-memory. The designed SR-SSM demonstrated abrupt threshold switching at different voltages (i.e., Vth, set of 1.3 V and Vth, reset of 2.0 V) without electroforming-process. The abrupt threshold switching mechanism via the formation of conductive Cu filaments in DFM was proved by measuring the double-sweep DC I-V curves at near-cryogenic temperatures. In addtion, unlike the reported other SSMs, the filamentary switched SR-SSM presented a drift-free property due to the fast rupturing speed of the conductive Cu filaments under 50 ns in DFM. Finally, we implemented all 16 Boolean logic gates via a sequential logic scheme using one or two SR-SSMs. The polarity-induced Vth shift mechanism, electrical perfomance, and logic-in-memory application of the SR-SSM will be presented in detail. Acknowledgement This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MSIT) (No. RS-2023-00260527) and Institute of Information & communications Technology Planning & Evaluation (IITP) under the artificial intelligence semiconductor support program to nurture the best talents (IITP-(2023)-RS-2023-00253914) grant funded by the Korea government(MSIT). References Yi, J. et al. The chalcogenide-based memory technology continues: beyond 20nm 4-deck 256Gb cross-point memory. Dig. Tech. Pap. - Symp. VLSI Technol. 2023-June, 1–2 (2023).Hong, S. et al. Extremely high performance, high density 20nm self-selecting cross-point memory for Compute Express Link. Tech. Dig. - Int. Electron Devices Meet. IEDM 2022-Decem, 1861–1864 (2022).Ravsher, T. et al. Self-Rectifying Memory Cell Based on SiGeAsSe Ovonic Threshold Switch. IEEE Trans. Electron Devices 70, 2276–2281 (2023).Lee, J. et al. Enhancing Se-based Selector-only Memory with Ultra-fast Write Speed (~ 10 ns) and Superior Retention Characteristics (> 10 years at RT) via Material Design and UV Treatment Engineering. in 2023 International Electron Devices Meeting (IEDM) 1–4 (IEEE, 2024). doi:10.1109/iedm45741.2023.10413815.Park, I.-M. et al. Enhanced Endurance Characteristics in High Performance 16nm Selector Only Memory (SOM). in 1–4 (2024). doi:10.1109/iedm45741.2023.10413748.

Engineered Gate-Based Nanoscaled JK Flip-Flop: Design, Simulation and Applications

In this paper, we design and simulate a novel, highly compact and power-efficient silicon-based JK flip-flop (JKFF) employing an engineered gate technique, for the first time. Herein, the pull-down and the pull-up paths used to realize the JKFF have been realized by 4 and 2 engineered gate transistors, respectively (total six), whereas 8 pull-ups and 8 pull-down (total 16) transistors are used to realize the JK flip-flip in the conventional MOS technology. Two-dimensional (2D) calibrated mixed-mode simulations have revealed substantial improvement in various performance measuring parameters of the proposed JK flip-flop. The proposed technique has resulted in a significant reduction of 62.5% in transistor count, [Formula: see text]9.12% in power consumption, 2.5% decrease in delay and 11.38% in power delay product in comparison to the conventional JKFF realization. Further, the proposed gate-engineered JKFF has been used to realize highly compact D and T flip-flops. It has been observed that a 55.5% and 62.5% decrease in transistor count have been achieved in comparison to the conventional MOS-based JKFF realization of D and T flip-flops, respectively. A significant improvement in power consumption, delay, and power delay products has been achieved in the proposed D and T flip-flops in comparison to the conventional JKFF-based D and T flips. It has been observed that notably, the versatility of this approach allows for straightforward adaptation to realize various other sequential and combinational circuits. Besides, the process flow for the fabrication of the proposed engineered gate transistors for realizing the JKFF, D and T flip-flops has also been given.

3D Nano Hafnium‐Based Ferroelectric Memory Vertical Array for High‐Density and High‐Reliability Logic‐In‐Memory Application

AbstractA new type of ferroelectric memory device with high reliability and complementary metal‐oxide‐semiconductor (CMOS) compatibility characteristics is an important condition for achieving integrated memory and computing chips. Here, 3D stacked ferroelectric memory devices based on ferroelectric materials of HfO2 are fabricated. The device exhibits high speed (50 ns), low read voltage (0.5 V), and great reliability with no substantial degradation after 1010 cycles and a 10‐years data retention at 85 °C. The IMP and NAND logic are achieved with stable memory window (>200 mV) across the vertical devices’ interconnection. On this basis, combining with the traditional CMOS logic device, multiple combination logic functions containing NOT, AND, and NOR are achieved by simulation. The collaboration of devices in the vertical direction providing the possibility of combining multi‐bit logic in memory functions and paves the way for the implementation of high‐density, high‐reliability, and low‐energy consumption computing‐in‐memory chips compatible with the CMOS technology.

Institutional Complexity and Social Innovation: The Case of Chinese Social Enterprises

Abstract Social enterprises (SEs) have emerged throughout the world to address societal challenges through market-based activities and innovation. Research has focused on how SEs manage the tensions arising from the combination of social-welfare and market logics, neglecting the institutional complexity that arises in authoritarian regimes where the state plays a dominant role. Based on the institutional logics perspective and interview data of 42 SE leaders in China, we find that key tensions arise from the state and social-welfare logics and that state logic (re)configures the social–market relationships to be compatible. Chinese SEs employed depoliticization and localization to adapt to this unique form of institutional complexity in their social innovation efforts. This study advances research on SEs, institutional complexity, and hybrid organizing.

The combinatorics of Farey words and their traces

We introduce a family of 3 -variable ‘Farey polynomials’ that are closely connected with the geometry and topology of 3 -manifolds and orbifolds as they can be used to produce concrete realisations of the boundaries and local coordinates for one-dimensional (over \mathbb{C} ) deformation spaces of Kleinian groups. As such, this family of polynomials has a number of quite remarkable properties. We study these polynomials from an abstract combinatorial viewpoint, including a recursive definition extending that which is known in the literature for the special case of manifolds, even beyond what the geometry predicts. We also present some intriguing examples and conjectures which we would like to bring to the attention of researchers interested in algebraic combinatorics and hypergeometric functions. The results in this paper additionally provide a practical approach to various classification problems for rank 2 subgroups of \operatorname{PSL}(2,\mathbb{C}) since they, together with other recent work of the authors, make it possible to provide certificates that certain groups are discrete and free, and effective ways to identify relators.

Analyzing Multilayer Graphene Nanoribbon‐Based Via‐Interconnect Scheme: Prospects and Challenges for Monolithic 3D Integrated Circuits

This article presents a multilayer graphene nanoribbon (MLGNR)‐based single‐tier on‐chip nanoscale via‐interconnect scheme (VIS), which combines the vertical MLGNR via and horizontal MLGNR interconnect, as a prospect for monolithic 3D (M‐3D) integrated circuits (ICs). To go beyond the simplifying assumptions of perfect MLGNR and conventional skin‐effect, this study incorporates the impact of edge‐ and substrate‐induced scatterers in a realistic MLGNR and considers the 1D skin depth formula for MLGNR‐based on‐chip interconnect and via. A combined equivalent circuit model is developed to analyze the challenges induced by scatterers, skin‐effect, and crosstalk effect in perfect MLGNR VIS (P‐VIS) and realistic MLGNR VIS (R‐VIS). The results show that for width in the range of 5–30 nm, P‐VIS outperforms R‐VIS in terms of crosstalk delay. Moreover, at high frequencies ranging from 1 to 104 GHz with a width of 16 nm, R‐VIS demonstrates a performance decline of 243.18% (5.3934 × 103%) for L = 4.8 μm (1 mm), respectively, in comparison with P‐VIS. Hence, in order to leverage the potential of MLGNR‐based VIS for M‐3D ICs at high frequencies, it is imperative to integrate Li‐intercalation doping and mitigate the impact of edge and substrate scatterers in MLGNR.

Measurement of SET pulse width modulation in CMOS combinational logic by laser-induced fault injection

Measurement of SET pulse width modulation in CMOS combinational logic by laser-induced fault injection

UV LED Printing Device for PCB Fabrication

Photolithography is commonly used to fabricate printed circuit boards (PCBs) in micromanufacturing. It involves UV exposure to pattern portions of a thin film of a substrate before a geometric design is transferred from a photo mask to a light-sensitive substance (photoresist) on the substrate using light. Conventionally, metal halide lamps and UV fluorescent bulbs make up most of the exposure systems during photolithography. However, both systems are highly costly in educational establishments and consume high electrical energy. Moreover, they also have too broad UV radiation and are not appropriate for the sizes of PCBs that need to be mounted on the apparatus. Hence, this innovation aims to create a low-cost, portable UV exposure system that works well in educational settings by utilizing LED illumination technology. In order to manage time, relay, and LCD, these UV LED exposures were built using a combined LED circuit with a controller board. With a dimension of 120 mm by 190 mm and 3 mm LEDs, the UV LED circuit generates a wavelength of 400 to 405 mm for the UV exposure system. Due to its powerful and flexible design capabilities, LED lighting may be integrated in any shape to create highly efficient illumination. The testing result shows that LED lights have higher application efficiency due to its ability to concentrate light in one area. Therefore, well-designed LED illumination systems may deliver light to the intended spot more effectively. They also brighten up instantly when powered on and can be turned on and off repeatedly. This research has highlighted the advantages of LEDs for infrastructure projects, such as exposure systems, which could be further developed for future technology.

Groupoidal realizability for intensional type theory

Abstract We develop realizability models of intensional type theory, based on groupoids, wherein realizers themselves carry non-trivial (non-discrete) homotopical structure. In the spirit of realizability, this is intended to formalize a homotopical BHK interpretation, whereby evidence for an identification is a path. Specifically, we study partitioned groupoidal assemblies. Categories of such are parameterized by “realizer categories” (instead of the usual partial combinatory algebras) that come equipped with an interval qua internal cogroupoid. The interval furnishes a notion of homotopy as well as a fundamental groupoid construction. Objects in a base groupoid are realized by points in the fundamental groupoid of some object from the realizer category; isomorphisms in the base groupoid are realized by paths in said fundamental groupoid. The main result is that, under mild conditions on the realizer category, the ensuing category of partitioned groupoidal assemblies models intensional (1-truncated) type theory without function extensionality. Moreover, when the underlying realizer category is “untyped,” there exists an impredicative universe of 1-types (the modest fibrations). This is a groupoidal analog of the traditional situation.

EnR: extend and reduce methodology to enable formal verification of truncated adders

Abstract Truncated adders are widely used in applications where using lower bit-width is enough to generate the desired outputs. Truncated adders give benefits in area, power, and delay as compared to their non-truncated counterparts. While prior works deal with the formal verification of n-bit adders, there is no prior work dealing with the formal verification of unverified m-bit truncated adders using verified n-bit adder designs, where m < ${< } $ n. In this work, we propose a methodology that enables the verification for any truncated adder designs, irrespective of the architecture, called Extend and Reduce (EnR). EnR uses a three-step methodology to formally verify the truncated adders, which are considered as Design Under Verification (DUV). Firstly, it extends the bit-width of the DUV (truncated adder) to match with the nearest higher 2 n -bit adder, called an Extended Truncated Adder (ETA). Secondly, it reduces off-the-shelf formally verified golden reference adder design by forcing 0’s at the input bits to match it to the extended DUV design and re-synthesizing it to generate a Reduced Golden Adder (RGA). Lastly, a combinational equivalence check is then performed between the ETA and the RGA for formal verification. If the truncated adder is correct, the ETA and RGA are equivalent and vice versa. We evaluate a number and variety of adder designs to show the efficacy of the EnR methodology. We performed the formal verification using Binary Decision Diagrams (BDDs) and And-Inverter Graphs (AIGs). Lastly, we show the scalability of EnR methodology using adders up to a bit-width of 512 bits. ACM CCS Hardware → Arithmetic and datapath circuits; Combinational circuits; Equivalence checking; Functional verification; Electronic design automation.