Column Driver Research Articles

670-nA CMOS OTA FOR AMLCD COLUMN DRIVER

A transconductance operational amplifier specifically optimized for a switched-capacitor LCD column driver is presented. It exploits MOS transistors in subthreshold region and dissipates 670 nA at DC. Despite this extremely low quiescent current value, the amplifier exhibits a DC gain of about 80 dB, and a gain-bandwidth product and phase margin around 2 MHz and 70°, with a load capacitance of 500 fF. Besides, working in class AB, the solution provides a slew rate equal to 27 V/μs. With exception of the DC gain, these performances represent an improvement with respect to comparable solutions, and are obtained while halving the area occupation.

A cost‐effective 60hz FHD LCD using 800Mbps AiPi technology

AiPi technology incorporates an embedded clock and control scheme with a point‐to‐point bus topology, thereby having the smallest possible number of interface lines between a timing controller and column drivers. A point‐to‐point architecture boosts the data rate and reduces the number of interface lines, because impedance matching can be easily achieved. An embedded clock and control scheme is implemented by means of multi‐level signalling, which results in a simple clock/data recovery circuitry. A 46” AiPi‐based 10‐bit FHD prototype requires only 20 interface lines, compared to 38 lines for mini‐LVDS. The measured maximum data rate per data pair is more than 800 Mbps.

Circuit-Level Impact of a-Si:H Thin-Film-Transistor Degradation Effects

This paper reviews amorphous silicon thin-film-transistor (TFT) degradation with electrical stress, examining the implications for various types of circuitry. Experimental measurements on active-matrix backplanes, integrated a-Si:H column drivers, and a-Si:H digital circuitry are performed. Circuit modeling that enables the prediction of complex-circuit degradation is described. The similarity of degradation in amorphous silicon to negative bias temperature instability in crystalline PMOS FETs is discussed as well as approaches in reducing the TFT degradation effects. Experimental electrical-stress-induced degradation results in controlled humidity environments are also presented.

Si-based emissive microdisplays

Standard silicon microelectronics technology is very attractive for use in microdisplays, because it is the shortest way to highest pixel densities and integration of matrix with column and row drivers into a common chip. Use of nanostructured silicon light-emitting diodes (Si LEDs) may completely solve the problem of low compatibility of display elements and silicon chip. At present time the most suitable kinds of Si LEDs are porous silicon avalanche LEDs. They have such advantages as long operation lifetime, continuous spectrum, low operation voltages and extremely sharp voltage–current characteristic, nanosecond response time and high operation current density. This paper considers the background, approaches and achievements in design of the silicon-based LEDs and high-resolution matrix displays.

P‐57: A 10‐Bit TFT‐LCD Column Driver with Hybrid Digital to Analog Converters

AbstractA 10‐bit TFT‐LCD column driver with hybrid DACs is proposed. The data conversion is implemented by an R‐DAC and a C‐DAC, which are used for the MSB and LSB data conversions, respectively. The simulated results show that the DAC exhibits the maximum DNL and INL of 0.28 LSB and 0.35 LSB, respectively. The settling time is within 4 μs. The areas for one R‐DAC and one C‐DAC are 0.438 × 1.063 mm2 and 0.207 × 0.11 mm2, respectively.

58.3: Area and Power Efficient 10‐bit Column Driver with Interpolating DAC and Push‐Pull Amplifier for AMLCDs

AbstractA channel interpolating digital‐to‐analog converter (DAC) and push‐pull buffer amplifiers are presented for area and power efficient 10b column drivers in large‐Sized AMLCDs. The interpolating circuit occupies an area of 110μm × 35μm for 3b data generation and wastes no additional static power. The measured INL / DNL were ± 0.6 LSB and ± 0.55 LSB, respectively, for a 3b interpolating DAC. The push‐pull buffer amplifiers consume 2.3μA of static current per channel at a slew rate of 14∼18V/μs in a 0.35μm 3.3V CMOS process.

58.4: 10‐Bit Column Driver with Split‐DAC Architecture

AbstractAn 8‐bit coarse digital‐to‐analog converter (DAC), which adopts both array and tree‐type decoders, is combined with a 2‐bit fine interpolation DAC to reduce RC time delay and die area of a column driver for LCD‐HDTV applications. Error amplifiers drive a pair of column lines in the output buffer to realize rail‐to‐rail voltage swing with a high slew rate. The design has been fabricated in 0.3 μm LV‐HV CMOS technology.

30.2: Active Matrix Electrophoretic Displays on Temporary Bonded Stainless Steel Substrates with 180 °C a‐Si:H TFTs

AbstractA low temperature, 180 °C, amorphous Si (a‐Si:H) process on bonded stainless steel substrates is discussed and a 3.8‐inch QVGA active matrix (AM) electrophoretic display as well as a 64×64 electrophoretic display with integrated column drivers are demonstrated. The n‐channel thin‐film transistors (TFTs) exhibited saturation mobilities of 0.7 cm2/V‐sec, median drive currents of 26.2 μA and low defectivity.

Design considerations of channel buffer amplifiers for low-power area-efficient column drivers in active-matrix LCDs

The performance criteria and corresponding design specifications for channel buffer amplifiers in state-of- the-art column driver ICs of active-matrix LCD (AMLCD) applications are presented. And the relationships between the amplifier characteristics and the display image quality are defined. In addition, several display patterns and their driving waveforms that enable the prediction of the performance of channel buffer amplifiers in real panel applications are presented.

Thin-film inverters based on high mobility microcrystalline silicon thin-film transistors

Thin-film inverters based on high mobility microcrystalline silicon thin-film transistors (TFTs) with different channel lengths were realized. The NMOS enhancement load saturation mode (NELS) inverters were prepared by plasma-enhanced chemical vapor deposition at temperatures below 200°C. The realization of microcrystalline silicon thin-film inverters facilitates the direct integration of column and row drivers and circuitry on display backpanels. The influence of the transistor properties and underlying contact effects on the performance of the inverters will be discussed.

Counting-Based Digital-to-Analog Converter Scheme for Compact Column Driver with Low-Temperature Polycrystalline Silicon Thin-Film Transistors

The concept of a counting-based digital-to-analog converter (CNT-DAC) is proposed to realize a compact column driver circuit for system-on-panel (SoP) applications. The traditional ramp DAC is very promising in the circuit-area respect, because it replaces the area-consuming read only memory (ROM)-type decoder with a counter; however, it is not widely used for display column drivers because it has several problems such as ramp signal distortion, charge sharing between column lines and pixel electrode and ramp signal generation. The CNT-DAC was inspired by the ramp DAC, which uses a counter instead of an area-consuming ROM-type decoder but can avoid the problems mentioned above by using a resistor string at each channel and a global shift register. Instead of designing an 8-bit DAC with the counting-based DAC alone, we combine the 3-bit traditional decoder-based DAC and the 5-bit CNT-DAC, because the 8-bit CNT-DAC needs a clock frequency of about 20 MHz for a portrait qVGA format (H: 240, V: 320), which is a fairy difficult requirement to meet. For a 2-in. diagonal portrait qVGA AMOLED panel, the circuit area of one channel DAC is 73×1,010 µm2 with the design rule of 2 µm and a TFT channel length of 4 µm. The total power consumption of the CNT-DAC is about 3.2 mW; the static power consumption due to the resistor string at each channel is 1.7 mW, the dynamic power consumption for driving the column lines is about 1.0 mW, and the global shift register consumes about 0.5 mW.

Novel 120‐Hz TFT‐LCD motion‐blur‐reduction technology with integrated motion‐compensated frame‐interpolation timing controller

Abstract— Samsung has developed a high‐resolution full‐HD (1920 × 1080) 120‐Hz LCD‐TV panel using a novel pixel structure and a motion‐compensated frame‐interpolation (McFi) single‐chip solution. Our latest work includes launch of a 70‐in. full‐HD panel, the world's largest LCD TV in mass production, with a 120‐Hz frame rate. A serious problem involving the charging time margin has been completely overcome through the use of a new alternative 1G‐2D pixel structure and a new driving scheme. Compared with conventional dot‐inversion driving, our new dot‐inversion method, which is a spatial averaging technique, can save power because the column drivers are operated using vertical inversion driving. In addition, McFi, which merges individual ME/MC and timing‐controller (TCON) ICs and memories, has been developed and applied in a mass‐production product for the first time ever. The McFi solution provides 120‐Hz driving with the lowest possible system cost. Motion‐picture response time (MPRT) has been reduced from 1 5 to 8 msec. Moreover, for the case of 24‐Hz film source mode, motion judder has been completely eliminated. As a result, a lineup consisting of 40‐, 46‐, 52‐, 70‐, and 82‐in. LCD‐TV panels with high quality and manufacturability has been made possible.

On-time modulation for liquid crystal displays with insufficient charging time

I propose on-time modulation (OTM) to compensate for insufficient time to charge column lines in liquid crystal displays (LCDs). OTM modulates turn-on times of row signals as a function of column signal delay. Most LCD panels for monitors and laptop computer displays adopt a two-line inversion. OTM extends turn-on times of even row signals and reduces pulse widths of the next odd rows. Experimental results showed that turn-on times of even row signals should be unequally extended in accordance with a distance of the row from a column driver. Because OTM successfully solves the charging time problem, it contributes to the success of 120-Hz driving, which has been widely investigated to solve motion blur in LCDs, but has a very severe charging problem.

A 10-Bit LCD Column Driver With Piecewise Linear Digital-to-Analog Converters

A 10-bit LCD column driver, consisting of piecewise linear digital to analog converters (DACs), is proposed. Piecewise linear compensation is utilized to reduce the die area and to increase the effective color depth. The data conversion is carried out by a resistor string type DAC (R-DAC) and a charge sharing DAC, which are used for the most significant bit and least significant bit data conversions, respectively. Gamma correction voltages are applied to the R-DAC to lit the inverse of the liquid crystal trans-mittance-voltage characteristic. The gamma correction can also be digitally fine-tuned in the timing controller or column drivers. A prototype 10-bit LCD column driver implemented in a 0.35-mum CMOS technology demonstrates that the settling time is within 3 mus and the average die size per channel is 0.063 mm2, smaller than those of column drivers based exclusively on R-DACs.

A Gray-Level Dependent Pre-Emphasis Column Driver With Fast Settling for Active-Matrix LCD Applications

In this brief, simple analytical solutions for pre-emphasis driving conditions in active-matrix liquid crystal display (AMLCD) applications are presented. According to the solutions presented, the column driver with a gray-level dependent pre-emphasis (GLDP) function is designed for fast settling. The GLDP column driver is implemented without using additional frame memory. Also, modifications to the display system and integrated circuit fabrication process changes are not required. The GLDP column driver provides output voltage signals with variable pre-emphasis durations according to the magnitude of the gray-level shift to be driven. By applying the GLDP column driver, 8-mus reduction of the required one row line time was achieved on average. This one row line time reduction makes it possible to realize high performance and low cost AMLCDs. The 640 channel, full function GLDP column driver is fabricated by a 13.5-V 0.35-mum CMOS process.

Transistor Sizing of LCD Driver Circuit for Technology Migration

Design automation of LCD driver circuits is not sophisticatedly established. Display fineness of an LCD panel depends on a performance metric, ratio of pixel voltage to video voltage (RPV). However, there are several other important metrics, such as area, and the best circuit cannot be decided uniquely. This paper proposes a design automation technique for a LCD column driver to provide several circuit design results with different performance so that designers can select an appropriate design among them. The proposed technique is evaluated with an actual design data, and experimental results show that the proposed method successfully performs technology migration by transistor sizing. Also, the proposed technique is experimentally verified from points of solution quality and computational time.

A High Speed and Low Chip Surface Temperature Column Driver for Large TFT LCD TV Applications

Power consumption increment in column driver IC that drives the large TFT LCD panel, makes chip surface temperature higher and is the root cause of shortening the chip life time and package burn-out. To reduce the surface temperature of column driver IC, a new driving scheme has been developed to cut down panel AC power which is the largest portion of power consumption of column driver IC. Compared with the previous charge sharing method, proposed new driving method reduces the power consumption in the chip up to 50% that of conventional ones and decreases the surface temperature and increases the driving speed of the column driver IC. This method has been designed and verified by HSPICE simulation and applies to 8-bit 720-outputs column driver IC. Test chips with the proposed and conventional method have been fabricated in a 0.35 mum 18 V high voltage CMOS technology. Experiments have been performed with 37-inch WXGA TFT LCD TV panel that mounted the fabricated column driver IC. Experimental results show that power consumption in the chip, driving speed and chip surface temperature of the proposed driver, is 14.5% smaller, almost 4~5degC lower and about 0.93 us shorter than that of conventional charge sharing method, respectively.

P‐43: A Multi‐Chip Reference Current Generating Circuit for Current‐Mode Column Driver ICs

AbstractA reference current generating circuit is proposed for current‐mode displays using plural column driver ICs. The circuit supplies the uniform current with the column drivers. The cascaded circuits use an input reference current, sense it, and independently generate output currents in accordance with the current. The variation of generated output current in the reference current generating circuit of each column driver IC is reduced as compared with the conventional method. The generated output currents in column drivers have 0.1% error to the input reference current.

P‐42: A 10 bit Gray Scale Digital‐to‐Analog Converter with an Interpolating Buffer Amplifier for AMLCD Column Drivers

AbstractA 10 bit digital‐to‐analog converter (DAC) with an interpolating buffer amplifier is proposed for AMLCD column drivers. The proposed circuit is more effective than a conventional circuit in decreasing the DAC (Pass‐Transistor Logic) area per channel. The average static current per channel is 1.8 μA and the average interpolating error rate in most of the gray range is a sufficiently small rate of 2.5 % (and less than 0.5 % in the mid‐gray range). The uniformity of the channel output is also guaranteed by the proposed error‐reduction technique.

A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays

In the design of an active matrix LCD (Liquid Crystal Display), the ratio of the pixel voltage to the video voltage (RPV) of a pixel is an important factor of the performance of the LCD, since the pixel voltage of each pixel determines its transmitted luminance. Thus, of practical importance is the issue of how to maintain the admissible allowance of RPV of each pixel within a prescribed narrow range. This constraint on RPV is analyzed in terms of circuit parameters associated with the sampling switch and sampling pulse of a column driver in the LCD. With the use of a minimal set of such circuit parameters, a design procedure is described dedicatedly for the sampling switch, which intends to seek an optimal sampling switch as well as an optimal sampling pulse waveform. A number of experimental results show that an optimal sampling switch attained by the proposed procedure yields a source driver with almost 18% less power consumption than the one by manual design. Moreover, the percentage of the RPVs within 100±1% among 270 cases of fluctuations is 88.1% for the optimal sampling switch, but 46.7% for the manual design.