Coherence Overhead Research Articles

A Performance Study on Bounteous Transfer in Multiprocessor Sectored Caches

In a sectored cache, a cache line is divided into several subblocks. Each subblock is a basic coherence unit. In this way partial block invalidation can be done on the cache lines in order to eliminate false sharing on invalidate-based multiprocessors. Sectored caches often include a facility, called bounteous transfers, to supply extra subblocks after transferring the missed subblock on a read miss. Unfortunately, previous works on sectored caches concentrated mainly on solving the false sharing problem, while overlooked the prefetching effects of bounteous transfer. In this paper, we evaluate the performance impacts of bounteous based on a MESI-based sectored cache. Three different types of bounteous transfer are evaluateds bounteous transfer wuth valid subblocks (BT-V), bounteous transfer with clean subblocks (BT-C), and bounteous disabled (No-BT). We simulated the execution of typical benchmarksFFT, LU, Radix, SOR, on the MESI-based sectored cache. Two metrics U-rate and R-rate are proposed to help observe the sharing granularities and coherence overhead. Evaluation results show that different benchmarks work better with different kinds of bounteous transfer and using bounteous transfer carelessly may result in performance degradation.

Hiding communication latency and coherence overhead in software DSMs

In this paper we propose the use of a PCI-based programmable protocol controller for hiding communication and coherence overheads in software DSMs. Our protocol controller provides three different types of overhead tolerance: a) moving basic communication and coherence tasks away from computation processors; b) prefetching of diffs; and c) generating and applying diffs with hardware assistance. We evaluate the isolated and combined impact of these features on the performance of TreadMarks. We also compare performance against two versions of the Shrimp-based AURC protocol. Using detailed execution-driven simulations of a 16-node network of workstations, we show that the greatest performance benefits provided by our protocol controller come from our hardware-supported diffs. Reducing the burden of communication and coherence transactions on the computation processor is also beneficial but to a smaller extent. Prefetching is not always profitable. Our results show that our protocol controller can improve running time performance by up to 50% for TreadMarks, which means that it can double the TreadMarks speedups. The overlapping implementation of TreadMarks performs as well or better than AURC for 5 of our 6 applications. We conclude that the simple hardware support we propose allows for the implementation of high-performance software DSMs at low cost. Based on this conclusion, we are building the NCP 2 parallel system at COPPE/UFRJ.

Hiding communication latency and coherence overhead in software DSMs

In this paper we propose the use of a PCI-based programmable protocol controller for hiding communication and coherence overheads in software DSMs. Our protocol controller provides three different types of overhead tolerance: a) moving basic communication and coherence tasks away from computation processors; b) prefetching of diffs; and c) generating and applying diffs with hardware assistance. We evaluate the isolated and combined impact of these features on the performance of TreadMarks. We also compare performance against two versions of the Shrimp-based AURC protocol. Using detailed execution-driven simulations of a 16-node network of workstations, we show that the greatest performance benefits provided by our protocol controller come from our hardware-supported diffs. Reducing the burden of communication and coherence transactions on the computation processor is also beneficial but to a smaller extent. Prefetching is not always profitable. Our results show that our protocol controller can improve running time performance by up to 50% for TreadMarks, which means that it can double the TreadMarks speedups. The overlapping implementation of TreadMarks performs as well or better than AURC for 5 of our 6 applications. We conclude that the simple hardware support we propose allows for the implementation of high-performance software DSMs at low cost. Based on this conclusion, we are building the NCP 2 parallel system at COPPE/UFRJ.

Dynamic self-invalidation

This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages by having a processor automatically invalidate its local copy of a cache block before a conflicting access by another processor. Eliminating invalidation overhead is particularly important under sequential consistency, where the latency of invalidating outstanding copies can increase a program's critical path.DSI is applicable to software, hardware, and hybrid coherence schemes. In this paper we evaluate DSI in the context of hardware directory-based write-invalidate coherence protocols. Our results show that DSI reduces execution time of a sequentially consistent full-map coherence protocol by as much as 41%. This is comparable to an implementation of weak consistency that uses a coalescing write-buffer to allow up to 16 outstanding requests for exclusive blocks. When used in conjunction with weak consistency, DSI can exploit tear-off blocks---which eliminate both invalidation and acknowledgment messages---for a total reduction in messages of up to 26%.

A HYBRID COHERENCE SCHEME FOR SOFTWARE DISTRIBUTED SHARED MEMORY

Software distributed shared memory (DSM) provides a convenient and effective solution for programming parallel applications on distributed systems. However, the performance of current implementations suffers from large overhead in enforcing memory coherence. Coherence faults are the sources of massive network traffic. Various memory consistency models have been proposed in order to eliminate the effects of network traffic and memory latency. In this paper, we present a novel approach that combines relaxed memory consistency models and a compiler strategy to solve memory coherence problems for DSM. This approach produces fewer coherence faults. Experimental results also show this hybrid approach is effective for reducing the memory coherence overhead of DSM.

Design of an adaptive cache coherence protocol for large scale multiprocessors

A large scale, cache-based multiprocessor that is interconnected by a hierarchical network such as hierarchical buses or a multistage interconnection network (MIN) is considered. An adaptive cache coherence scheme for the system is proposed based on a hardware approach that handles multiple shared reads efficiently. The new protocol allows multiple copies of a shared data block in the hierarchical network, but minimizes the cache coherence overhead by dynamically partitioning the network into sharing and nonsharing regions based on program behavior. The new cache coherence scheme effectively utilizes the bandwidth of the hierarchical networks and exploits the locality properties of parallel algorithms. Simulation experiments have been carried out to analyze the performance of the new protocol. The simulation results show that the new protocol gives 15% to 30% performance improvement over some existing cache coherence schemes on similar systems for a wide range of workload parameters. >

Shared block contention in a cache coherence protocol

Simulation is used to analyze shared block contention in eight parallel algorithms and its effects on the performance of a cache coherence protocol under the assumption of infinite cache sizes. A simple program model for data and block sharing is introduced, and an analytical closed-form solution is found for all components of the cache coherence overhead. This model is based on the observation that shared writable blocks are accessed in critical or in semicritical sections. The program model is applied to the analysis of multiprocessor systems with finite cache sizes and for steady state computations. The authors compare the model predictions to the results of execution-driven simulations of eight parallel algorithms. The simulation is conducted for various numbers of processors and different cache block sizes.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Simplicity versus accuracy in a model of cache coherency overhead

The important factors building a model of coherency overhead for a single-bus, shared memory multiprocessor are analyzed. Three architectural features are examined: the size of the coherency block, the cache size, and the type of bus operation used to carry out a particular coherency function. The experiments judge the effect of each architectural parameter on model accuracy by selectively including it in a base model and then comparing the model's predictions of coherency overhead to the results of detailed multiprocessor simulations. The results indicate that coherency block size is critical to include in a model of coherency overhead. This improves the accuracy of the base model by a factor of approximately 5-50, depending on the application. Cache size and the type of coherency-related bus operation are less important, contributing a 1.5% (for 128 kbyte caches) and 6% improvement, respectively, averaged over all traces. >

A characterization of sharing in parallel programs and its application to coherency protocol evaluation

In this paper we use trace-driven simulation to analyze the memory reference patterns of write shared data in several parallel applications. We first develop a characterization of write sharing (based on the notion of a write run), and then examine the traces, using metrics derived from the characterization. The results indicate that the amount of write sharing in all programs is small; and that it is characterized by short to medium sequences of per processor references, with little contention for either data or locks. We determine to what extent this analysis can be used to predict the coherency overhead of write-invalidate and write-broadcast protocols. We develop a simple model of write sharing from the write run characterization. By applying the results of the sharing analysis to the model, weighted by machine-specific cycle costs for carrying out coherency-related bus operations, we can estimate relative protocol performance. We compare these results to those from detailed architectural simulations. The simulation results indicate that (1) neither protocol dominates in performance; and that (2) the write run model is a good predictor of protocol performance when the unit of the coherency operations matches that in the sharing analysis. This is the case for the write-broadcast protocols, in which one word is broadcast for each write to shared data. However, in Berkeley Ownership, a write-invalidate protocol, the unit of coherency is an entire cache block. When the block size is large, performance for this protocol is quite sensitive to the memory reference patterns within the block.

A cache-based multiprocessor with high efficiency

Shared-memory multiprocessors to support concurrent languages for general-purpose multitasked systems are analyzed. To solve the traditional performance problems caused by memory access latency and conflicts, extensive caching of instructions and data is performed in each processor mode. Caches are private to each processor, and coherence is maintained in hardware between the caches. To maintain a good efficiency, several contexts are resident in each processor. On a miss in the cache, a microswitch to another resident context is operated by changing the program counter and a pointer in the register memory. The instruction set of each processor is RISC-like, so that a microswitch should waste few machine cycles. The proposed system has high efficiency, even when the number of processors increases and when the coherence overhead and conflicts are high. Models are developed to evaluate throughput and efficiency.