Codec Circuit Research Articles

QCA-based Hamming code circuit for nano communication network

Quantum-dot cellular automata (QCA) is one of the most promising technologies for designing digital circuits with high integration, ultra-low energy consumption, and high switching speed. The efficient implementation based on QCA has been verified in some nanocommunication code circuits. In this manuscript, a bottom-up method is adopted to design and implement novel 3–8 and 4–16 decoders. Based on the proposed structure, (7,4) and (15,11) Hamming codec circuits are implemented. The general design method of QCA Hamming code communication network is also given. For different generator matrices in Hamming codes, the proposed design only needs to modify the corresponding interconnection lines in the communication network without major adjustments to the circuit structure to achieve the same function. Compared with the Hamming code related designs in other studies, the proposed design has better hardware complexity. The proposed Hamming code circuit has a great performance improvement in terms of cell number, area, and clock delay. The above designs have been functionally verified by the QCADesigner.

Chaos based blood glucose noninvasive measurement: new concept and custom study

Background. Non invasive monitoring of Blood Glucose (BG) has been a challenge calling for new accurate and fast measurement methods. Objective. To propose new concept of chaos based BG non invasive test aiming at personal customization requirements. Methods. First to build the compact RC model of tissue BG through impedance precision measuring Kit, then to simulate and soft-test BG by Boolean chaotic Codec circuits in soft tool Multisim 13.0, The third to capture the chaotic decoding outputs with the Kit plus PC in calculated signatures of resistor and phase of the tested impedance at the subjects’ left wrist in synchronous test by Bayer BG meter. Results. All in controlled trials of Bayer BG meter, the chaotic BG modelling had gained three new compared formulae in merits of errors less than 1mmol/L and latency less than 1minute. Conclusion. During further verification of this chaotic test paradigm, the opened logic route of above methods will boost measurement experts’ confidence in overcoming future problems of blood glucose monitoring in vivo.

A CMOS MEMS Audio Transducer Implemented by Silicon Condenser Microphone With Analog Front-End Circuits of Audio Codec

This study proposes a CMOS MEMS audio transducer implemented by combining a silicon condenser microphone with analog front-end audio codec circuits. The proposed CMOS MEMS audio transducer is attractive because the sensor and all the circuits are robustly and compactly integrated. The overall size of the proposed device is much smaller than traditional electrets-condenser microphones (ECMs). Another innovation of the proposed CMOS MEMS audio transducer is that it can operate without any charge pump circuits, which overcomes the problem of requiring a high bias voltage. Measurement results confirm the correct functions and performance of the proposed CMOS MEMS audio transducer. The area of the proposed CMOS MEMS audio transducer is 1352×1410 μm2 and the FOM of the proposed sigma-delta modulator is 148 dB. The proposed CMOS MEMS audio transducer is suitable for audio devices, such as audio codecs.

Cellular Phone, And Codec Circuit And Receiving Call Sound Volume Automatic Adjustment Method For Use In Cellular Phone

Provided is a cellular phone enabling improvement of the level of a sense of hearing of a pseudo noise which is generated when there exists no voice signal. In the cellular phone, frame type information included in a baseband signal “in” is identified by the frame type identification unit 71 and when the frame type information represents pseudo noise information, a pseudo noise signal generated by the AMR (Adaptive Multi-Rate) decoder 72 with an internal pseudo noise generator is output to the call receiver unit 43 with its level reduced by a predetermined amount by the signal level change amount calculation unit 74 and the signal level change unit 73 , while when the frame type information represents a voice signal, the voice signal decoded by the AMR (Adaptive Multi-Rate) decoder 72 with an internal pseudo noise generator is output to the call receiver 43 with its level unchanged.

Coding for reliable on-chip buses: a class of fundamental bounds and practical codes

A reliable high-speed bus employing low-swing signaling can be designed by encoding the bus to prevent crosstalk and provide error correction. Coding for on-chip buses requires additional bus wires and codec circuits. In this paper, fundamental bounds on the number of wires required to provide joint crosstalk avoidance and error correction using memoryless codes are presented. The authors propose a code construction that results in practical codec circuits with the number of wires being within 35% of the fundamental bounds. When applied to a 10-mm 32-bit bus in a 0.13-μm CMOS technology with low-swing signaling, one of the proposed codes provides 2.14× speedup and 27.5% energy savings at the cost of 2.1× area overhead, but without any loss in reliability.

Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes

A reliable high-speed bus employing low-swing signaling can be designed by encoding the bus to prevent crosstalk and provide error correction. Coding for on-chip buses requires additional bus wires and codec circuits. In this paper, fundamental bounds on the number of wires required to provide joint crosstalk avoidance and error correction using memoryless codes are presented. The authors propose a code construction that results in practical codec circuits with the number of wires being within 35% of the fundamental bounds. When applied to a 10-mm 32-bit bus in a 0.13-mum CMOS technology with low-swing signaling, one of the proposed codes provides 2.14times speedup and 27.5% energy savings at the cost of 2.1times area overhead, but without any loss in reliability

24.4: A 510-Kb SOG-DRAM for Frame-Memory-Integrated Displays

A system-on-glass (SOG) DRAM intended for integrated frame-memories of 262k-color QCIF+ displays has been developed. An integrated codec circuit reduces the number of memory cells and layout area by a factor of 2/3. By combining the SOG-DRAM, which has a data retention time of over 16.6 ms, with an embedded controller that enables simultaneous access for writing and reading, a frame-memory has been created. The operation was verified by chip measurement and demonstration.

Design of a low-power real-time wavelet CODEC circuit

Abstract This paper presents the architecture and design of a CODEC circuit that can compress and reconstruct 4:2:2 color VGA video images using two-dimensional DWT. For real-time operation and low-power consumption, we modified the traditional Mallat's sub-band coding method to reduce the amount of computation required in two-dimensional DWT. Using the modified method, two-dimensional DWT can be performed by two sets of one-dimensional DWT operations regardless of the number of decomposition levels. We adopted the systolic array architecture to design the circuit implementing our method. Our low-power real-time CODEC circuit was designed using Verilog HDL and fabricated as a VLSI chip using 0.35 μm 3.3 V CMOS standard cell process. We made a simple DVR system using our CODEC chip to store and retrieve the video image data to and from the hard disk, and observed successful real-time operations.

A bipartition-codec architecture to reduce power in pipelined circuits

This paper proposes a new approach to synthesize pipelined circuits with low-power consideration. We treat each output value of a combinational circuit as one state of a finite-state machine (FSM). If the output of a combinational circuit transits mainly among some few states, we could extract those states (output) and the corresponding input to build a subcircuit. After bipartitioning the circuit, we apply the encoding technique to the highly active subcircuit for further power reduction. In this paper, we formulate the bipartition problem and present a probabilistic-driven algorithm to bipartition a circuit so as to minimize the power dissipation. Our experimental results show that an average power reduction on several Microelectronic Center of North Carolina (MCNC) benchmarks of 31.6% is achievable.

Reed-Solomon VLSI codec for advanced television

A VLSI implementation of a Reed-Solomon codec circuit is reported. The 1.6- mu m double metal CMOS chip is 8.2 mm by 8.4 mm, contains 200000 transistors, operates at a sustained data rate of 80 Mbits/s and executes up to 1000 MOPS while consuming less than 500 mW of power. The 10-MHz sustained byte rate for the data is independent of the error pattern. The circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths of 255 bytes as well as shortened codes are supported with no external buffering. Erasure corrections as well as random error corrections are supported with selectable correction of up to ten symbol errors. Corrected data is output at a fixed latency. These features make this Reed-Solomon processor suitable for use in advanced television systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Integrated PCM Codec

A one-chip PCM codec circuit has been implemented in the CMOS process. The design uses two separate linear digital-digital-to-analog converters, made with charge redistribution techniques. Experimental results show the circuit to meet accepted requirements and operate with very low power requirements.

Integrated PCM codec

Describes a one-chip PCM codec circuit which has been implemented in the CMOS process. The design uses two separate linear digital-to-analog converters, made with charge redistribution techniques. Experimental results show the circuit to meet accepted requirements and operate with very low power requirements.