Code Density Test Research Articles

Cross-Talk Issues in Time Measurements

The enormous diffusion of Time-Mode circuits, in particular Time-to-Digital Converter (TDC) time measurement circuits, and at the same time the dizzying increase in parallel channels required by the most recent applications, for example in the automotive and digital imaging fields, brings the problem of electromagnetic interference between channels ever more to the fore. This phenomenon, generally known as Cross-Talk (XT), is particularly critical given the increase in the operating frequency and density of systems components, and its effect on the timing parameters in TDC measurements is investigated. Considering the time measurements, XT creates temporal shift on the physical events from which the timestamps are extracted; in this manner, an error in the measurements is generated. In order to detect the XT phenomena, a methodical analysis based on Code-Density Test (CDT) is performed; in this terms, two different typologies of XTs are investigated, which are correlated and uncorrelated XT. Furthermore, a TDC board is used as case study and all the XT sources are detected and classified. Thus, a classification of the importance of the different sources of XT is achieved and a solution to minimize the different causes is proposed.

A high precision TDC design based on FPGA+ARM

In this paper, a high precision time digital converter(TDC) is designed based on FPGA and ARM, It includes coarse module, delay chain module, look-up-table module, ringosc moduleand spi module in the FPGA chip. The ARM chip is used for reading the timestamp and printing through the serial port. The key technology of this design is using the CARRY4 block of Xilinx Aritex-7 series to construct a delay chain for finecount. The system clock is used as the coarse count. The timestamp is obtained by the combination of fine time and coarse time.In addition, the precison of TDC is improved by code density test. The experiment result shows that precision of TDC is 43.2ps.

Run‐time calibration scheme for the implementation of a robust field‐programmable gate array–based time‐to‐digital converter

SummaryIn this study, we propose a robust field‐programmable gate array (FPGA)–based time‐to‐digital converter (TDC) with run‐time calibration. A code density test was used for differential nonlinearity (DNL) calibration to deal with nonuniformity in delay cells. The proposed calibration scheme is implemented as a four‐step finite state machine (FSM) for run‐time calibration. We implemented the TDC with the proposed run‐time calibration circuit on the Xilinx 65‐nm FPGA platform. This improved the DNL and integral nonlinearity (INL) values over those obtained using a TDC without run‐time calibration circuit. The DNL and INL values at a time resolution of 46.875 picoseconds were [−0.68, 1.04] and [−4.27, 2.27] least significant bits, respectively. More than 30% DNL and INL improvements are achieved for the TDC with calibration circuit. The results obtained at temperatures of 27°C to approximately 70°C indicated that the proposed run‐time calibration circuit enhanced the capability of the FPGA‐based TDC against temperature effects. The FPGA‐based TDC with the proposed run‐time calibration FSM provides robust high‐resolution performance suited for a range of scientific applications.

Multichannel, Low Nonlinearity Time-to-Digital Converters Based on 20 and 28 nm FPGAs

This paper presents low nonlinearity, compact, and multichannel time-to-digital converters (TDC) in Xilinx 28 nm Virtex 7 and 20 nm UltraScale field-programmable gate arrays (FPGAs). The proposed TDCs integrate several innovative methods that we have developed: 1) the subtapped delay line averaging topology; 2) tap timing tests; 3) a direct compensation architecture; and 4) a mixed calibration method. The code density tests show that the proposed TDCs have much better linearity performances than previously reported ones. Our approach is cost-effective in terms of the consumption of logic resources. To demonstrate this, we implemented 96 channel TDCs in both FPGAs, using less than 25% of the logic resources. The achieved least significant bit (LSB) is 10.5 ps for Virtex 7 and 5.0 ps for UltraScale FPGAs. After the compensation and calibration, the differential nonlinearity (DNL) is within [–0.05, 0.08] LSB with σDNL = 0.01 LSB, and the integral nonlinearity (INL) is within [–0.09, 0.11] LSB with σINL = 0.04 LSB for the Virtex 7 FPGA. The DNL is within [–0.12, 0.11] LSB with σDNL = 0.03 LSB, and the INL is within [–0.15, 0.48] LSB with σINL = 0.20 LSB for the UltraScale FPGA.

A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS

A non-interleaved 2-GS/s, 8-bit flash analog-to-digital converter (ADC) utilizing the remainder number system (RNS) quantization principle is presented. The RNS quantization reduces the number of comparators and thus improves the figure of merit of the flash ADC. A time-domain implementation is adopted to reduce the ADC input capacitance with a voltage-to-time converter (VTC) front end. The ring oscillator-based time-to-digital converter (TDC) also provides a linear and efficient modulo (folding) operation for the RNS quantization with built-in dynamic element matching. Offline TDC mismatch calibration based on a histogram (code density) test is also employed to further improve the ADC linearity. The prototype RNS ADC was fabricated in a 65-nm CMOS process with an active area of 0.08 mm2. It measures an SNDR of 40.7 dB for a Nyquist input and an effective resolution bandwidth of 1.74 GHz.

An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA

A new time-to-digital converter (TDC) with high resolution and high precision is designed and tested in this paper. The converter is realized by combining coarse clock counter with a two-stage delay-line loop shrinking interpolator (DLLSI) based on Vernier configuration, and its prototype has been implemented in a low-cost flash field-programmable gate array device SmartFusion A2F200M3F (Actel). Delay-line loops are used to achieve differential Vernier delay unit and directly shrink the time interval. In order to improve the resolution, decrease measurement time, and diminish the jitter of the cyclic pulse, a two-stage DLLSI method is proposed. The first-stage interpolator rapidly shrinks the measured time interval with low resolution, and the second-stage interpolator determines the final fine resolution. The resolutions are dependent on the entire delay time differences between two delay-line loops of each interpolator. The optimal resolutions are theoretically calculated, and statistic code density test is used to estimate the resolution of the implemented TDC. The implemented two-stage DLLSI has achieved 8.5-ps resolution with 42.4-ps standard deviation and 10-ns dynamic range. The maximum integral and differential nonlinearity errors are less than 7.8 and 3.1 ps.

Design and Characterization of a Low-Cost FPGA-Based TDC

We present a field-programmable gate array (FPGA) implementation of a time-to-digital converter (TDC) based on a low-cost, low-area Spartan 6 device. The converter is based on a tapped delay line model. Several implementation details are discussed with a particular focus on critical blocks such as the input stage and thermometer-to-binary decoding techniques. We implemented a tap filtering technique to improve the differential nonlinearity (DNL) of the single delay line while keeping a good LSB value of 25.57 ps with a single-shot precision (SSP) between 0.69 - 1.46 LSB. Measured DNL and integral nonlinearity (INL) lie in the range between -0.90 + 1.23 and -0.43 ÷ 2.96 LSB, respectively. Measured DNL and INL lie in the range between -0.90 ÷ 1.23 and -0.43 ÷ 2.96 LSB, respectively. We then implemented an interpolating TDC to overcome the limitations of a single delay line in terms of linearity and measurement range. The interpolating TDC uses the sliding scale technique, where the time interval to be measured is asynchronous with respect to the FPGA clock, achieving DNL and INL in the range -0.072 ÷ 0.070 and -0.755 ÷ 0.872 LSB. SSP is in the 1.096 ÷ 2.815 range. Moreover, we present a novel comparison between the DNLs obtained with two different methods: statistical code density test and using a finely controlled delay source. Finally, we present the results of a Monte Carlo simulation used to investigate the effects of nonlinear propagation of the signal through the delay line.

Toward Implementing Multichannels, Ring-Oscillator-Based, Vernier Time-to-Digital Converter in FPGAs: Key Design Points and Construction Method

For TOF positron emission tomography (TOF PET) detectors, time-to-digital converters (TDCs) are essential to resolve the coincidence time of the photon pairs. Recently, an efficient TDC structure called ring-oscillator-based (RO-based) Vernier TDC using carry chains was reported by our team. The method is very promising due to its low linearity error and low resource cost. However, the implementation complexity is rather high especially when moving to multi-channels TDC designs, since this method calls for a manual intervention to the initial fitting results of the compilation software. In this paper, we elaborate the key points toward implementing high performance multi-channels TDCs of this kind while keeping the least implementation complexity. Furthermore, we propose an efficient fine time interpolator construction method called the period difference recording which only needs at most 31 adjustment trials to obtain a targeted TDC resolution. To validate the techniques proposed in this paper, we built a 32-channels TDC on a Stratix III FPGA chip and fully evaluated its performance. Code density tests show that the obtained resolution results lie in the range of (23 ps ~ 37 ps), the differential nonlinearity (DNL) results lie in the range of (-0.4 LSB ~ 0.4 LSB) and the integral nonlinearity (INL) results lie in the range of (-0.7 LSB ~ 0.7 LSB) for each of the 32 TDC channels. This paper greatly eases the designing difficulty of the carry chain RO-based TDCs and can significantly propel their development in practical use.

A Low Nonlinearity, Missing-Code Free Time-to-Digital Converter Based on 28-nm FPGAs With Embedded Bin-Width Calibrations

This paper presents a low nonlinearity, missing-code free, time-to-digital converter (TDC) implemented in a 28-nm field programmable gate array (FPGA) device (Xilinx Virtex 7 XC7V690T) with novel direct bin-width calibrations. We combine the tuned tapped delay lines (TDLs) and a modified direct-histogram architecture to correct the nonuniformity originated from carry chains, and use a multiphase sampling structure to minimize the skews of clock routes. Results of code density tests show that the proposed TDC has much better linearity performances than previously published TDCs. Moreover, our TDC does not generate missing codes. For a single TDL, the differential nonlinearity (DNL) is within [−0.38, 0.87] LSB (the least significant bit: 10.5 ps) with $\sigma _{\mathrm {DNL}} = 0.20$ LSB, and the integral nonlinearity (INL) is within [−1.23, 1.02] LSB with $\sigma _{\mathrm {INL}} = 0.50$ LSB. Based on the modified direct-histogram architecture, a direct bin-width calibration method was implemented and verified in the FPGA. By implementing embedded bin-width calibrations, the histogram data of TDCs can be calibrated on the fly. After the calibration, the DNL $_{\mathrm {pk-pk}}$ (peak-to-peak DNL) and INL $_{\mathrm {pk-pk}}$ (peak-to-peak INL) can be reduced to 0.08 LSB with $\sigma _{\mathrm {DNL}} = 0.01$ and 0.13 LSB with $\sigma _{\mathrm {INL}} = 0.02$ LSB, respectively.

A readout integrated circuit based on DBI-CTIA and cyclic ADC for MEMS-array-based focal plane**Project supported by by National Natural Science Foundation of China (No. 61271130), the Beijing Municipal Science and Tech Project (No. D13110100290000), the Tsinghua University Initiative Scientific Research Program (No. 20131089225), and the Shenzhen Science and Technology Development Fund (No. CXZZ20130322170740736).

A readout integrated circuit (ROIC) for a MEMS (microelectromechanical system)-array-based focal plane (MAFP) intended for imaging applications is presented. The ROIC incorporates current sources for diode detectors, scanners, timing sequence controllers, differential buffered injection-capacitive trans-impedance amplifier (DBI-CTIA) and 10-bit cyclic ADCs, and is integrated with MAFP using 3-D integration technology. A small-signal equivalent model is built to include thermal detectors into circuit simulations. The biasing current is optimized in terms of signal-to-noise ratio and power consumption. Layout design is tailored to fulfill the requirements of 3-D integration and to adapt to the size of MAFP elements, with not all but only the 2 bottom metal layers to complete nearly all the interconnections in DBI-CTIA and ADC in a 40 μm wide column. Experimental chips are designed and fabricated in a 0.35 μm CMOS mixed signal process, and verified in a code density test of which the results indicate a (0.29/−0.31) LSB differential nonlinearity (DNL) and a (0.61/−0.45) LSB integral nonlinearity (INL). Spectrum analysis shows that the effective number of bits (ENOB) is 9.09. The ROIC consumes 248 mW of power at most if not to cut off quiescent current paths when not needed.

Time interval generator with 8 ps resolution and wide range for large TDC array characterization

Accurate generation of picosecond-resolution wide---range time intervals gives rise to a new time-efficient method for the characterization of large arrays of time-to-digital converters involved in time resolved imaging. This paper presents the design and measurement of a time interval generator based on FPGA technology. Although it can be employed in different automatic test setups, it has been designed to characterize an array of time-to-digital converters. It can work as periodic pulse/frequency generator but also as a digital-to-time converter. The accuracy of periodic pulse generator is around 20 ps RMS jitter for a pulse width ranging from 600 ps to 33 µs. The incremental time resolution is 8 ps and the repetition rate is up to 2 MHz. The accuracy of the digital-to-time converter is less than 0.8LSB DNL and 2LSB INL, whilst the time resolution is 27 ps. Full characterization of the module is reported including a comparison with state-of-the-art instruments in this field. The measurement results of the time-to-digital converter array driven by the designed digital-to-time converter module are presented as well. The effectiveness of the proposed method is evaluated by comparing it with the statistical code density test.

A Digital Phase-Locked Loop With Calibrated Coarse and Stochastic Fine TDC

A coarse-fine time-to-digital converter (TDC) is presented with a calibrated coarse stage followed by a stochastic fine stage. On power-up, a calibration algorithm based on a code density test is used to minimize nonlinearities in the coarse TDC. By using a balanced mean method, the number of registers required for the calibration algorithm is reduced by 30%. Based upon the coarse TDC output, the appropriate clock signals are multiplexed into the stochastic fine TDC. The TDC is incorporated into a 1.99-2.5-GHz digital phase-locked loop (DPLL) in 0.13-μm CMOS. The DPLL consumes a total of 15.2 mW of which 4.4 mW are consumed in the TDC. Measurements show an in-band phase noise of -107 dBc/Hz which is equivalent to 4-ps TDC resolution, approximately an order of magnitude better than an inverter delay in this process technology. The integrated random jitter is 213 fs rms for a 2-GHz output carrier frequency with 700-kHz loop bandwidth. The calibration reduces worst-case spurs by 16 dB.

EXPLOITING CHAOTIC DYNAMICS FOR A-D CONVERTER TESTING

In this paper we discuss the possible use of chaotic signals for testing Analog-to-Digital Converters (ADCs), with particular reference to the well-known Code Density Test (CDT, also called Histogram Test). In detail, we discuss the implementation of a chaos-based discrete-time noise generator circuit, providing the theoretical analysis of its statistical characterization. The implementation of the chaos-based device is discussed with reference to a generic hardware architecture, taking into account the nonidealities introduced by the presence of noise and the variability of the circuit parameters. Based on this device, we propose a method for generating noisy samples that are distributed, over a target subinterval of the circuit output range, according to a probability density function (pdf) that can be made arbitrarily close to the ideal uniform pdf, in exchange for an acceptable reduction of the uniform-distributed samples generation rate. Theoretical results, also supported by two experiments, confirm the reliability of the proposed solution, showing that chaotic systems can represent an alternative with respect to traditional methods for the generation of signals to be used in the Code Density Test of ADCs.

A high-resolution time interpolator based on a delay locked loop and an RC delay line

An architecture for a time interpolation circuit with an rms error of /spl sim/25 ps has been developed in a 0.7-/spl mu/m CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT). The very small temperature/voltage dependence of R and C parameters and the self calibrating DLL results in a low-power, high-resolution time interpolation circuit in a standard digital CMOS technology.

An improved code density test for the dynamic characterization of flash A/D converters

An improved code density test for flash A/D converters is proposed, revealing some dynamic phenomena (e.g., missing codes) hidden by the conventional approach. Formulas are reported for obtaining, from code density, effective noise estimates fully consistent with those provided by waveform analysis. Finally, it is shown that the variance of noise estimates obtained by time-domain analysis may be unacceptably large if the observation window is not properly chosen.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Reliability of code density test for high resolution ADCs

The effect of convertor internal noise on its output code histogram is analysed. Simulations show that large linearity errors, including missing codes, may vanish when sufficient noise is experienced. Consequently, the code density test is likely to yield a differential nonlinearity error within +/-0.5 LSB for any high accuracy noisy convertor.

Full-speed testing of A/D converters

Improved computer-aided analog-to-digital converter (ADC) characterization methods based on the code density test and spectral analysis using the fast Fourier transform are described. The code density test produces a histogram of the digital output codes of an ADC sampling a known input. The code density can be interpreted to compute the differential and integral nonlinearities, gain error, offset error, and internal noise. Conversion-rate and frequency-dependent behavior can also be measured.