Code Checkers Research Articles

Comments on 'A MOS implementation of totally self-checking checker for the 1-out-of-3 code'

Shows that the transistor count of the MOS totally self-checking (TSC) 1-out-of-3 code checker given can be reduced from 17 to 13. Similarly, the transistor count of the 2-out-of-3 code checker can be reduced from 11 to 7.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Modulo 3 residue checker: new results on performance and cost

The performance and cost of a modulo-3 residue code checker that has been attached to a pipelined serial multiplier to provide a concurrent self-test capability are considered. Analytical results are derived for error detection coverage and minimum error latency; these quantities are observed to be in agreement with simulation results obtained by using ISPS, a register-transfer language. The residue checker error detection coverage and minimum error latency are observed to be dependent on the statistical properties of the multiplier input operands. The checker and serial multiplier were implemented in 4- mu m NMOS, using a standard cell design. The residue code checker required approximately half of the total silicon area.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Efficient modular design of TSC checkers for m-out-of-2m codes

A design method of totally self-checking (TSC) m-out-of-2m code checkers is presented. The design is composed basically of two full-adder/half-adder trees, each summing up the ones received on m input lines, and a k-variable two-pair two-rail code tree that compares the outputs of the two-adder tree. The only modules used are full-adders, half-adders, and two-variable TSC two-rail code checkers. This method is well suited for VLSI MOS implementation and, compared to previous methods, it results in significant circuit cost reduction and smaller test set, without sacrificing performance. Also, the proposed design has the advantages of a modular design. >

Concurrently totally self-checking microprogram control unit with duplication of microprogram sequencer

This paper presents a new design method for concurrently Totally Self-Checking Microprogram Control Units of bit-slice microprocessors. We consider a fault model that includes arbitrary failures in a single IC package and multiple errors on address, data and control buses. In our method the microprogram sequencer and the remaining functional units that support it are duplicated. Also, the microinstructions with their b-bit addresses are encoded in a distance-2 n-adjacent encoding scheme. Finally an N-adjacent code checker is employed to monitor the outputs from the microprogram memory and the microprogram sequencer. The checker and hence the whole Microprogram Control Unit becomes concurrently Totally Self-Checking by using a small number of microinstructions stored in predefined addresses in the microprogram memory. Our method in comparison to others has the added advantage to detect concurrently not only the permanent faults, but also temporary faults occurring during normal operation.

Techniques for efficiently implementing totally self-checking checkers in MOS technology

This paper presents some new techniques for reducing the transistor count oof MOS implementations of totally self-checking (TSC) checkers. The techniques are (1) transfer of fanouts, (2) removal of inverters and (3) use of multi-level realizations of functions. These techniques also increase the speed of the circuit and may reduce the number of required tests. Their effectiveness has been demonstrated by applying them to m-out-of- n and Berger code checkers. Impressive reductions of up to 90% in the transistor count in some cases have been obtained for the MOS implementation of these checkers. This directly translates into saving of chip area.

Efficient modular design of m-out-of-2m TSC checkers, for m=2K−1, K&gt;2

A very efficient modular design method for m-out-of-2m TSC checkers, for m=2K−1, is described. The checkers are designed using full-adder modules and TSC two-rail code checker modules only. Comparisons are made of the number of MOS transistors required and the size of the test set. The low transistor count and the modular structure of the design favours its VLSI implementation.

Fault tolerance and digital systems

The paper surveys recent techniques for incorporating selftest and fault-tolerant features into digital systems and comments on their applicability to designs containing VLSI components, such as microprocessors and microcomputers. In particular, the paper covers coding techniques and the design of totally self-checking code checkers; the design of fault-tolerant computer subsystems such as clock generators and semiconductor memory; and techniques for including built-in test facilities and the development of self-test checkout routines. In conclusion, it is suggested that the next major area for research must be the design of fault-tolerant software.

Detection of Storage Errors in Mass Memories Using Low-Cost Arithmetic Error Codes

Arithmetic error codes constitute a class of error codes that are preserved during most arithmetic operations. Effectiveness studies for arithmetic error codes have shown their value for concurrent detection of faults in arithmetic processors, data transmission subsystems, and main storage units in fault-tolerant computers. In this paper, it is shown that the same class of codes is also quite effective for detecting storage errors in both shift-register and magnetic-recording mass memories. Some of the results are more general and deal with properties of arithmetic error codes in detecting unidirectional failures. For example, it is shown that a low-cost arithmetic error code with check modulus A = 2N - 1 can detect any unidirectional failure which affects fewer than N bits. The use of arithmetic error codes for checking of mass memories is further justified since it eliminates the need for hard-core or self-checking code translators and reduces the number of different types of code checkers required.