Coarse-grained Reconfiguration Research Articles

Towards Trust Hardware Deployment of Edge Computing: Mitigation of Hardware Trojans Based on Evolvable Hardware

Hardware Trojans (HTs) are malicious hardware components designed to leak confidential information or cause the chip/circuit on which they are integrated to malfunction during operation. When we deploy such hardware platforms for edge computing, FPGA-based implementations of Coarse-Grained Reconfigurable Array (CGRA) are also currently falling victim to HT insertion. However, for CGRA, an evolvable hardware (EHW) platform, which has the ability to dynamically change its configuration and behavioral characteristics based on inputs from the environment, provides us with a new way to mitigate HT attacks. In this regard, we investigate the feasibility of using EHW to mitigate HTs that disrupt normal functionality in CGRA in this paper. When it is determined that HT is inserted into certain processing elements (PEs), the array autonomously reconfigures the circuit structure based on an evolutionary algorithm (EA) to avoid the use of HT-infected (HT-I) PEs. We show that the proposed approach is applicable to: (1) hardware platforms that support coarse-grained reconfiguration; and (2) pure combinatorial circuits. In a simulation environment built in Python, this paper reports experimental results for two target evolutionary circuits and outlines the effectiveness of the proposed method.

Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators

Domain-specific acceleration is now a must for all the computing spectrum, going from high performance computing to embedded systems. Unfortunately, system specialization is by nature a nightmare from the design productivity perspective. Nevertheless, in contexts where kernels to be accelerated are intrinsically streaming oriented, the combination of dataflow (DF) models of computation with coarse-grained reconfiguration (CGR) architectures can be particularly handful. In this letter we introduce a novel methodology to assemble and characterize virtually reconfigurable accelerators based on DF and functional programming principles, capable of addressing design productivity issues for CGR accelerators. The main advantage of the proposed methodology is accurate IP-level latency predictability improving design space exploration when compared with state-of-the-art high-level synthesis.

Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC

Abstract: Many embedded video-based systems require a video codec to reduce the bitrate prior to exchange video information. MPEG High Efficiency Video Coding (HEVC) is the latest, most efficient codec developed by the MPEG group. In the context of HEVC decoding, the optimization of the motion compensation stage is a daunting task. Recently, software implementation studies tackled it leveraging on approximate computing. This paper intends to prove the possibility of adopting coarse-grained hardware reconfiguration to provide dynamic energy management to an HEVC decoder. Runtime coarse-grained adaptation is shown to guarantee energy reduction, in constraint-aware or user-defined situations, while introducing a controllable quality degradation due to approximation.

Fast, Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts

High-level synthesis from OpenCL has shown significant potential, but current approaches conflict with mainstream OpenCL design methodologies owing to orders-of-magnitude longer field-programmable gate array compilation times and limited support for changing or adding kernels after system compilation. In this article, the authors introduce a back-end synthesis approach for potentially any OpenCL tool. This approach uses virtual coarse-grained reconfiguration contexts to speed up compilation by 4,211× at a cost of 1.8× system resource overhead, while also enabling 144× faster reconfiguration to support different kernels and rapid changes to kernels.

Reconfigurable computer architectures

Reconfigurable computing is a promising approach to overcome the traditional trade-off between flexibility and performance in the design of computer architectures. Computing systems that adapt their hardware to each application can achieve the high performance of dedicated hardware while retaining the flexibility of general-purpose processors. This paper introduces to the currently taken approaches in reconfigurable computing: fine-grained and coarse-grained reconfiguration. The enabling technology is discussed, reconfiguration models and application examples are presented. Finally, topical research problems are enumerated.