Coarse-grained Applications Research Articles

Generating Unified Platforms Using Multigranularity Domain DSE (MG-DmDSE) Exploiting Application Similarities

Heterogeneous accelerator-rich (ACC-rich) platforms combining general-purpose cores and specialized HW accelerators (ACCs) promise high-performance and low-power streaming application deployments in a variety of domains, such as video analytics and software-defined radio. In order to benefit a domain of applications, a domain platform exploration tool must take advantage of structural and functional similarities across applications by allocating a common set of ACCs. A previous approach proposed a genetic domain exploration tool (GIDE) that applied a restrictive binding algorithm that mapped applications functions to monolithic accelerators. This approach suffered from a low average application throughput across and reduced platform generality. This article introduces a multigranularity-based domain design space exploration tool (MG-DmDSE) to improve both average application throughput as well as platform generality. The key contributions of MG-DmDSE are: 1) applying a multigranular decomposition of coarse-grained application functions into more granular compute kernels; 2) examining compute similarity between functions in order to provide more generic functions; 3) configuring monolithic ACCs by selectively bypassing compute elements within them during DSE to expose more functionality; and 4) speeding up MG-DmDSE platform allocation exploration through a greedy guided mutation (GGM) algorithm. To assess MG-DmDSE, both GIDE and MG-DmDSE were applied to applications in the OpenVX library. MG-DmDSE achieves an average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.84\times $ </tex-math></inline-formula> greater application throughput compared to GIDE. Additionally, 87.5% of applications benefited from running on the platform produced by MG-DmDSE versus 50% from GIDE, which indicated increased platform generality. The generated MG-DmDSE platforms achieve an average of 61.8% logarithmic throughput improvement for unknown applications over GIDE. GGM results in saving 84.8% of the exploration time in MG-DmDSE with only 0.23% performance loss.

Research into compaction characteristics of large-size coarse-grained soil and application

The filling characteristic of rockfill is a non-ignorable engineering problem for high dams, and a reasonable control of compaction quality is the key to promoting the development of high dams. In this article, numerical and field tests were implemented to study the main problems affecting the compaction characteristics of large-size coarse-grained soil, namely determinations of the reasonable H0/dmax (the ratio of the compaction layer thickness to the maximum particle size) and the main influencing factors of minimum porosity. The macroscopic manifestations of the compaction characteristics were analyzed from the perspectives of energy, force chain, and particle breakage. The interaction between particles was explained by the ‘filling effect’ of fine particles, the ‘wedging effect’, and the ‘wall effect’ of coarse particles. It was found that the minimum porosity was not an inherent characteristic of rockfill, since the porosity and the corresponding degree of breakage were influenced by the compaction conditions. The value of H0/dmax meeting engineering practice was proposed, which can create favorable compaction conditions for obtaining the minimum porosity. Meantime, some suggestions were provided for obtaining the minimum porosity of large-size coarse-grained soil. The research results have an application reference value for the filling design and evaluation of high dams.

Cosmo: a concurrent separation logic for multicore OCaml

Multicore OCaml extends OCaml with support for shared-memory concurrency. It is equipped with a weak memory model, for which an operational semantics has been published. This begs the question: what reasoning rules can one rely upon while writing or verifying Multicore OCaml code? To answer it, we instantiate Iris, a modern descendant of Concurrent Separation Logic, for Multicore OCaml. This yields a low-level program logic whose reasoning rules expose the details of the memory model. On top of it, we build a higher-level logic, Cosmo, which trades off some expressive power in return for a simple set of reasoning rules that allow accessing nonatomic locations in a data-race-free manner, exploiting the sequentially-consistent behavior of atomic locations, and exploiting the release/acquire behavior of atomic locations. Cosmo allows both low-level reasoning, where the details of the Multicore OCaml memory model are apparent, and high-level reasoning, which is independent of this memory model. We illustrate this claim via a number of case studies: we verify several implementations of locks with respect to a classic, memory-model-independent specification. Thus, a coarse-grained application that uses locks as the sole means of synchronization can be verified in the Concurrent-Separation-Logic fragment of Cosmo, without any knowledge of the weak memory model.

Arbitrary Resolution with Two Bead Types Coarse-Grained Strategy and Applications to Protein Recognition.

Molecular recognition is a fundamental step in essentially any biological process. However, the kinetic processes during association and dissociation are difficult to be efficiently sampled by direct all-atom molecular dynamics simulations because of the large spatial and temporal scales. Here we propose an arbitrary resolution with two bead types (ART) coarse-grained (CG) strategy that is adept in molecular recognition. ART is a universal user-customized CG strategy that can generate a system-specific CG force field anytime and be applied to any system with an arbitrary CG resolution according to research requirements. ART CG simulations can be very efficiently performed with implicit solvation in prevalent simulation packages and provide interfaces for any enhanced sampling method. We used three applications, HLA-HIV epitope recognition, barnase-barstar association, and trimeric TRAF2 self-assembly, to validate the feasibility of the ART CG strategy, its advantages in protein recognition, and its high performance in simulations. Regular CG simulations can successfully achieve valid protein recognitions without any prior bound structure.

The Grain Size Distribution of Blasted Rock

The determination of the grain size distribution of blasted rock exceeds the capability of an analytical sieving machine which only gives reliable results within a range of 63 μm to 125 mm. Other sophisticated methods are often not available for particle size measurement in coarse-grained applications in medium scale mining. Therefore, an alternative low cost method to investigate the grain sizes of blasted rock is introduced which can cover a range from 63 μm at the lower end without an upper limit. Three different options to examine blasted dolomite grains are investigated and combined with sieve analysis to determine a complete sieving equivalent grain size distribution. Comparison with results of a technical sieving shows that this method gives a good approximation of the size distribution, improving the possibilities for design of mineral processing equipment.

The Unicorn Runtime: Efficient Distributed Shared Memory Programming for Hybrid CPU-GPU Clusters

Programming hybrid CPU-GPU clusters is hard. This paper addresses this difficulty and presents the design and runtime implementation of Unicorn —a parallel programming model for hybrid CPU-GPU clusters. In particular, this paper proves that efficient distributed shared memory style programing is possible and its simplicity can be retained across CPUs and GPUs in a cluster, minus the frustration of dealing with race conditions. Further, this can be done with a unified abstraction, avoiding much of the complication of dealing with hybrid architectures. This is achieved with the help of transactional semantics (on shared global address spaces), deferred bulk data synchronization, workload pipelining and various communication and computation scheduling optimizations. We describe the said abstraction, our computation and communication scheduling system and report its performance on a few benchmarks like Matrix Multiplication , LU Decomposition and 2D FFT . We find that parallelization of coarse-grained applications like matrix multiplication or 2D FFT using our system requires only about 30 lines of C code to set up the runtime. The rest of the application code is regular single CPU/GPU implementation. This indicates the ease of extending parallel code to a distributed environment. The execution is efficient as well. When multiplying two square matrices of size $65,536\times 65,536$ , Unicorn achieves a peak performance of 7.88 TFlop/s when run over a cluster of 14 nodes with each node equipped with two Tesla M2070 GPUs and two 6-core Intel Xeon 2.67 GHz CPUs, connected over a 32 Gbps Infiniband network. In this paper, we also demonstrate that the Unicorn programming model can be efficiently used to implement high level abstractions like MapReduce. We use such an extension to implement PageRank and report its performance. For a sample web of 500 million web pages, our implementation completes a page rank iteration in about 18 seconds (on average) on a 14-node cluster.

RECONFIGURABLE AND VERSATILE BILRC ARCHITECTURE DESIGN WITH AN AREA AND POWER EFFICIENT TECHNIQUE

Coarse Grained Reconfigurable Architecture based systems have become increasingly important in these days. In order to handle multiple applications with low area and power requirement ,a new coarse grained reconfigurable architecture (CGRA) is exhibited here. The architecture which is named BilRC, Bilkent Reconfigurable Computer manipulates an execution-triggering mechanism. By mapping real-world applications, the adaptability of the architecture and the computation model are justified. BilRC design is done by using Xilinx and analysis of Area and Power are done. The proposed architecture design can also be implemented by mapping the applications to a 90-nm FPGA array. The model minimizes the configuration size to about 33 times. The design is further developed leading to a new architecture design so as to support multimedia applications. One of the distinguishing features of the proposed BilRC architecture is that the hardware and the programming language are code signed. The simulation results show an increase in the performance by reducing the power consumption to 92%. The design is synthesized with 90-nm technology, and the mapping applications on BilRC run faster than those on FPGA about 2.5 times. The expectation from BilRC is the replacement of FPGAs with BilRC in Coarse Grained Applications.

Enhancing throughput for streaming applications running on cluster systems

The exploitation of throughput in a parallel application that processes an input data stream is a difficult challenge. For typical coarse-grain applications, where the computation time of tasks is greater than their communication time, the maximum achievable throughput is determined by the maximum task computation time. Thus, the improvement in throughput above this maximum would eventually require the modification of the source code of the tasks. In this work, we address the improvement of throughput by proposing two task replication methodologies that have the target throughput to be achieved as an input parameter. They proceed by generating a new task graph structure that permits the target throughput to be achieved. The first replication mechanism, named DPRM (Data Parallel Replication Mechanism), exploits the inner task data parallelism. The second mechanism, named TCRM (Task Copy Replication Mechanism), creates new execution paths inside the application task graph structure that allows more than one instance of data to be processed concurrently. We evaluate the effectiveness of these mechanisms with three real applications executed in a cluster system: the MPEG2 video compressor, the IVUS (Intra-Vascular Ultra-Sound) medical image application and the BASIZ (Bright and SAtured Images Zone) video processing application. In all these cases, the obtained throughput was greater after applying the proposed replication mechanism than what the application could provide with the original implementation.

An integrated pseudo-associativity and relaxed-order approach to hardware transactional memory

Our experimental study and analysis reveal that the bottlenecks of existing hardware transactional memory systems are largely rooted in the extra data movements in version management and in the inefficient scheduling of conflicting transactions in conflict management, particularly in the presence of high-contention and coarse-grained applications. In order to address this problem, we propose an integrated Pseudo-Associativity and Relaxed-Order approach to hardware Transactional Memory, called PARO-TM. It exploits the extra pseudo-associative space in the data cache to hold the new value of each transactional modification, and maintains the mappings between the old and new versions via an implicit pseudo-associative hash algorithm (i.e., by inverting the specific bit of the SET index). PARO-TM can branch out the speculative version from the old version upon each transactional modification on demand without a dedicated hardware component to hold the uncommitted data. This means that it is able to automatically access the proper version upon the transaction's commit or abort. Moreover, PARO-TM augments multi-version support in a chained directory to schedule conflicting transactions in a relaxed-order manner to further reduce their overheads. We compare PARO-TM with the state-of-the-art LogTM-SE, TCC, DynTM, and SUV-TM systems and find that PARO-TM consistently outperforms these four representative HTMs. This performance advantage of PARO-TM is far more pronounced under the high-contention and coarse-grained applications in the STAMP benchmark suite, for which PARO-TM is motivated and designed.

Active pebbles

A variety of programming models exist to support large-scale, distributed memory, parallel computation. These programming models have historically targeted coarse-grained applications with natural locality such as those found in a variety of scientific simulations of the physical world. Fine-grained, irregular, and unstructured applications such as those found in biology, social network analysis, and graph theory are less well supported. We propose Active Pebbles, a programming model which allows these applications to be expressed naturally; an accompanying execution model ensures performance and scalability.

Mapping workflow applications with types on heterogeneous specialized platforms

In this paper, we study the problem of optimizing the throughput of coarse-grain workflow applications, for which each task of the workflow is of a given type, and subject to failures. The goal is to map such an application onto a heterogeneous specialized platform, which consists of a set of processors that can be specialized to process one type of tasks. The objective function is to maximize the throughput of the workflow, i.e., the rate at which the data sets can enter the system. If there is exactly one task per processor in the mapping, then we prove that the optimal solution can be computed in polynomial time. However, the problem becomes NP-hard if several tasks can be assigned to the same processor. Several polynomial time heuristics are presented for the most realistic specialized setting, in which tasks of the same type can be mapped onto the same processor, but a processor cannot process two tasks of different types. Also, we give an integer linear program formulation of this problem, which allows us to find the optimal solution (in exponential time) for small problem instances. Experimental results show that the best heuristics obtain a good throughput, much better than the throughput obtained with a random mapping. Moreover, we obtain a throughput close to the optimal solution in the particular cases on which the optimal throughput can be computed (small problem instances or particular mappings).

An Integrated Approach to Locality-Conscious Processor Allocation and Scheduling of Mixed-Parallel Applications

Complex parallel applications can often be modeled as directed acyclic graphs of coarse-grained application tasks with dependences. These applications exhibit both task and data parallelism, and combining these two (also called mixed parallelism) has been shown to be an effective model for their execution. In this paper, we present an algorithm to compute the appropriate mix of task and data parallelism required to minimize the parallel completion time (makespan) of these applications. In other words, our algorithm determines the set of tasks that should be run concurrently and the number of processors to be allocated to each task. The processor allocation and scheduling decisions are made in an integrated manner and are based on several factors such as the structure of the task graph, the runtime estimates and scalability characteristics of the tasks, and the intertask data communication volumes. A locality-conscious scheduling strategy is used to improve intertask data reuse. Evaluation through simulations and actual executions of task graphs derived from real applications and synthetic graphs shows that our algorithm consistently generates schedules with a lower makespan as compared to Critical Path Reduction (CPR) and Critical Path and Allocation (CPA), two previously proposed scheduling algorithms. Our algorithm also produces schedules that have a lower makespan than pure task- and data-parallel schedules. For task graphs with known optimal schedules or lower bounds on the makespan, our algorithm generates schedules that are closer to the optima than other scheduling approaches.

The Design and Evaluation of MPI-Style Web Services

In this paper, we introduce MPI-style Web service (MPIWS), a novel service presented as a standard Web service but integrated with MPI programming technologies to allow Web applications to run in parallel over a loosely coupled distributed environment. MPIWS takes advantage of the SOAP communication protocol, and allows direct MPI-style communication among loosely coupled services. The MPI-style communication supported by MPIWS includes both point-to-point and collective communications. In this paper, point-to-point and collective communication operations are evaluated in comparison with mpiJava. The evaluation results demonstrate that although the overhead of SOAP messaging takes a toll on performance, MPIWS is generally comparable with mpiJava sending Object data types, especially for coarse-grain applications, and outperforms mpiJava in some cases.

Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis

A growing number of applications, often with real-time requirements, are integrated on the same system on chip (SoC), in the form of hardware and software intellectual property (IP). To facilitate real-time applications, networks on chip (NoC) guarantee bounds on latency and throughput. These bounds, however, only extend to the network interfaces (NI), between the IP and the NoC. To give performance guarantees on the application level, the buffers in the NIs must be sufficiently large for the particular application. At the same time, it is imperative to minimise the size of the NI buffers, as they are major contributors to the area and power consumption of the NoC. Existing buffer-sizing methods use coarse-grained application models, based on linear traffic bounds or periodic producers and consumers, thus severely limiting their applicability. In this work, the authors propose to capture the behaviour of the NoC and the applications using a dataflow model. This enables one to verify the temporal behaviour and to compute buffer sizes using existing dataflow analysis techniques. The authors show what is required from the NoC architecture and demonstrate how to construct an NoC model, with multiple levels of detail. Using the proposed model, buffer sizes are determined for a range of SoC designs with a run time comparable to existing analytical methods, and results comparable to exhaustive simulation. For an application case study, where existing buffer-sizing methods are not applicable, the proposed model enables the verification of end-to-end temporal behaviour.

Fast procedure for reconstruction of full‐atom protein models from reduced representations

We introduce PULCHRA, a fast and robust method for the reconstruction of full-atom protein models starting from a reduced protein representation. The algorithm is particularly suitable as an intermediate step between coarse-grained model-based structure prediction and applications requiring an all-atom structure, such as molecular dynamics, protein-ligand docking, structure-based function prediction, or assessment of quality of the predicted structure. The accuracy of the method was tested on a set of high-resolution crystallographic structures as well as on a set of low-resolution protein decoys generated by a protein structure prediction algorithm TASSER. The method is implemented as a standalone program that is available for download from http://cssb.biology.gatech.edu/skolnick/files/PULCHRA.

Dryad

Dryad is a general-purpose distributed execution engine for coarse-grain data-parallel applications. A Dryad application combines computational "vertices" with communication "channels" to form a dataflow graph. Dryad runs the application by executing the vertices of this graph on a set of available computers, communicating as appropriate through flies, TCP pipes, and shared-memory FIFOs. The vertices provided by the application developer are quite simple and are usually written as sequential programs with no thread creation or locking. Concurrency arises from Dryad scheduling vertices to run simultaneously on multiple computers, or on multiple CPU cores within a computer. The application can discover the size and placement of data at run time, and modify the graph as the computation progresses to make efficient use of the available resources. Dryad is designed to scale from powerful multi-core single computers, through small clusters of computers, to data centers with thousands of computers. The Dryad execution engine handles all the difficult problems of creating a large distributed, concurrent application: scheduling the use of computers and their CPUs, recovering from communication or computer failures, and transporting data between vertices.

Building Large Phylogenetic Trees on Coarse-Grained Parallel Machines

Phylogenetic analysis is an area of computational biology concerned with the reconstruction of evolutionary relationships between organisms, genes, and gene families. Maximum likelihood evaluation has proven to be one of the most reliable methods for constructing phylogenetic trees. The huge computational requirements associated with maximum likelihood analysis means that it is not feasible to produce large phylogenetic trees using a single processor. We have completed a fully cross platform coarse-grained distributed application, DPRml, which overcomes many of the limitations imposed by the current set of parallel phylogenetic programs. We have completed a set of efficiency tests that show how to maximise efficiency while using the program to build large phylogenetic trees. The software is publicly available under the terms of the GNU general public licence from the system webpage at http://www.cs.nuim.ie/distributed.

Run-time support for distributed sharing in safe languages

We present a new run-time system that supports object sharing in a distributed system. The key insight in this system is that a handle-based implementation of such a system enables efficient and transparent sharing of data with both fine- and coarse-grained access patterns. In addition, it supports efficient execution of garbage-collected programs. In contrast, conventional distributed shared memory (DSM) systems are limited to providing only one granularity with good performance, and have experienced difficulty in efficiently supporting garbage collection. A safe language, in which no pointer arithmetic is allowed, can transparently be compiled into a handle-based system and constitutes its preferred mode of use. A programmer can also directly use a handle-based programming model that avoids pointer arithmetic on the handles, and achieve the same performance but without the programming benefits of a safe programming language. This new run-time system, DOSA (Distributed Object Sharing Architecture), provides a shared object space abstraction rather than a shared address space abstraction. The key to its efficiency is the observation that a handle-based distributed implementation permits VM-based access and modification detection without suffering false sharing for fine-grained access patterns. We compare DOSA to TreadMarks, a conventional DSM system that is efficient at handling coarse-grained sharing. The performance of fine-grained applications and garbage-collected applications is considerably better than in TreadMarks, and the performance of coarse-grained applications is nearly as good as in TreadMarks. Inasmuch as the performance of such applications is already good in TreadMarks, we consider this an acceptable performance penalty.

DPAC: an object-oriented distributed and parallel computing framework for manufacturing applications

Parallel and distributed computing infrastructures are increasingly being embraced in the context of manufacturing applications, including real-time scheduling. We present the design and implementation of one such framework that can work on the Internet, with applications in manufacturing. The architecture, DPAC (distributed and parallel computing framework), has the goal of harnessing the Internet's vast, growing computational capacity for ultra-large, coarse-grained parallel applications. The idea is to bring together diverse, heterogeneous, geographically distributed computing environments in order to attack large-scale computing problems. We present a scalable and fault-tolerant architecture in DPAC and the results of running performance experiments. DPAC is implemented on the interoperable, increasingly secure, and ubiquitous platform Java. The unique feature of DPAC is that it frees application developers from concerns about complex interprocess communication and fault tolerance among Internet-worked hosts and supports piecework and branch-and-bound computational models. We describe an implementation and present case studies showing the effectiveness in solving complex combinatorial optimization problems in the context of manufacturing systems.

AUTOMATIC PARALLELIZATION TECHNIQUES BASED ON COMPACT DAG EXTRACTION AND SYMBOLIC SCHEDULING

Symbolic allocation and dynamic scheduling of tasks on a distributed memory machine for coarse-grained applications represented by parameterized task graphs (PTG) are presented in this paper. A PTG is a new computation model for symbolically representing directed acyclic task graphs (DAGs). The size of a PTG is independent of the problem size and its parameters can be instantiated at run time. Parameter independent optimization is important for exploiting non-static parallelism in scientific computing programs with varying problem sizes. Previous DAG scheduling algorithms are not able to handle such cases. We present and study a symbolic scheduling algorithm called SLC (Symbolic Linear Clustering) which derives task clusters from a PTG using affine piecewise mapping functions and then evenly assigns clusters to processors. Thus a complete automatic parallelization method is presented.