CNFET-based Circuits Research Articles

Efficient RF-to-DC Converters for Biomedical Implantable Devices

The power management section associated with the biomedical circuit is very crucial and should be optimally designed for optimal utilization of power. This work discusses the different power shaping or conversion circuits that had been taken for their performance analysis. The two-performance metrics power conversion efficiency and susceptibility against the wireless power transfer have been taken to investigate the operational performance of the biomedical circuits against the input signal strength and operating frequencies. Simulated results confirm the CNFET-based circuit performance is very good at a small value of input voltage 0.6V and a broad range of operating frequency (953 MHz). Therefore, a CNFET-based circuit can be used suitably in implantable devices with optimum power utilization and a remote powering mechanism over the RF link.

Critical Path Tube Redundancy for Power Minimization in CNFET Circuits With Variations

Tube redundancy and correlation has been proposed to increase the functional yield of CNFET-based circuits under CNT variations. However, adding redundant-CNTs is associated with increased power and sometimes increased area. The impact of CNT correlation on CNFET-based circuit performance also remains unexplored. Adding redundancy to all transistors in a circuit was considered in many works. In this paper, we propose adding an optimized number of redundant tubes only to transistors on critical paths. The optimized number of redundant-CNTs is pre-calculated for a desired functional yield. We show that this restricted redundancy retains the improved delay-limited yield achieved in circuits with redundant-CNTs added to all transistors. Moreover, this limited redundancy also reduces power dissipation without exceeding the allowed delay degradation. To ensure redundant tubes are added to all transistors on all critical paths which can emerge in all fabricated circuits due to CNT variations, those paths must first be identified. We propose an efficient method to identify all the critical paths that can exist in the presence of CNT variations. With uncorrelated-CNFETs, our approach reduces the average power increase by 7.8% as compared to all-transistor redundancy. Results also show an improvement in critical path delay by 15-20% and up to 10% reduction in allowed delay-degradation. To examine the influence of tube correlation on CNFET-based circuit performance, two correlated-CNFET standard-cell layouts are evaluated. An average increase of 1.8X in critical path delay variation due to CNFET correlation is noticed in a set of ISCAS'85 benchmarks.

Evaluating a Methodology for Designing CNFET-Based Ternary Circuits

A methodology for designing ternary circuits is proposed and evaluated. The method is based on a schema that consists of voltage levels, conditional blocks and weighting elements. The main idea is selecting appropriate voltage levels in conditional blocks and weighting them to generate desired output. In fact, the diagram is a framework for designing ternary logic gates. Hence, the optimum design can be accomplished by choosing the proper strategy particularly in conditional blocks. This could lead to minimum count of elements and decrement in complexity of the circuit. To examine the efficiency of the proposed method, three designs for standard ternary inverter (STI), ternary NAND (TNAND) and ternary NOR (TNOR) gates in carbon nanotube field-effect-transistor (CNFET) technology are presented, respectively. Several simulations are done using Synopsys HSPICE tool in 32 nm CNFET technology to measure the performance parameters for proposed designs and state-of-the-art CNFET-based designs. Moreover, the robustness of STIs in different operational conditions such as variations frequency and output load, and their senility to process deviations are measured. The simulation is done for TNAND, TNOR and half adder cell as well. The results demonstrate the proper functionality of the proposed methodology. Moreover, the designed circuits benefit from the minimum count of CNFETs, least maximum equivalent input capacitor, minimum variety of CNT diameters and delay time, while its pdp is very close to best results in comparison with state-of-the-art designs.

Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization

Carbon nanotube field-effect transistors (CNFETs) show great potential to build digital systems on advanced technology nodes with big benefits in terms of power, performance, and area (PPA). However, CNFET-specific additional features such as the number of tubes, pitch (spacing between tubes), tube position, and diameter in array of tubes play a significant role in accurate PPA evaluation. Furthermore, count and density variations in carbon nanotubes (CNTs) due to manufacturing limitations, like the presence of metallic tubes in the CNFET channel, degrade the anticipated PPA benefits. Moreover, modeling the CNFET parameters, CNT variations and etching techniques for CNTs create additional complexity during performance optimization. Hence, for realistic optimization of CNFET circuit’s performance, it is imperative to incorporate the impact of these parameters and variations. In this paper, we propose delay models [pitch-aware logical effort (PALE) and position-aware pitch factor (PAPF)] for fast and accurate performance evaluation by including the impact due to CNFET-specific parameters and CNT variations. These models are developed based on industry standard logical effort framework. Furthermore, we present an optimization tool using PALE and PAPF to minimize the delay and area of CNFET circuits. We deploy several circuit-level techniques prior to optimizing the tubes (CNTs) in the logic gates to achieve globally optimum solution. For better optimization of the circuits, we also include the impact of wire parasitic in estimating the delay of the individual gates. Our optimization tool results in the maximum and average delay improvement by 27% and 17%, respectively, and $2.5\times $ reduction in area for standard ISCAS and OpenSPARC benchmark circuits. Fast and fairly accurate delay computation in our optimization framework offers great runtime benefits as compared to state-of-the-art simulation and statistical-based methods.

A new design method for imperfection-immune CNFET-based circuit design

CNFETs (Carbon Nanotube Field Effect Transistors) are among the most outstanding candidates to replace with current semiconductor technology. The facing challenges of this newly introduced nanotechnology like metallic CNT (Carbon nanotube) and misaligned and mispositioned CNTs are considered as obstacles in mass production of circuits based on CNFET. In the present article, first, the correlation between methods of CNFET-based designs circuits and misalignment and mispositioning of CNTs occurrence are assessed in the fabrication phase, and then an approach is propose, which may deal with and eliminate the effects of this challenge. This method is introduced at design level, which is immune against misaligned and mispositioned CNTs and due to the lack of complexity in its layout, it is compatible with recent techniques in eliminating metallic CNT, in a sense that, the application of such techniques does not require change in layout. To evaluate circuit parameters in circuits designed with this proposed method, together with evaluating their tolerance against variations in CNT diameter and density and supply voltage variation a full adder is designed based on this proposed method. The various simulations prove the efficiency of this proposed method and the improvement of circuit parameters compared to previous studies.

Carbon Nanotubes-Based Digitally Programmable Current Follower

The physical constraints of ever-shrinking CMOS transistors are rapidly approaching atomistic and quantum mechanical limits. Therefore, research is now directed towards the development of nanoscale devices that could work efficiently in the sub-10 nm regime. This coupled with the fact that recent design trend for analog signal processing applications is moving towards current-mode circuits which offer lower voltage swings, higher bandwidth, and better signal linearity is the motivation for this work. A digitally controlled DVCC has been realized using CNFETs. This work exploited the CNFET’s parameters like chirality, pitch, and numbers of CNTs to perform the digital control operation. The circuit has minimum number of transistors and can control the output current digitally. A similar CMOS circuit with 32 nm CMOS parameters was also simulated and compared. The result shows that CMOS-based circuit requires 418.6 μW while CNFET-based circuit consumes 352.1 μW only. Further, the proposed circuit is used to realize a CNFET-based instrumentation amplifier with digitally programmable gain. The amplifier has a CMRR of 100 dB and ICMR equal to 0.806 V. The 3 dB bandwidth of the amplifier is 11.78 GHz which is suitable for the applications like navigation, radar instrumentation, and high-frequency signal amplification and conditioning.

Full-Chip Power/Performance Benefits of Carbon Nanotube-Based Circuits

As a potential alternative to the complementary metal-oxide semiconductor (CMOS) technology, many researchers are focusing on carbon-nanotube field-effect transistors (CNFETs) for future electronics. However, existing studies report the advantages of CNFETs over CMOS at the device level by using small-scale circuits, or over outdated CMOS technology. In this paper, we propose a methodology of analyzing CNFET-based circuits and study its impact at the full-chip scale. First, we design CNFET standard cells and use them to construct large-scale designs. Second, we perform parasitic extraction of CNFET devices and characterize their timing and power behaviors. Then, we perform a full-chip analysis and show the benefits of CNFET over CMOS in 45-nm and 20-nm designs. Our full-chip study shows that in the 45-nm design, CNFET circuits achieve a 5.91×/3.87× (delay/power) benefit over CMOS circuits at a density of 200 CNTs/μm. In the 20-nm design, CNFET achieves a 6.44×/3.01× (delay/power) benefit over CMOS at a density of 200 CNTs/μm.

Statistical Functional Yield Estimation and Enhancement of CNFET-Based VLSI Circuits

Carbon nanotube field effect transistors (CNFETs) show great promise as extensions to silicon CMOS. However, imperfections, which are mainly related to carbon nanotubes (CNTs) growth process, result in metallic and nonuniform CNTs leading to significant functional yield reduction. This paper presents a comprehensive technique for statistical functional yield estimation and enhancement of CNFET-based VLSI circuits. Based on experimental data extracted from aligned CNTs, we propose a compact statistical model to estimate the failure probability of a CNFET. Using the proposed failure model, we show that enhancing the CNT synthesis process alone cannot achieve acceptable functional yield for upcoming CNFET-based VLSI circuits. We propose a technique which is based on replacing each transistor by series-parallel transistor structures to reduce the failure probability of CNFETs in the presence of metallic and nonuniform CNTs. The technique is adapted to use single directional independence, which is inherent in aligned CNTs, to enhance the functional yield as validated by theoretical analysis and simulation results. Tradeoffs between failure probability reduction and design overheads such as area and current drive are explored. As demonstrated by extensive simulation results, the proposed technique achieves 80% functional yield in CNFET technology at the cost of 7.5X area and 34% current drive overheads if the CNT density and the fraction of semiconducting CNTs are improved to 200 CNTs per μm and 99.99%, respectively.

Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit

Carbon Nanotube Field Effect Transistors (CNFETs) show great promise as extensions to silicon CMOS. However, CNFET-based circuits will face great fabrication challenges that will translate into important parameter variations and decreased reliability. Hence, asynchronous logic, which is intrinsically more robust to variability, seems an ideal and perhaps unavoidable choice for digital circuits in CNFET technology. This article presents the results on the design and analysis of a CNFET-based implementation of an asynchronous circuit primitive: the Muller C-element. Using a CNFET SPICE model, we evaluate the robustness of CNFET-based C-element in the presence of CNT fabrication-related nonidealities. We investigate a quantitative evaluation of how timing variability impacts the functionality of a C-element and then, extract the necessary delay constraints of the C-element circuit from the signal transition graph specification. Considering the large degrees of spatial correlation observed between the CNFETs fabricated on directionally grown CNTs, a layout technique is exploited to overcome the robustness challenges of a CNFET-based C-element. Extensive Monte Carlo simulations on the proposed technique have demonstrated the effectiveness of the proposed CNFET-based C-element by improving approximately 50X in its robustness in expense of 65% area, 47% delay, and 56% power consumption overheads. Experimental results indicate that implementation of some CNFET-based Quasi Delay Insensitive (QDI) benchmark circuits using the proposed C-element results in significant robustness improvement with negligible power and throughput overheads. As a promising step toward CNFET-based giga-scale integrated circuits, this article shows that the asynchronous logic is an effective approach to design robust integrated circuits in CNFET technology with inherent extreme physical variations.

A statistical-based material and process guidelines for design of carbon nanotubefield-effect transistors in gigascale integrated circuits

Carbon nanotube field-effect transistors (CNFETs) show great promise as buildingblocks of future integrated circuits. However, synthesizing single-walled carbonnanotubes (CNTs) with accurate chirality and exact positioning control has beenwidely acknowledged as an exceedingly complex task. Indeed, density and chiralityvariations in CNT growth can compromise the reliability of CNFET-based circuits. Inthis paper, we present a novel statistical compact model to estimate the failureprobability of CNFETs to provide some material and process guidelines for thedesign of CNFETs in gigascale integrated circuits. We use measured CNT spacingdistributions within the framework of detailed failure analysis to demonstrate thatboth the CNT density and the ratio of metallic to semiconducting CNTs playdominant roles in defining the failure probability of CNFETs. Besides, it is arguedthat the large-scale integration of these devices within an integrated circuit willbe feasible only if a specific range of CNT density with an acceptable ratio ofsemiconducting to metallic CNTs can be adjusted in a typical synthesis process.