CMOS Voltage-controlled Oscillator Research Articles

A 0.35-μm CMOS cross-coupled complementary Colpitts voltage controlled oscillator

This article presents a differential cross-coupled complementary Colpitts CMOS voltage-controlled oscillator (VCO).The low phase noise CMOS VCO has been implemented with the TSMC 0.35-μm 2P4M CMOS technology and adopts a pair of cross-coupled PMOS transistors to achieve faster start-up oscillation. The VCO operates from 6.16 to 6.5 GHz with 5.3% tuning range. The measured phase noise at 1 MHz offset is −121.12 dBc/Hz at 6.417 GHz. The power consumption of the VCO core is 6.16 mW. The figure of merit is −189.37 dBc/Hz. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26192

A miniature CMOS VCO with symmetric trace differential stacked spiral inductor

In this study, a miniature silicon-based symmetric trace differential stacked spiral inductor (SDSSI) was used in the design of a voltage controlled oscillator (VCO) using standard 0.18 μm CMOS technology. The SDSSI has a high self-resonance frequency (fsr) and quality factor (Q) in spite of using the stacking technique, because the parasitic capacitance between the layers is reduced by alternatively locating traces at different positions in each layer. The output power spectrum and phase noise of the designed VCO is −0.79 dBm and 114 dBc/Hz at 1-MHz offset frequency, respectively. The oscillation frequencies cover from 1.84 GHz to 2.38 GHz with a tuning range of 26%, while the occupied on-chip area of the VCO is only 350 × 450 μm2. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26073

A K-Band Low-Power Colpitts VCO With Voltage-to-Current Positive-Feedback Network in 0.18 $\mu{\rm m}$ CMOS

A circuit topology suitable for low-power Colpitts voltage-controlled oscillators (VCOs) is presented in this letter. By employing the proposed voltage-to-current positive-feedback network, the required transconductance for VCO startup can be reduced, leading to the minimized dc power for sustaining VCO oscillation. Moreover, the Q-factor enhanced varactor is used in this VCO design for phase noise improvement. Based on the proposed architecture, the fabricated VCO in standard 0.18 μm CMOS exhibits a 3.58% tuning range. Operating at 1.35-V supply voltage, the VCO core consumes 3.3-mW dc power. The measured phase noise is -110.82 dBc/Hz at 1 MHz offset from 18.95 GHz oscillation frequency. Compared with the recently published K-band 0.18 μm CMOS VCOs, it is observed that the proposed Colpitts VCO exhibits comparable circuit performance under low dc-power consumption.

An integrated 10 GHz low-noise phase-locked loop with improved PVT tolerance

An integrated phase-locked loop (PLL) with low phase noise is presented, which is robust with respect to variations of device parameters with process, supply voltage, and temperature (PVT). The low-noise CMOS voltage-controlled oscillator (VCO) employs two varactors for fine and coarse tuning. By using a CMOS charge pump with output biasing, the dc fine tuning voltage of the VCO and the loop dynamics of the PLL are well defined and fairly independent of PVT variations. Device noise in the charge pump and linearity of the phase detector are much improved by a two-transistor charge pump architecture for fine tuning. We measured a phase noise below ?131 dBc/Hz at 10 MHz offset and below ?94 dBc/Hz at 10 kHz offset over a tuning range of 1.2 GHz. An integrated phase error below 0.6° was measured, corresponding to an rms jitter below 160 fs. The chip was produced in a 0.25 μm low-cost SiGe BiCMOS technology, occupies a chip area of 2.25 mm2 and draws 60 mA from a 3 V supply.

A 60-GHz CMOS VCO Using Capacitance-Splitting and Gate–Drain Impedance-Balancing Techniques

The design and measurement of a 60-GHz 90-nm CMOS voltage-controlled oscillator is presented. To reduce the power consumption and to improve the phase-noise performance, a capacitance-splitting and a gate-drain impedance-balancing techniques, which are realized with an inductive divider, are proposed. With these techniques, the size of the cross-coupled pair is reduced. Analysis of the proposed techniques shows that the transistor <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g m</i> generation efficiency is improved and the oscillator noise factor is reduced. Moreover, the tank loaded quality factor is increased by balancing impedance levels across the transistor terminals. The 60-GHz oscillator was fabricated in a 90-nm CMOS technology. Under 0.6-V supply, the oscillator achieved a tuning range from 61.1 to 66.7 GHz, consuming only 3.16 mW. At 64 GHz, the phase noise is -95 dBc/Hz at 1-MHz offset.

A low-power low-phase-noise wide-tuning-range K-band VCO in 0.18-.MU.m CMOS

A low-phase-noise wide-tuning-range K-band voltage-controlled oscillator (VCO) is presented in this paper. By employing accumulation MOS (AMOS) varactors deposited between drain and source terminations of the cross-coupled pair, the tuning mechanism are enhanced, leading to a boosted VCO tuning range. Moreover, the phase noise can be improved due to the better cyclostationary noise property. Based on this architecture, the fabricated VCO in 0.18-µm CMOS exhibits a measured 18.2% tuning range. Operating at 0.6-V supply voltage, the VCO consumes 2.28-mW dc power excluding the buffers. The measured phase noise is -112.53dBc/Hz at 1-MHz offset from 24.68-GHz oscillation frequency. Compared to the recently published K-band 0.18-µm CMOS VCOs, it is observed that the proposed VCO can simultaneously achieve low phase noise, wide tuning range, and low dc-power dissipation.

Low Noise Phase CMOS Quadrature VCO with Superharmonic Coupling Using Cross-Couple Pair

This paper aims to introduce a quadrature VCO (voltage control oscillator) which applies superharmonic coupling. The presented quadrature VCO is suitable to be used, both with 2 × subharmonic mixers, as well as 4×subharmonic mixers. It would be impossible to avoid the presence of harmonics in CMOS VCO circuits. These harmonics are in general, undesirable signals which tend to accompany the desired fundamental signal. There are common-mode nodes (similar to those in the two source nodes in a cross-coupled VCO) in deferential VCO at which higher-order harmonics are present while the fundamental is absent in essence. We can make use of these second-order harmonics which are present at the common-mode nodes of two VCO in order to implement a quadrature connection between the fundamental outputs. The technique through which this is done is called superharmonic coupling. This CMOS quadrature VCO which applies active superharmonic coupling puts an excellent performance in show, with an output power –0.942 dBm for fundamental and –9.751 dBm for subharmonic, phase noise –107.2 dBc/Hz for fundamental and –114.8 dBc/Hz at a 1MHz offset. All of circuit applied are designed and simulated by ADS, 2008.

Wide tuning range W-band Colpitts VCO in 90 nm CMOS

A compact wide tuning range design of a CMOS voltage-controlled oscillator (VCO) at W-band frequencies is presented. The design employs a differential Colpitts configuration, using a bufferless transformer output and nested inductors. The gate bias is used for frequency tuning that achieves a wide range of 93.7–100.7 GHz. A peak output power of 4.7 dBm with power efficiency of 5.5% is achieved at 98.8 GHz and the phase noise is around −80 dBc/Hz at 1 MHz offset across the tuning range. The VCO uses a silicon area of 0.15 mm2 including pads and, depending on bias, consumes between 6–63 mW of DC power.

Design of a 24-GHz CMOS VCO With an Asymmetric-Width Transformer

A K-band CMOS voltage-controlled oscillator (VCO) is implemented with a 0.18- ¿m radio frequency CMOS process. For low supply voltage operation, a transformer-feedback topology using a transformer is proposed. The analysis of the transformer-feedback VCO is presented. This shows that the inductance ratio of the transformer must be optimized, and asymmetric-width transformers allow the easy optimization and the high Q-factor. Based on this analysis, the transformer design consideration of the transformer feedback VCO is presented. The VCO operates at 24.27 GHz with the phase noise of -100.33 dBc/Hz at 1-MHz offset, and it consumes 7.8 mW from a 0.65-V supply voltage.

개방 루프 다중 분할 링 공진기를 이용한 0.13 um 전압 제어 발진기 설계

In this paper, a novel voltage-controlled oscillator(VCO) using the open loop multiple split ring resonator(OLMSRR) is presented for improving the phase noise, implemented in 130 nm CMOS technology. Compared with the conventional CMOS LC resonator, the proposed CMOS OLMSRR has the larger coupling coefficient value, which makes a higher Q-factor, and has improved the phase noise of the VCO. The proposed CMOS VCO based OLMSRR has the phase noise of -99.67 dBc/Hz @ 1 MHz in the oscillation frequency. Compared with the VCO using the conventional CMOS LC resonator and the proposed VCO using the CMOS OLMSRR structure has been improved in 7 dB. The prototype 24 GHz CMOS VCO is implemented in 130 nm CMOS and occupies a compact die area of .

A 1.8–2.6 GHz CMOS VCO with switched capacitor array and switched inductor array

The design of a 1.76–2.56 GHz CMOS voltage-controlled oscillator (VCO) with switched capacitor array and switched inductor array is presented. Fabricated in 0.18 μm 1P6M CMOS technology, the VCO achieves a 37% frequency tuning range. The measured phase noise varies between −118.5 dBc/Hz and −122.8 dBc/Hz at 1 MHz offset across the tuning range. Power consumption is about 14.4 mW with a 1.8 V supply. Based on a reconfigurable LC tank with switched capacitor array and switched inductor array, the tuning range is analyzed and derived in terms of design parameters, yielding useful equations to guide the circuit design.

Fully-integrated wideband CMOS VCO with improved f – V linearity and low tuning sensitivity

A technique to improve the linearity of the frequency–voltage (f–V) characteristic and to reduce the differential tuning sensitivity, KVCO, of voltage-controlled oscillators (VCOs) is proposed. The VCO designed using the linearisation technique is tunable from 806 to 1113 MHz with a 34% tuning range and exhibits a nearly constant KVCO of 62 MHz/V over the entire frequency range.

Low Phase Noise G$ _{m}$-Boosted Differential Gate-to-Source Feedback Colpitts CMOS VCO

This paper presents a g m-boosted differential gate-to-source feedback Colpitts (GS-Colpitts) CMOS voltage-controlled oscillator (VCO) that consumes a lower oscillation start-up current. The proposed architecture allows a wider range of saturation mode operation for the switching transistors, which helps suppress AM-to-FM conversion by these transistors. In addition, the phase noise contribution of the flicker noise in the switching transistor is reduced through the capacitor feedback network of the Colpitts oscillator. As a result, the proposed topology can achieve better phase noise performance and a higher figure of merit (FOM) compared to a conventional NMOS-only cross-coupled VCO. The proposed VCO is implemented in a 0.18-mum CMOS for 1.78 to 1.93 GHz operation. At 1.86 GHz, the measurements show phase noise of -105 and -128 dBc/Hz (corresponding to FOM = 191.2) at offsets of 100 kHz and 1 MHz, respectively, while dissipating 1.8 mA from a 0.9-V supply.

An enhanced close-in phase noise LC-VCO using parasitic V-NPN transistors in a CMOS process

A differential LC voltage controlled oscillator (VCO) employing parasitic vertical-NPN (V-NPN) transistors as a negative gm-cell is presented to improve the close-in phase noise. The V-NPN transistors have lower flicker noise compared to MOS transistors. DC and AC characteristics of the V-NPN transistors are measured to facilitate the VCO design. The proposed VCO is implemented in a 0.18 μm CMOS RF/mixed signal process, and the measurement results show the close-in phase noise is improved by 3.5–9.1 dB from 100 Hz to 10 kHz offset compared to that of a similar CMOS VCO. The proposed VCO consumes only 0.41 mA from a 1.5 V power supply.

Design of 1.9 GHz RF CMOS VCO

A voltage controlled oscillator (VCO) module is designed, which can be used for the third generation mobile communication (3G) system. The circuit is simulated by spectre radio frequency (RF) by TSMC 0.25 μm CMOS process. During the simulation, the performance parameters of the designed VCO are as follows: tuning range 1.804 GHz–2.039 GHz, phase noise − 136.457 dBc/Hz @1 MHz, − 146.045 dBc/Hz@3 MHz, supply voltage 2.5 V, voltage output rate of 0.8 V–2.6 V, power consumption 25 mW. The layout of the related circuit is drawn by the Virtuoso Layout Editor.

A V-Band CMOS VCO With an Admittance-Transforming Cross-Coupled Pair

A novel circuit topology suitable for the implementation of CMOS voltage-controlled oscillators (VCOs) at millimeter-wave frequencies is presented in this paper. By employing transmission line segments to transform the admittance of the additional cross-coupled pair, the proposed LC-tank VCO can sustain fundamental oscillation at a frequency close to the fmax of the transistors. Using a standard 0.18 mum CMOS process, a V-band VCO is realized for demonstration. The fabricated circuit exhibits a frequency tuning range of 670 MHz in the vicinity of 63 GHz. The measured output power and phase noise at 1 MHz offset are -15 dBm and -89 dBc/Hz, respectively. Operated at a 1.8 V supply voltage, the VCO core and the output buffer consume a total DC current of 55 mA.

A 5 GHz Differential Colpitts CMOS VCO Using the Bottom PMOS Cross-Coupled Current Source

A low phase noise differential Colpitts voltage-controlled oscillator (VCO) with the bottom series PMOS cross-coupled current source is presented. The core Colpitts VCO adopts a pair of PMOS as the biased current source at the bottom, instead of a conventional NMOS topology, to achieve a better phase noise performance as the PMOS has lower flicker and white noise than those of NMOS and the output power spectral density of PMOS operated in bottom-biased type is further less than that in top-biased one in the same power consumption. The fabricated VCO operates from 4.9 to 5.46 GHz with 10.6% tuning range when the power consumption is below 6.4 mW with a supply voltage of 1.8 V. The measured phase noise at 100 kHz offset is -100.3 dBc/Hz at 5.46 GHz and achieves a good FOM performance of -187 dBc/Hz.

A Low-Parasitic and Common-Centroid Cross-Coupled CMOS Transistor Structure for High-Frequency VCO Design

This letter reports a cross-coupled transistor structure that allows simple routing, induces no gate-drain overlap interconnect capacitances, minimizes the parasitic resistances of interconnects, allows smaller drain-junction parasitic capacitances, and provides inherent common-centroid characteristic, all of which help to improve the high-frequency and wideband performances of CMOS voltage-controlled oscillators (VCOs). The proposed cross-coupled transistor structure is applied for a 26.2-GHz differential VCO design which dissipates 7.3 mA from 1.8-V supply using 0.18-mum CMOS. Measurements show 2.1-GHz, 29%, and 4-dB improvements in operating frequency, tuning range, and phase noise compared to those of the VCO using a conventional cross-coupled transistor layout, respectively. The VCO with the proposed transistor structure shows the phase noise of -113.7 dBc/Hz at 1 MHz, which corresponds to <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FOM</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FOMT</i> of -190.4 and -194 dBc/Hz, respectively.

Ultra wideband, low-power, 3–5.6 GHz, CMOS voltage-controlled oscillator

In this paper, a low-power inductorless ultra wideband (UWB) CMOS voltage-controlled oscillator is designed in TSMC 0.18μm CMOS technology as a part of a ultra wideband FM (UWBFM) transmitter. The VCO includes a current-controlled oscillator (CCO) which generates output frequencies between 1.5 and 2.8GHz and a voltage-to-current (V-to-I) converter. A low-power frequency doubler based on a Gilbert cell, which operates in weak inversion, doubles the VCO tuning range achieving oscillation frequencies between 3 and 5.6GHz. Thus, the well-known proportionality between the oscillation frequency and the bias tuning current in CCOs is avoided for the entire achieved tuning range, resulting in a lower power design. The employed architecture provides high suppression, over 45dB, of the 1st and 3rd harmonics, while enabling high-frequency operation and conversion gain due to the unbalanced structure and the single-ended output. The current consumption is 5mA at a supply voltage of 1.8V. The VCO exhibits a phase noise of −80.56dBc/Hz at 1MHz frequency offset from the carrier and a very high ratio of tuning range (60.4%) over power consumption equal to 8.26dB which is essential for a UWBFM transmitter.

An eight‐phase CMOS voltage controlled oscillator

AbstractThis article presents an eight‐phase low phase noise CMOS voltage controlled oscillator (VCO). The low noise CMOS VCO has been implemented with the TSMC 0.18 μm 1P6M CMOS technology and adopts two quadrature cross‐coupled nMOS‐core VCOs injection‐locked through the second‐harmonic. The VCO operates from 5.1 GHz to 5.5 GHz with 7.54% tuning range. The measured phase noise at 1 MHz offset from 5.1 GHz is about −115.4 dBc/Hz. The power consumption of the VCO core is 7.43 mW at the supply voltage of 1 V. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1225–1228, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24270