CMOS Technology Research Articles

A Direct-Digital 40 μA 100 kb/s Intracardiac Communication Receiver with 250 μs Startup Time for Low Duty-Cycle Leadless Pacemaker Synchronization.

The first commercial dual-chamber leadless pacemaker (LLPM) was introduced recently. The system combines two separate implants situated in the right atrium and the right ventricle of the heart. Implant synchronization is accomplished with conductive intracardiac communication (CIC) using the myocardium and blood as transmission channel. Successful implant synchronization of this dual-chamber LLPM has been demonstrated. However, the continuously active synchronization transceivers, consuming about 800 nA, cause a 25-45% reduction in the projected device longevity. This work proposes an alternative strategy for power-optimized LLPM synchronization, which is based on synchronous duty-cycling of the transceivers and direct-digital CIC (DD-CIC). In line with this strategy, a novel low-power DD-CIC receiver for short-packet communication based on Manchester-encoded data and with fast startup time is presented. The circuit was fabricated in 180 nm CMOS technology and analyzed with respect to sensitivity, current consumption and startup time under highly duty-cycled operation. The receiver achieves a sensitivity of 81.6±7.4 μV at a data rate of 100 kb/s, with an active current consumption of 39.1±0.6 μA and a startup time below 250 μs. Operating the receiver as specified by the proposed LLPM synchronization strategy reduces the current consumption to a measured average value of 73 nA. In conclusion, this work suggests synchronous duty-cycling for CIC-based implant synchronization as a promising concept to severely reduce the current consumption of contemporary dual-chamber LLPMs. Consequently, device longevity may be increased significantly, potentially reducing the frequency of costly and complication-prone re-interventions.

A scalable top-gate graphene field effect transistor with a polydimethylsiloxane dielectric

The limitations of modern CMOS technology have created a call to action for novel devices with great scalability potential. Graphene has been recognized as a suitable material for an enhanced transistor channel based on its incredibly large conductivity while also being easily scaled. Previous research has noted the importance of a top gate device structure, which is difficult to accomplish for graphene transistors due to graphene's incompatibility with oxide growth processes. A novel process flow for graphene field effect transistors with scalability is presented. The emphasis is on the growth of multilayer graphene using chemical vapor deposition and the implementation of polydimethylsiloxane as a gate dielectric. Polydimethylsiloxane gate insulator thickness of 815 nm and 570 nm were successfully developed on 4in large-scale wafers. Two devices of similar channel dimensions and different dielectric were compared and mobilities of 14.57cm2V−1s−1 and 0.44 cm2V−1s−1 were measured. Gate voltage sweeps from -20 V to 20 V also demonstrated channel current modulation with a charge neutrality point between 5 V and 8 V, indicating achievement of expected device operation.

A 500 mVpp Input Range First-Order VCO-Based ADC with a Multi-Phase Quantizer for EEG Recording Front Ends

This paper proposes a VCO-based ADC with first-order noise shaping for EEG signal recording front ends. Addressing the challenge of applying analog integrators in advanced processes due to low voltage issues, a multi-phase quantizer structure is introduced based on V-F conversion within the VCO structure, resulting in lower analog power consumption at the same output bit-width. By introducing a form of Gray code encoding, errors caused by circuit metastability are limited to within 1 bit. Considering the effects of motion artifacts and the electrode DC offset, the circuit achieves a wide input range of 500 mVpp by adjusting the feedback coefficients. A prototype ADC is fabricated using 180 nm CMOS technology, operating at a 1.8 V/1 V power supply voltage, with power consumption of 17.1 μW, while achieving a 62.1 dB signal-to-noise and distortion ratio (SNDR) and 55.2 dB dynamic range (DR). The proposed ADC exhibits input noise of 8.64 μVrms within a bandwidth of 0.5 Hz–5 kHz.

A Low-Power Tunable Differentiator Using Voltage Difference Transconductance Amplifier (VDTA) for Tunable PD Controller

The electronically tunable differentiator using a voltage difference transconductance amplifier (VDTA) is proposed, designed, and analyzed. The simulation was done using the Cadence Virtuoso tool of 45[Formula: see text]nm CMOS technology with a supply voltage of ±0.9[Formula: see text]V. The maximum power consumption of the proposed circuit is 246[Formula: see text][Formula: see text]W with a total harmonic distortion of 5.4%. The output can be tuned using four parameters: [Formula: see text], [Formula: see text], [Formula: see text], and [Formula: see text]. The transconductance can be varied using bias current and aspect ratio of CMOS transistors. The utilized area of VDTA layout is [Formula: see text]. The parasitic impedance affects the output of post-layout simulation and causes little delay compared to schematic. The design has been experimentally verified using LM13700 integrated circuit. The results of the proposed circuit show good agreement with the experimental results and mathematical expressions. The proposed circuit can be used as a tunable PD controller, in which the voltage gain of the proposed circuit is [Formula: see text]. The design is versatile and can be used in different applications such as temperature control systems, photo voltaic cells, waveform generators, microwave communications systems, and instrumentation systems.

A 12-Bit 1.2-GS/s Current-Steering DAC in 45-NM CMOS Technology

This research paper presents a 12-bit 8–4-segmented current-steering DAC (digital-to-analog converter) that offers notable advantages, particularly in terms of its reduced power consumption compared to other similar designs. The exceptional performance of our DAC can be attributed to two key factors: the use of a thermometer encoder and an efficient digital input bit segmentation. These features contribute to enhanced precision and reduced power requirements, setting our DAC apart from the existing solutions in the field. These enhancements significantly reduce glitches and improve the accuracy of the DAC’s output. DAC dissipates a total power of about 44.95[Formula: see text]mW when running at a sample rate of 1.2[Formula: see text]GHz with the CMOS technology of 45[Formula: see text]nm. While the supply input voltage is held constant at 1.2[Formula: see text]V, the DAC’s digital input is pulsating in nature in which the ON voltage is 1[Formula: see text]V and OFF voltage is 0[Formula: see text]V. Also, the DAC has a spurious-free dynamic range (SFDR) of 41.77[Formula: see text]dB.

Efficient 32-nm CNTFET-Based 1-Bit Adder: A Fast and Energy-Optimized Design

CNTFETs are a shows potential choice for traditional CMOS technology due to their potential for lesser power consumption and superior performance. In the present paper, a new 1-bit hybrid full adder has been deliberated and proposed using both pass transistor (PT) and transmission gate logics (TGL), which utilizes a total of 16 transistors. The combination of PT and TGL can lead to improved power efficiency, reduced delay, and enhanced circuit performance in various VLSI applications. For 0.9 V supply voltage at 32-nm CNTFET technology, the power consumption is 0.0748 μW, which is to be an exceptionally low value with a lesser delay of 7.586 Ps and the power-delay-product (PDP) of 0.5674 aJ. The results obtained from this analysis demonstrate the power efficiency, speed, and overall performance of the proposed full adder design. The combination of 32-nm CNTFET technology, deliberate circuit design choices, and the use of specific logic elements (CMOS inverters and strong transmission gates) contributes to the reported characteristics. Using a 0.9 V supply voltage and 32-nm Stanford CNTFET Model technology, the suggested 1-bit adder circuit's concert was investigated using the Mentor Graphics Tool. Finally, using the proposed 1-bit full adder circuit, an N-bit ripple carry adder (N=8, 16 & 32) is implemented and demonstrated. The Simulation results of the 8-bit RCA with a power consumption of 0.373 μW, the delay is 16.852 Ps and the PDP is 6.2857 aJ. These results show that proposed RCA’s have better performance compared to the already reported designs in terms of performance, speed, and power economy.

A symmetrical fully-integrated CMOS doherty power amplifier

This paper presents a new method to enhance the efficiency of a symmetrical doherty power amplifier (DPA) by fully utilizing the current driving capability of a class-C biased peaking amplifier. In this method, with utilization of the passive voltage gain concept, the input matching networks are designed in a way that the peaking path experiences a higher voltage gain than the carrier path, at high powers. As a result, the higher drive voltage of the peaking amplifier compensates for its lower gate bias and identical peak output currents for both amplifiers can be achieved. For demonstration purpose, a two-stage symmetrical DPA with a power utilization factor (PUF) of about unity is designed and fabricated in a standard 0.18-μm CMOS technology. The measurement results at 2.6 GHz show a power gain of 21 dB and an 1 dB compression point of 21.3 dBm. The peak power added efficiency (PAE) is 35% and the PAE at 6 dB power back-off (PBO) is better than 23%.

An analog to digital converter in a SiC CMOS technology for high-temperature applications

Integrated circuits based on wide bandgap semiconductors are considered an attractive option for meeting the demand for high-temperature electronics. Here, we report an analog-to-digital converter fabricated in a silicon carbide complementary metal–oxide–semiconductor technology now available through Europractice. The MOSFET component in this technology was measured up to 500 °C, and the key parameters, such as threshold voltage, field-effect mobility, and channel-length modulation parameters, were extracted. A 4-bit flash data converter, consisting of 266 transistors, is implemented with this technology and demonstrates correct operation up to 400 °C. Finally, the gate oxide quality is investigated by time-dependent dielectric breakdown measurements at 500 °C. A field-acceleration factor of 4.4 dec/(MV/cm) is obtained by applying the E model.

Horn Antenna on Chip Operating at 180 GHz Using the SiGe CMOS Process

This article proposes a chip antenna on millimeter-Waves. This antenna combined with TSMC 180 nm SiGe CMOS technology has the advantage of being small in size and is suitable for wireless communications. The multilayer architecture Horn antenna implemented on M4–M6 can meet both process reliability specifications and radiation performance. The results of the simulation show that the maximum gain is −4.2 dBi. The return loss measurement results are almost consistent with the simulation results, and the bandwidth range is 177.4–183 GHz. This article first describes the antenna production process and measurement results, analyses the impact of the parameters on the antenna, and further compares it with other designs. The excellence of this article is that it proposes a design that solves the problem of large millimeter wave loss and successfully reduces the area. At the same time, this article can contribute to readers’ future optimization and continued research directions, and at the same time contribute simulation and measurement trends to let readers understand the stability of CMOS chip antenna simulation and measurement.

VLSI design for adjustable compression rate in lossless/lossy compression of EEG signal

In the realm of remote health monitoring, the compression of electroencephalography (EEG) signals at the edge holds significant importance. This paper presents a VLSI structure capable of adjustable compression rates to achieve both lossless and lossy compression of EEG data, catering to environments requiring flexible adjustment of compression types and rates. The architecture integrates two-dimensional discrete wavelet transform (2D-DWT) and the Set Partitioning in Hierarchical Trees (SPIHT). Notably, the Haar wavelet lifting structure is employed in 2D-DWT, and the SPIHT scanning sequence is optimized for enhanced resource efficiency. The proposed algorithm is validated using the CHB-MIT Scalp EEG Database, demonstrating compression ratios of ≥1.95 for normal EEG and ≥1.69 for epileptic EEG. Through synthesis and layout design in the 130 nm CMOS technology, the resulting circuit achieves a maximum clock frequency of 57 MHz and occupies an area of 81 kμm2, with an average power consumption of less than 0.71nj per data for 16-bit data. These findings affirm the efficacy of the proposed VLSI structure for achieving efficient lossless/lossy compression of edge EEG data.

A Broadband Millimeter-Wave 5G Low Noise Amplifier Design in 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS

This paper presents a broadband millimeter-wave (mm-Wave) low noise amplifier (LNA) designed in a 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Electromagnetic (EM) simulations suggest that the LNA has a 3-dB bandwidth (BW) from 17.8 to 42.4 GHz and a fractional bandwidth (FBW) of 81.7%, covering the key frequency bands within the mm-Wave 5G FR2 band, with its noise figure (NF) ranging from 2.9 to 4.9 dB, and its input-referred 1-dB compression point (IP1dB) of −17.9 dBm and input-referred third-order intercept point (IIP3) of −8.5 dBm at 28 GHz with 15.8 mW DC power consumption (PDC). Using the FOM (figure-of-merit) developed for broadband LNAs (FOM = 20 × log((Gain[V/V] × S21-3 dB-BW [GHz])/(PDC [mW] × (F-1)))), this LNA achieves a competitive FOM (FOM = 18.9) among reported state-of-the-art mm-Wave LNAs in the literature.

A reduced complexity rate-matching and channel interleaver/de-interleaver for 5G NR

Rate matching and channel interleavers play a pivotal role in code rate adaptation and minimizing burst errors in communication systems. The data and control channels in the Fifth generation (5G) New Radio (NR) employs distinct channel interleavers/de-interleavers for reducing bit error rate. However, the independent implementation results in a substantial increase in silicon cost. To address this challenge, hardware sharing is pivotal for optimizing resource utilization and improving overall system performance. This study introduces a rate-matching architecture and a simple algorithm for the creation of a new Shared-Resource Channel interleaver/De-interleaver (SRC) architecture. The proposed work ensures low complexity tailored for both data and control channels within the 5G NR framework by incorporating the hardware sharing technique. The proposed SRC architecture, synthesized on the Virtex-7 Field Programmable Gate Array (FPGA), showcases noteworthy advancements over existing 5G NR interleaver architecture, achieving a notable 23% reduction in resource utilization. Through implementation using the Qflow Compiler in 45 nm CMOS technology, the ASIC synthesis of the proposed design demonstrates a substantial decrease in hardware complexity and area by 44.6% and 43%, respectively. Furthermore, the proposed architecture exhibits a 19.2% reduction in power consumption compared to its existing counterpart in 5G NR. The proposed integrated design demonstrates a remarkable resource efficiency by occupying nearly half the resources compared to individual implementations.

A Defects Classification Algorithm for the Hybrid OBT–IDDQ Fault Diagnosis Technique in Analog CMOS Integrated Circuits

In this paper, a robust fault detection methodology for complex analog CMOS integrated filters is presented. It is based on combining the two types of testing methodologies, Oscillation-Based Testing (OBT) and IDDQ testing, i.e., measuring of the power-supply current ([Formula: see text]). The proposed methodology is applied to the Bi-quad Sallen–Key band-pass (BP) filter cell with relatively complex, two-stage, class-AB-output, operational amplifier (opamp) topology. The filter is custom designed targeting the 180-nm CMOS technology. Hundreds of time-domain simulations and analyses of the circuit output signal are performed in order to obtain the fault dictionary. The presented results show that the proposed hybrid OBT–IDDQ methodology is significantly more efficient in the defects coverage than any of the particular test methodologies alone. Subsequently, the specific algorithm for the defects classification is proposed. Based on the classification, certain degree of diagnosis of the individual defect, or a group of defects, can be achieved.

Analytical Modelling and Performance Characterization of Hybrid SET-MOS

Gordon Moore's "Moore's Law" suggests chip functionality demand doubles every 1.5-2 years, with global semiconductor technology roadmap recommending sub-nanometer ranges for IC production in nano-electronics. The single electron transistor (SET) is a promising nano-scale device that can be co-integrated with CMOS technology to improve performance. The paper explores the tunnelling effect between nanoparticles in single electron transistors (SET), revealing coulomb blockade transactions and resistance increases with reduced bias. It focuses on single electron transistors and pre-terminal devices, discussing IV characteristics, coulomb diamond plots, and metallic quantum dots. This research also explores the hybrid SET-FET based model, focusing on developing a room temperature SET in CMOS comparable technology with a Field Effect Transistor (FET). Prediction models and exploratory studies guide the integration of SET-FET technology. SIMON is a comprehensive simulator designed for single-electron devices and circuits. The output current is not impacted by capacitances up to 1 pF, and FET size in the micron range are appropriate for SET signal amplification up to 4 µA. This research explores the modelling of SET-FET technology in highlighting its ability to mitigate drawbacks in low drive current when combined with a FET. It also explores device variability mitigation in nanoscale array configurations, finding that SET-FET significantly reduces variability in larger arrays, despite the impact of capacitance and resistance.

A wireless stimulator system-on-chip with an optically writable ID for addressable cortical microimplants

For a profound understanding of brain function and connectivity, there is an escalating need to cover expansive cortical areas. While external recording methods such as electroencephalography (EEG) are prevalent, direct bidirectional interaction with the neural network mandates implanted electrodes. Integrating all microimplant functionalities into a single integrated circuit (IC) increases design complexities. Thus, challenges in the intricacies of distributed system networking have frustrated the drive toward implant miniaturization. In this context, we introduce addressable microimplants equipped with gate oxide-based anti-fuse (AF) Chip-IDs activated by a photodiode (PD) array. This mechanism generates a binary ID code by selectively degrading the anti-fuse gate oxide, eliminating the need for I/O PADs. These ID-equipped wireless micro-implants are distributed over vast regions, enabling bidirectional neural interfacing through recording and stimulation. We successfully fabricated an 8-channel wireless microstimulator and a spike-sensor in 180 nm CMOS, demonstrating the efficacy of the 5-bit Chip-ID in real-time networking scenarios. The system draws power from RF electromagnetic waves, receiving 1.2 V and 1 mW, and employs amplitude modulation at a 900 MHz carrier frequency for data communication. The minimum amplitude detected for demodulation was 350 mV, regenerating a 1 MHz clock and 34-bit command data. When tested, the array of eight microstimulators responded distinctly based on sequential command parameters. This IC realized in TSMC 180 nm CMOS technology, occupies only a 1 mm2 area.

Implementation of Lightweight Convolutional Neural Networks with an Early Exit Mechanism Utilizing 40 nm CMOS Process for Fire Detection in Unmanned Aerial Vehicles.

The advancement of unmanned aerial vehicles (UAVs) enables early detection of numerous disasters. Efforts have been made to automate the monitoring of data from UAVs, with machine learning methods recently attracting significant interest. These solutions often face challenges with high computational costs and energy usage. Conventionally, data from UAVs are processed using cloud computing, where they are sent to the cloud for analysis. However, this method might not meet the real-time needs of disaster relief scenarios. In contrast, edge computing provides real-time processing at the site but still struggles with computational and energy efficiency issues. To overcome these obstacles and enhance resource utilization, this paper presents a convolutional neural network (CNN) model with an early exit mechanism designed for fire detection in UAVs. This model is implemented using TSMC 40 nm CMOS technology, which aids in hardware acceleration. Notably, the neural network has a modest parameter count of 11.2 k. In the hardware computation part, the CNN circuit completes fire detection in approximately 230,000 cycles. Power-gating techniques are also used to turn off inactive memory, contributing to reduced power consumption. The experimental results show that this neural network reaches a maximum accuracy of 81.49% in the hardware implementation stage. After automatic layout and routing, the CNN hardware accelerator can operate at 300 MHz, consuming 117 mW of power.

Optoelectronic dual-synapse based on wafer-level GaN-on-Si device incorporating embedded SiO2 barrier layers

Optoelectronic synapses possess the potential to seamlessly integrate perception, storage, and neuromorphic computation, thereby offering advantages in constructing artificial vision systems. Gallium nitride (GaN) materials, renowned for their exceptional optoelectronic characteristics and the compatibility of Silicon-based GaN (GaN-on-Si) with CMOS technology, contribute significantly to realizing large-scale optoelectronic neuromorphic circuits. In this study, we present an optoelectronic dual-synapse based on a structurally-improved AlGaN/GaN MIS-HEMT with ring-shaped SiO2 barriers embedded surrounding the source and drain regions. This device facilitates simultaneous signal transmission to the source and drain through current-limiting electrical breakdown beneath the gate. This integration of two discrete optoelectronic synapses within a single device enhances neural signal transmission nodes and branching connectivity, facilitating the construction of large-scale neuromorphic circuits. Under the co-influence of electrical and optical pulses, the device not only demonstrates excellent optoelectronic synaptic characteristics but also exhibits the ability to modulate the critical wavelength of synaptic responses by varying the source/drain voltage, effectively simulating the light signal recognition observed in biological retinas. The synergistic operation of the two sub-synapses enables a successful transition from short-term potentiation (STP) to long-term potentiation (LTP). Furthermore, leveraging the device's STP, we emulate the function of artificial retina through a GaN optoelectronic neuromorphic array, successfully achieving image recognition in conjunction with artificial neural networks (ANNs). The devices developed in this study, based on GaN-on-Si allow wafer-level manufacturing, provding a promising avenue for the large-scale production of optoelectronic synapse devices and the realization of artificial vision systems.

A 5.12-Gbps serializer circuit for front-end fast readout electronics of silicon pixelated detectors

Advanced synchrotron radiation sources are major facilities for analyzing the formation and evolution of material structure in multidisciplinary research, owing to their high luminosity, low emittance, wide energy bandwidth and other characteristics. In China, several advanced synchrotron radiation sources are under construction, including the HEPS (High Energy Photon Source) and SHINE (Shanghai high repetition rate X-ray Free Electron Laser and extreme light facility). These facilities are poised to become major multidisciplinary research platforms in China. To meet the requirements of pixel detectors in these facilities, dedicated pixel readout chips are being developed, including HEPS-BPIX and HYLITE. This paper presents a high-speed serializer circuit developed in a commercial 130-nm CMOS technology for the full-scale (128 × 128) pixel readout chip of HYLITE, which requires a data rate of 4 Gbps currently. The serializer consists of a 16-to-1 binary-tree multiplexer, a ring-oscillating-based phase-locked loop (RO-PLL) and a current-mode logic driving stage with a multi-stage pre-amplifier. Test results demonstrate its expected functionality within a wide operating range from 0.52 Gbps to 5.5 Gbps. At 5.12 Gbps, the measured jitter values are about 2 ps for random jitter, 20 ps for deterministic jitter, and 47 ps for total jitter with a 10−12 bit error rate. Additionally, the horizontal and vertical eye openings are 0.84 UI and 72%, respectively. These positive results indicate that the serializer meets the requirements of HYLITE.

A 0.3 V OTA with Enhanced CMRR and High Robustness to PVT Variations

In this paper, we present a 0.3 V body-driven operational transconductance amplifier (OTA) that exploits a biasing approach based on the use of a replica loop with gain. An auxiliary amplifier is exploited both in the current mirror load of the first stage of the OTA and in the replica loop in order to achieve super-diode behavior, resulting in low mirror gain error, which enhances CMRR, and robust biasing. Common-mode feedforward, provided by the replica loop, further enhances CMRR. Simulations in a 180 nm CMOS technology show 65 dB gain with 2 kHz unity-gain frequency on a 200 pF load when consuming 9 nW. Very high linearity with a 0.24% THD at 90% full-scale and robustness to PVT variations are also achieved.

Characterization of the radiation tolerant ToASt ASIC for the readout of the PANDA MVD strip detector

The ToASt ASIC is a 64-channel integrated circuit developed for the readout of the Silicon strip detector project designed to be placed in the Micro-Vertex Detector of the PANDA experiment. ToASt is implemented in a commercial 110 nm CMOS technology and can provide information on the position, time, and deposited energy of the particle passing through the detector. Its time resolution is given by its 160 MHz master clock.The ASIC has been developed in the framework of the European FAIRnet project.The chip has been characterized electrically both standalone and coupled with sensors, with focus on its noise performances. It has also been tested for radiation tolerance, both in terms of Total Ionizing Dose and Single Event Upset.In particular, this work aims to guarantee that the studied ASICs can sustain the levels of ionizing radiation expected in the PANDA experiment and to study the noise characteristics for the two polarities of the ASIC.