CMOS Spiral Inductors Research Articles

Analytic Design of on-Chip Spiral Inductor with Variable Line Width

On-chip spiral inductors with variable line width layouts are known for their high quality factor (Q-factor). In this paper, we present an analytical approach to facilitate the design of such inductors. Based on an analysis of ohmic and eddy-current losses, we first derive an analytical formula for the metal resistance calculation of a spiral inductor. By minimizing the metal resistance, a simple design equation for finding the proper line width of each coil is then presented. Several 0.18 μm CMOS spiral inductors are investigated, via electromagnetic simulations and experimental studies, to test the proposed resistance calculation, as well as the variable line width design method. It is found that the developed resistance calculation can effectively model the metal-line resistance of a spiral inductor. Moreover, the inductor with a variable line width obtained using the proposed method can significantly improve the Q-factor with little compromise to inductance, which validates the capacity of the developed variable line width design technique. Since the proposed approach can be carried out using analytical calculations, it may be a more efficient design method than those previously reported in the literature.

Active Inductor-Based Ultra-Wideband Low Noise Amplifier for Rejection of Wireless LAN Interference

This paper presents a low noise amplifier (LNA) for the ultra-wideband (UWB) application in the range 3.1–10.6 GHz based on active inductor topology. The LNA is designed to provide a flat gain and to reject wireless local area networking interference at 5–6 GHz band. An active inductor based on the feedback resistor topology is proposed in this work and integrated with the LNA. The use of an active inductor instead of a conventional CMOS spiral inductor provides advantages over the area, quality factor, and inductance. The active inductor provides a relatively uniform inductance at 5–6 GHz and is used to design an on-chip notch filter circuit, which achieves a maximum attenuation of 45 dB at the center frequency of ~5.6 GHz. The LNA is designed and processed in the standard 0.18 mm CMOS technology. The simulated LNA exhibits the gain of 20 dB and a noise figure of less than 3.7 dB in the non-interfering bands. The input (S11) and output return losses (S22) are less than –10 and –12 dB, respectively, in the allocated UWB frequency spectrum, and amplifier occupies a chip area of 0.54 µm2. The proposed LNA has a superior flat gain, excellent interference rejection, minimum return losses, and a low noise figure in the intended operation band. This LNA finds important application in the radiofrequency front-end devices for UWB application.

Quality factor optimisation of spiral inductor using firefly algorithm and its application in amplifier

This proposal details an optimised design of a CMOS spiral inductor for output matching circuit of low noise amplifier by employing nature inspired intelligence-based technique called firefly optimisation algorithm (FA). Optimisation of these parameters has been carried out by considering single objective function. Penalty factor method is considered for handling the constraints. Using FA technique, the inductor with a high quality factor of 5.87 is obtained at 5.5 GHz frequency in Matlab environment. A computer-aided design tool ASITIC is used for the validation. The output matching circuit of low noise amplifier is designed using pi model obtained from ASITIC. The designed LNA has a cascode structure with inductive source degeneration topology and is implemented in UMC 0.18 µm CMOS technology using CADENCE software. The designed LNA has a simulated value at 5.5 GHz frequency.

Analysis of modeling approaches for on-chip spiral inductors

The recent modeling approaches for on-chip spiral inductors are extensively investigated and compared. The key features of the models are detailedly analyzed. By actual implementation of each model's parameter extraction procedure, the pros and cons of equivalent circuit topologies, parameter extraction techniques, and fitting capacity of models are provided, including 1-π, 2-π, and T-models. 1-π models and T-models are proved to be adequate for modeling distributed effect. 2-π models are more convenient in fitting asymmetric inductors. The transfer function of the spiral inductor is employed in the singularity analysis of the models. The proposals are verified by measured the S-parameters of 10 fabricated CMOS spiral inductors up to 40 GHz. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2012. © 2012 Wiley Periodicals, Inc.

A unified analytical and scalable lumped model of RF CMOS spiral inductors based on electromagnetic effects and circuit analysis

An enhanced scalable compact model for on-chip RF CMOS spiral inductors is presented. By considering layout and technology parameters, under quasi-static approximation, the model elements are all expressed analytically and based on electromagnetic effects. Frequency dependent behavior of CMOS spiral such as skin and proximity effects, and decrease of equivalent series resistance due to substrate coupling is considered. The model is suitable to be easily implemented in design kits by foundry and provides interesting accuracy to be used by CMOS Radio Frequency Integrated Circuits designers.

A Wideband and Scalable Model of Spiral Inductors Using Space-Mapping Neural Network

A wideband and scalable model of RF CMOS spiral inductors by virtue of a novel space-mapping neural network (SMNN) is presented. A new modified 2-pi equivalent circuit is used for constructing the SMNN model. This new modeling approach also exploits merits of space-mapping technology. This SMNN model has much enhanced learning and generalization capabilities. In comparison with the conventional neural network and the original 2-pi model, this new SMNN model can map the input-output relationships with fewer hidden neurons and have higher reliability for generalization. As a consequence, this SMNN model can run as fast as an approximate equivalent circuit, yet preserve the accuracy of detailed electromagnetic simulations. Experiments are included to demonstrate merits and efficiency of this new approach.

Efficient modeling of RF CMOS spiral inductors using generalized knowledge-based neural network

Efficient modeling of RF CMOS spiral inductors by virtue of a novel generalized knowledge-based neural network (GKBNN) is presented. Prior knowledge of on-chip inductors is used for constructing the GKBNN. This new modeling approach also exploits merits of the iterative multi stage algorithm. This GKBNN has much enhanced learning and generalization capabilities. Comparing with the conventional neural network or the knowledge-based neural network, this new GKBNN model can map the input---output relationships with fewer hidden neurons and has higher reliability for generalization. As a consequence, this GKBNN model can run as fast as an approximate equivalent circuit model yet generate results as accurate as detailed electromagnetic simulations. Experiments are included to demonstrate merits and efficiency of this new approach.

Scalable compact circuit model and synthesis for RF CMOS spiral inductors

A scalable industry-oriented, 24-element 2-/spl pi/ compact circuit model for on-chip RF CMOS spiral inductors is presented. It has a good accuracy up to self-resonant frequency (SRF). Two levels of modeling approaches are provided, which are: 1) the fixed model, which extracts the values of circuit elements directly from the measured S-parameters of a given device, achieving high accuracy, but no scalability and 2) the scalable model, in which circuit elements are related to the geometry (i.e., layout) through a set of formulas with model parameters calibrated upon a few testing devices. The synthesis procedure is also discussed, which includes the scalable model and a SPICE simulator as the evaluation method within the iteration loop.

A New Circuit Augmentation Method for Modeling of Interconnects and Passive Components

This paper presents a new methodology for automated broadband model generation from S-parameter data for interconnects and passive components. The new methodology is based on augmenting an existing equivalent circuit model with a macromodel (black-box) network described by rational functions while simultaneously perturbing the equivalent circuit component values. The macromodel network is determined using standard least-squares or vector-fitting approaches. The perturbation of the equivalent circuit parameter values is achieved during the macromodel generation by means of global optimization based on intelligent search algorithms. The new approach is demonstrated on several two-port test example structures including a broadband probe tip structure and a CMOS spiral inductor.

Analysis on the effect of parallel current path on the quality factor of CMOS spiral inductors for 1–10 GHz

A structure of spiral inductor having a parallel current path through the branch of the metal strip was designed to achieve a quality ( Q) factor enhancement compatible with conventional CMOS and/or established SiGe process in RF and microwave arena. The Q factor enhanced by 12% was quantitatively analyzed with a lumped-element model and its origin was investigated at a structural point of view. As a result we noted that the parallel-branching structure greatly reduced the series resistance of the inductor at a high frequency range of GHz by suppressing current crowding and in turn enhanced the Q factor beyond the additional parasitic capacitance.

S -parameter formulation of quality factor for a spiral inductor in generalized two-port configuration

This paper formulates various quality (Q) factors associated with the applications of on-chip spiral inductors to radio-frequency integrated circuits using S-parameters. The formulations start with the Q factor of a spiral inductor in a generalized two-port configuration based on a new complex-power approach and then extend to the Q factors of a tank and matching circuits that use the spiral inductors. In the demonstration, the two-port S-parameters for a series of CMOS spiral inductors have been measured to further generate such various Q factors for a many-sided evaluation of the inductor performance.