CMOS RFIC Research Articles

Parametric Conversion Using Custom MOS Varactors

The possible role of customized MOS varactors in amplification, mixing, and frequency control of future millimeter wave CMOS RFICs is outlined. First, the parametric conversion concept is revisited and discussed in terms of modern RF communications systems. Second, the modeling, design, and optimization of MOS varactors are reconsidered in the context of their central role in parametric circuits. Third, a balanced varactor structure is proposed for robust oscillator frequency control in the presence of large extrinsic noise expected in tightly integrated wireless communicators. Main points include the proposal of a subharmonic pumping scheme based on the MOS varactor, a nonequilibrium elastance-voltage model, optimal varactor layout suggestions, custom 0.13 µm-CMOS varactor design and measurement, device-level balanced varactor simulations, and parametric circuit evaluation based on measured device characteristics.

A 0.25-mm CMOS T/R switch for UWB wireless communications

A T/R switch, fabricated using standard 0.25-/spl mu/m CMOS process, for ultra wide-band (UWB) wireless communications is presented. The switch is designed based on the concept of synthetic transmission line, utilizing both CPW and CMOS transistors, to achieve not only an extremely wide bandwidth but also a linear phase response necessary for time-domain UWB applications. On-chip measurement is completed in both frequency and time domains. Frequency-domain measured results show insertion loss of 2.2-4.2 dB, isolation from 34-48 dB, and highly linear transmission phase from 0.45 MHz to 13 GHz. These results are quite consistent with the calculations. Particularly, the time-domain pulse measurement shows that the output pulses resemble closely the input pulses with very little reflection, demonstrating the switch's suitability for true time-domain UWB applications. The developed switch is ready to be integrated with other CMOS RFICs to form on-chip transceivers for various UWB applications.

Thyristor Input-Protection Device Suitable for CMOS RF IC?s

Based on simulation results and accompanying analysis, we suggest a thyristor-type ESD protection device structure suitable for implementation in standard CMOS processes to reduce the parasitic capacitances added to the input nodes, which is very important in CMOS RF IC's. We compare DC breakdown characteristics of the suggested device to those of a conventional NMOS protection device to show the benefits of using the suggested device for ESD protection. The characteristic improvements are demonstrated and the corresponding mechanisms are explained based on simulations. Structure dependencies are also examined to define the optimal structure. AC simulation results are introduced to estimate the magnitude of reduction in the added parasitic capacitance when using the suggested device for ESD protection. The analysis shows a possibility of reducing the added parasitic capacitance down to about 1/45 of that resulting with a conventional NMOS protection transistor, while maintaining robustness against ESD.

A simple systematic spiral inductor design with perfected Q improvement for CMOS RFIC application

In this paper, a systematic design procedure based on key factor analysis of the Q curve has been proposed. In addition to inductor design, we also present a technique that combines optimized shielding poly, and proton implantation treatment is utilized to improve the inductor Q value. The shielding effect of poly-silicon and the semi-insulating characteristics of proton-bombarded substrate have added a 37% and 54% increment to the Q value of the inductors, respectively. The combination of the two means has created a multiplication of their individual contribution rather than addition. The dramatic improvement of the Q value resulted from the doping level and film thickness optimization of a poly shield layer combined with a proton implantation treatment. A phenomenal Q-value increment as high as 122% of 4-nH spiral inductors can be realized. This technique shall become a critical measure to put inductors on a silicon substrate with satisfactory performance for Si-based RF integrated-circuit applications

Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs

We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite (and mediocre) Q-factors limited by material losses and constraints on expensive die area, low self-resonance frequencies and dual parasitics that are particularly prevalent in deep sub-micron CMOS processes (65 nm-0.18 μm. We use these integrated elements in an ideal synthesis of a Bluetooth/WLAN pass-band filter in single-ended or differential architectures, and show the significant deviations of the on-chip filter response from the ideal one. We identify which elements in the filter circuit need to maximize their Q-factors and which Q-factors do not affect the filter performance. This saves die area, and predicts the FET parameters (especially transconductances) and negative-resistance FET topologies that have to be integrated in the filter to restore its performance.