CMOS Multiplexer Research Articles

Reducing the heat in CMOS multiplexers

Reducing the heat in CMOS multiplexers

Multiplexed quantum transport using commercial off-the-shelf CMOS at sub-kelvin temperatures

Continuing advancements in quantum information processing have caused a paradigm shift from research mainly focused on testing the reality of quantum mechanics to engineering qubit devices with numbers required for practical quantum computation. One of the major challenges in scaling toward large-scale solid-state systems is the limited input/output (I/O) connectors present in cryostats operating at sub-kelvin temperatures required to execute quantum logic with high fidelity. This interconnect bottleneck is equally present in the device fabrication-measurement cycle, which requires high-throughput and cryogenic characterization to develop quantum processors. Here we multiplex quantum transport of two-dimensional electron gases at sub-kelvin temperatures. We use commercial off-the-shelf CMOS multiplexers to achieve an order of magnitude increase in the number of wires. Exploiting this technology, we accelerate the development of 300 mm epitaxial wafers manufactured in an industrial CMOS fab and report a remarkable electron mobility of (3.9 ± 0.6) × 105 cm2/Vs and percolation density of (6.9 ± 0.4) × 1010 cm−2, representing a key step toward large silicon qubit arrays. We envision that the demonstration will inspire the development of cryogenic electronics for quantum information, and because of the simplicity of assembly and versatility, we foresee widespread use of similar cryo-CMOS circuits for high-throughput quantum measurements and control of quantum engineered systems.

Investigation of CMOS Multiplexer Jet Matrix Addressing and Micro-Droplets within a Printhead Chip.

In this study, we demonstrate and investigate a new droplet injection design. We create a thermal inkjet (TIJ) printhead using an application-specific integrated circuit system and bulk micromachining technology (microelectromechanical systems). We design inkjet printhead chips with a new structure and investigate their properties. For the new structure, the integration of complementary metal-oxide-semiconductors (MOSs) and enhancement-mode devices, as well as power switches and a TIJ heater transducer, enables logic functions to be executed on-chip. This capability is used in the proposed design to address individual jets with even fewer input lines than in matrix addressing. A high number of jets (at least 896) can be addressed with only 11 input lines. E1 (Enable 1) and E2 (Enable 2) are set up dependently, and they have the ability to reverse their signals in relation to each other (i.e., if E1 is disabled, E2 is enabled and vice versa). The E1 and E2 signals each service 448 jets. If one of the MOSs is turned on, then it corresponds to a power line with a similar function. If an addressing gate terminal of the other MOS has a discharge action, then we can control a different heater to generate heating bubbles in the jet inks. The operating frequency for addressing these measurements is 18 kHz in normal mode, 26 kHz in draft mode, and 16 kHz in best mode.

Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure

Routing multiplexers based on pass-transistors or transmission gates are an essential components in many digital integrated circuits. However, whatever structure is employed, CMOS multiplexers have two major limitations: 1) their delay is linearly related to the input size; 2) their performance degrades seriously when operated in near-Vt regime. Resistive Random Access Memory (RRAM) technology brings opportunities of overcoming these limitations by exploiting the properties of RRAMs and associated programming structures. In this paper, we propose new one-level, two-level and tree-like multiplexers circuit designs using 4T(ransistors)1R(RAM) elements and we compare them to naive one-level multiplexers. We consider the main physical design aspects associated with 4T1R-based multiplexers, such as the layout implications using a 7 nm FinFET technology, and the co-integration of low-voltage nominal power supply and high-voltage programming supply. Electrical simulations show that using a 7 nm FinFET transistor technology, the proposed 4T1R-based multiplexers reduce delay by 2x and energy by 2.8x over naive 4T1R and 2T1R counterparts. At nominal working voltage, considering an input size ranging from 2 to 50, the proposed 4T1R-based multiplexers reduces Area-Delay and Power-Delay products by 2.6x and 3.8x respectively, as compared to best CMOS multiplexers. In the nearVt regime, the proposed 4T1R-based multiplexer demonstrates 2x larger delay efficiency over the best CMOS multiplexer. The proposed 4T1R-based multiplexers operating at near-Vt regime can still achieve up to 22% delay improvement when compared to best CMOS multiplexers working at nominal voltage.

English

English

Methodology and Design of a Massively Parallel Memristive Stateful IMPLY Logic-Based Reconfigurable Architecture

Continued dimensional scaling of CMOS processes is approaching fundamental limits and, therefore, alternate new devices and microarchitectures are explored to address the growing need of area scaling and performance gain. New nanotechnologies, such as memristors, emerge. Memristors can be used to perform stateful logic with nanowire crossbars, which allows for implementation of very large binary networks. This paper involves the design of a memristor-based massively parallel datapath for various applications, specifically single instruction multiple data and parallel pipelines. The innovation of our approach is that the datapath design is based on space-time diagrams that use stateful IMPLY gates built from binary memristors. The paper also develops a new model and methodology to design massively parallel memristor-CMOS hybrid datapath architectures at a system level. This methodology is based on an innovative concept of two interacting subsystems: 1) a controller composed of a memristive RAM, MsRAM, to act as a pulse generator, along with a finite-state machine realized in CMOS, a CMOS counter, CMOS multiplexers, and CMOS decoders; 2) massively parallel pipelined datapath realized with a new variant of a CMOL-like nanowire crossbar array, memristive stateful CMOL with binary stateful memristor-based IMPLY gates. In contrast to previous memristor-based FPGA, our proposed memristive stateful logic field programmable gate array uses memristors for both memory and combinational logic implementation. With a regular structure of square abutting blocks of memristive nanowire crossbars and their short connections, our architecture is highly reconfigurable. We present the design of a pipelined Euclidean distance processor along with its various applications. Euclidean distance calculation is widely used by many neural network and similar algorithms.

Analysis of CMOS Multiplexer Circuits of Different Area and Logic Style

Abstract: This paper is an approach to comprehend the VLSI design of multiplexers. A number of conventional designs of multiplexers along with several XOR based transmission gate and pass transistors based models are analyzed as a building block of diverse complex circuit system. Different sizes were approached starting from 4T to 22T. A comparative learning was made on total of eighteen (18) different 2:1 multiplexers to analyze the performance, area, power consumption and noise. PSPICE, DSCH, MICROWIND have been used for simulation. Finally different designs of multiplexers are specified for individual purpose to have better performance in diverse requirement.

Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers

In this brief, a design strategy to minimize the delay of high-fan-in CMOS multiplexers (MUXes) based on the heterogeneous-tree approach is proposed. A preliminary circuit analysis is carried out that takes interconnect parasitics into account, and analytical design criteria are then derived by assuming that the MUX switches are made up of pass transistors or transmission gates, as is often done in practical cases. The design criteria turn out to be very simple (even more than those in [1] which did not consider the effect of interconnects) and independent of the adopted technology. In addition, an approximate delay expression is given to predict the achievable speed performance before actually carrying out the optimized design. The results are validated through post-layout simulations on a 90-nm CMOS process.

A germanium photodetector array for the near infrared monolithically integrated with silicon CMOS readout electronics

Near infrared (NIR) detectors, operating in the 1.3– 1.6 μm region, are key elements in a number of applications ranging from optical communications to remote sensing. InGaAs and Ge are currently the materials of choice for the fabrication of NIR detectors due to their good absorption and transport properties. However, as the required performances increase (bit-rate in optical communications, number of pixels in imaging, etc.), it becomes more and more important to reduce the separation from detectors and driving/biasing and amplifying electronics, by integrating the two components on the same chip. We demonstrate an array of NIR detectors monolithically integrated with standard silicon CMOS readout electronics. The employed low temperature process allowed the integration of the detectors as the last step of chip fabrication. The integrated micro-system consists of a linear array of 120×120 μm 2 pixels, an analog CMOS multiplexer and a transimpedance amplifier. The chip exhibits a good photoresponse in the NIR, with responsivities as high as 43 V/ W at 1.3 μm , dark currents of 1 mA/ cm 2 and inter-pixel cross-talk better than −20 dB .

0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation

A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This logic is more tolerant to the threshold voltage fluctuation than the conventional MCML and is suitable for gigahertz operation of deep-submicron CMOS transistors. Using this logic, 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) ICs for optical-fiber-link systems have been fabricated with 0.18-/spl mu/m CMOS transistors. The ICs are faster than conventional CMOS MUX and DEMUX ICs and their power consumption is less than 1/4 of that of the conventional 10-Gb/s MUX and DEMUX ICs made using Si bipolar or GaAs transistors.

On the design of fast large fan-in CMOS multiplexers

The N-input multiplexers based on CMOS switches are conventionally designed with the binary-tree structure to simplify the address decoder and obtain a reasonable delay, which estimates the propagation time from data input end to the output end of the multiplexers. However, this design strategy in general takes too much hardware and incurs too much delay. To reduce both delay and cost, some structures other than the binary-tree structure have to be used. Therefore, in this paper we propose a general procedure based on the heterogeneous-tree structure for designing fast large fan-in CMOS multiplexers. The results show that not only can the speed be increased but the cost can also be reduced considerably for the proposed circuits with various input sizes. In addition, we show that both the binary-tree structure and the uniform structure are special cases of the proposed approach.

Total dose and proton testing of a commercial HgCdTe array

The radiation tolerance of a commercially available 256/spl times/4 HgCdTe array has been measured. The main effects were ionization-induced and produced changes in diode slope resistance and CMOS multiplexer characteristics particularly the onset of parasitic leakage currents after /spl sim/15 krad(Si). However these effects annealed with storage above 20/spl deg/C.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Attainment of high sensitivity at elevated operating temperatures with staring hybrid HgCdTe-on-sapphire focal plane arrays

Cost-effective high-performance IR imaging cameras need affordable staring focal plane arrays (FPAs) that can operate effectively at temperatures compatible with inexpensive long-life coolers. We report on staring hybrid 128 x 128 and 256 x 256 Hg_1-<i>x</i>Cd_<i>x</i>Te FPAs that have requisite yield, sensitivity, operability, and reliability at a medium-wavelength IR (MWIR) cutoff wavelength (λ_<i>c</i> ~4.6 μm at 180 K) and elevated operating temperatures. Mean 256 x 256 FPA noise-equivalent temperature differences (NEΔT) using broadband <i>f</i>/1.7 optics were 4.3, 7.7, and 55 mK at 120, 140, and 180 K, respectively. We extrapolate that camera NEΔT ≤ 0.02 K can be achieved at 190 K using optimized (λ_<i>c</i> of ~4.4 μm (180 K), a 3.4- to 4.2-μm bandpass filter, and <i>f</i>/1 optics. Because the CMOS multiplexers have a low-power dissipation and need little ancillary circuitry in the dewar, a viable thermoelectrically-cooled FPA technology is thus implied once the λ_<i>c</i> is optimized for MWIR imaging.

Extending HgCdTe Photovoltaic Detector Technology to Cutoff Wavelengths of 17 μm

AbstractWe are developing two-layer LPE P-on-n HgCdTe photovoltaic detector arrays with cutoff wavelengths out to 17 μm for a NASA spaceborne infrared radiometer. These bilinear multiplexed arrays will operate at 60 K, and must achieve sensitivities approaching the background limit for a background photon flux of 2×1015 photons/cm2-sec. The detectors must operate at reverse bias voltage to interface with silicon CMOS multiplexer circuits, and must exhibit low 1/f noise.This paper reviews progress toward these demanding requirements. The limiting junction current mechanisms for HgCdTe photodiodes at these very long cutoff wavelengths are reviewed. Data are presented for both CdTe-passivated and ZnS-passivated arrays at 60 K with cutoff wavelengths of 15.4−16.9 μm. Average R0A products of 13 ohm-cm2 and quantum efficiencies of 89% have been achieved for cutoff wavelengths of 15.4 μm at 60 K. These array data demonstrate the potential for VLWIR PV HgCdTe to meet the requirements for advanced NASA applications.

Long wavelength infrared 128*128 Al/sub x/Ga/sub 1-x/As/GaAs quantum well infrared camera and imaging system

The authors discuss the development of a long-wavelength (8-14- mu m) 128*128 Al/sub x/Ga/sub 1-x/As/GaAs multiquantum well infrared (MQW IR) imaging system. Highly uniform, high-yield GaAs focal plane arrays, incorporating an integral grating structure for efficient optical coupling, were hybridized to CMOS multiplexers. Excellent imagery, with low noise, a noise equivalent differential temperature (NE Delta T) of less than 10 mK, and a high image contrast signal-to-noise ratio, has been achieved. It is shown that figures of merit concerning array uniformity, such as yield, NE Delta T, and maximum deliverable charge to the CMOS multiplexer are much more relevant variables that affect image quality than D*.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Temperature effects on CMOS multiplexers used for data acquisition

Experiments were performed to evaluate the effects of temperature on a single type of CMOS multiplexer which is currently used for data acquisition in agricultural research. The results indicate that the internal resistance of each channel within the multiplexer increases linearly with increasing temperature. However, the rate of increase was significantly different for one or more channels of an eight-channel multiplexer. Also, the mean resistances between channels were significantly different over the range of temperatures expected in field data acquisition systems in the Southeast Region. These results illustrate the need for specific characteristic data on the particular multiplexers used in a circuit. For most sensor-interface systems the error induced by the multiplexer may not be significant if the total range in expected resistance is very large, but for precision sensors this characteristic must be accounted for.