CMOS-grade Silicon Substrates Research Articles

Three-solenoid windings transformer baluns on CMOS-grade silicon substrate

Several novel on-chip three-solenoid windings transformer baluns were designed and fabricated using post-CMOS compatible concave-suspending micromachining process, which are applicable in the design of radio-frequency integrated circuits (RFICs). A generalized lumped-element circuit model (LECM) is developed to accurately characterize input and output characteristics of these three-port signal conversion devices, with the partial element equivalent circuit (PEEC) method implemented for capturing skin and proximity effects in them. Satisfactory agreements are obtained among the measured, simulated, and modeled S-parameters of the fabricated baluns over the frequency range of 500MHz-10GHz. Measurements show that these baluns exhibit less than 1dB amplitude imbalance and less than 1^o phase imbalance up to 6GHz. Their power transfer and impedance matching are also examined in details.

Modeling of Multilayer Suspended Microstrip Line and its Discontinuities on CMOS Grade Silicon Substrate for Millimeter Wave Integrated Circuit Applications

Transmission line parameters such as characteristic impedance Z0, effective dielectric constant eeff, attenuation constant α of suspended microstrip line on multilayer low resistively silicon substrate are investigated using full wave FEM simulator HFSS. Effect of variation in the thickness of Si3N4, polyimide and metal layers on attenuation are studied. Due to suspended nature, significant reduction in transmission loss is observed in the simulation at 60 GHz frequency. Discontinuities such as open end, gap and step in width of strip conductor are analyzed to extract their lumped equivalent circuits which can be used in the design of integrated circuits.

High Performance Inductors on CMOS-Grade Trenched Silicon Substrate

This paper reports on a new implementation of high-quality factor copper inductors on CMOS-grade silicon substrates (p = 10-20 Omega ldr cm) using a CMOS-compatible process. A low-temperature fabrication sequence (<300degC) is used to reduce the loss in silicon at RF frequencies by trenching the silicon substrate. The high aspect-ratio (30:1) trenches are subsequently bridged over or refilled with a low-loss dielectric to close the open areas and create a rigid low-loss island, referred to as Trenched Si Island. This method does not require air suspension of the inductors, resulting in mechanically-robust structures that are compatible with any packaging technology. A one-turn 0.8 nH inductor fabricated on a Trenched Silicon Island exhibits a very high peak quality factor of 71 at 8.75 GHz with a self-resonant frequency larger than 15 GHz.

30 GHz self-assembled highly-efficient on-chip monopole antennas

A novel monopole antenna made from an out-of-plane stressed cantilever beam is presented. The radiating element is isolated from a low-resistivity silicon substrate with a ground plane and thus high radiation efficiency of more than ∼50% can be achieved even with a CMOS-grade silicon substrate. The proposed antennas can be readily fabricated by a conventional IC fabrication process, which enables a high level of integration and low cost. Our experimental results of the monopole operating at 30 GHz agree well with our theoretical predictions.

Coplanar waveguide transmission lines and highQ inductors on CMOS grade silicon using photoresist and polyimide

Gold coplanar waveguide (CPW) transmission lines with losses of <0.5 dB/mm at 60 GHz have been produced on CMOS grade silicon substrates using a 15 /spl mu/m thick layer of either photoresist or polyimide. This process, together with an electroplated interconnect technique, has been used to produce spiral inductors on a 2 /spl Omega//cm n-Si substrate with a Q of 15 and L of 1.2 nH at 6 GHz.

Measured attenuation of coplanar waveguide on CMOSgrade silicon substrates with polyimide interface layer

The measured propagation constant of a coplanar waveguide on CMOS grade silicon with a polyimide interface layer is presented. It is shown that the transmission line can have an attenuation comparable to other transmission lines on Si substrates if the proper polyimide thickness is used.