High Performance Inductors on CMOS-Grade Trenched Silicon Substrate

Abstract

This paper reports on a new implementation of high-quality factor copper inductors on CMOS-grade silicon substrates (p = 10-20 Omega ldr cm) using a CMOS-compatible process. A low-temperature fabrication sequence (<300degC) is used to reduce the loss in silicon at RF frequencies by trenching the silicon substrate. The high aspect-ratio (30:1) trenches are subsequently bridged over or refilled with a low-loss dielectric to close the open areas and create a rigid low-loss island, referred to as Trenched Si Island. This method does not require air suspension of the inductors, resulting in mechanically-robust structures that are compatible with any packaging technology. A one-turn 0.8 nH inductor fabricated on a Trenched Silicon Island exhibits a very high peak quality factor of 71 at 8.75 GHz with a self-resonant frequency larger than 15 GHz.