A High-Q Inductor based on Fan-Out Panel Level Package Technology

Abstract

In this paper., a planar spiral inductor is presented based on the fan-out panel-level packaging (FOPLP) technology. The inductor is constructed by two redistribution layers (RDL) of the FOPLP process. The size of the designed planar spiral inductor is 250um x 250um. Compared to the on-chip inductors with the same size., the proposed inductor using fan-out panel-level packaging technology has much higher quality factor and nearly same inductance. Due to the thicker metal used for the proposed inductor., the self-resonating frequency (SRF) is slightly lower than that of the on-chip counterpart. The maximum value of the inductor quality factor designed using fan-out panel-level packaging technology is 16.61., while the on-chip inductor achieve 13.27 Q-factor., and both of the two inductors present 1.3nH inductance. Obviously., if the on-chip inductor is replaced by the FOPLP inductor., not only higher Q-factor and larger inductance can be obtained., but also a large chip size can be saved.