CMOS Full Adder Research Articles

Low Power CMOS Full Adder Cells based on Alternative Logic for High-Speed Arithmetic Applications

Low Power CMOS Full Adder Cells based on Alternative Logic for High-Speed Arithmetic Applications

Efficient design approaches to CMOS full adder circuits

In the field of high-performance chip designs, many applications have the ability to tolerate small errors through the use of approximate full adders. By appropriately reducing the corresponding precision, the performance of hardware implementation can be greatly improved. The adders are commonly applied in digital signal processors (DSP), communication systems, image processing, etc., to quickly complete addition estimation operations. This paper proposes the designs of 8 approximate adders and compares their performance with existing circuit structures. Simulation results demonstrate that the approximate adders proposed in the first group (i.e., LCAFA1∼LCAFA3) achieve an average area reduction of 21.44 % and an average delay reduction of 42.85 %. In the second group, the proposed approximate adders LCAFA4∼LCAFA8 achieve an average power reduction of 28.35 %, an average area reduction of 17.39 %, an average delay reduction of 84.25 %, and an average decrease in the power-area-delay product (PADP) of 68.26 %.

Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model

The multiplier is the fundamental component of many computing modules. As the most important component of a multiplier, the full adder (FA) also has a significant impact on the overall performance. Full adders based on pass transistor logic (PTL) have been a very popular research field in recent years, but the uneven delay makes it difficult to analyze the critical path of multipliers based on PTL full adders. In this paper, we propose a model to evaluate the critical path of the carry save array (CSA) multiplier that could reduce the size of the simulation input set from 4 G to 93 K to finally obtain the maximum delay of the multiplier. We propose a novel low-power, high-speed CSA multiplier based on both PTL full adders and CMOS full adders, using our critical-path evaluation model. The proposed work is implemented in the 28 nm process. We use the model to reduce the worst-case delay by 14.5%. The proposed multiplier improved the power delay product by 9.4% over the conventional full CMOS multiplier.

CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications

In modern Digital System design, adders are widely used in many applications including Microprocessors, Digital Signal Processors, Arithmetic Logic Units and digital signal processing. Power efficiency is an important key factor for any integrated circuits. By considering the importance of Full Adder (FA) cells, their power consumption may play significant role in overall power consumption. So designing a low-power full adder is important to achieve the high-performance computing. Swing restored technique is commonly used method to reduce the signal swing at the internal nodes and it helps to reduce the power consumption and improves the circuit's speed. This paper presents a novel hybrid full adder cell design using the modified swing restored technique and complementary pass transistor logic. The Full Adder circuit was implemented using Cadence Virtuoso tool on gptk 180nm CMOS process technology. The proposed full adder was compared with earlier reported circuits based on Delay, Power and PDP. The comparison shows that proposed circuit consumes less power with high performance. Also various process corners and noise immunity were analyzed to find the sensitivity of the circuit. Further an 8-bit Ripple Carry Adder was designed using the proposed full adder to verify the functionality in higher order bits. Simulations were performed and analysed using the Cadence Spectre.

Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier

With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and multiplier circuits due to the low count of transistors and low-power characteristics. In this paper, we present a novel full adder based on pass transistors. The proposed full adder consists of 18 transistors. The post-layout simulation shows a 13.78% of power reduction compared to conventional CMOS full adders. Moreover, we propose an 8-bit signed multiplier based on the proposed full adder. The post-layout simulation shows an 8% power reduction compared to the multiplier produced by the Design Compiler synthesis tool. Compared to the existing work with a similar process, our work achieved only 19.02% of the power-delay product and 3.5% of the area-power product.

FULL ADDER CIRCUIT DESIGN WITH LOW POWER AND HIGH SPEED AT 0.25µM CMOS TECHNOLOGY USING TANNER EDA

A CMOS Full Adder is designed using Tanner EDA Tool based on 0.25µm CMOS Technology. In the arithmetic logic unit (ALU), the full adder cell is one of the most frequently utilized digital circuit components and the fundamental functional unit of all computational circuits. Right now, a lot of work has been done to improve the architecture and functionality of full adder circuit designs. In this research, two innovative 1-bit full adder cell designs are developed using ten transistors and 0.25mm CMOS technology (10-T). Tanner software tools will be used in the design of the CMOS full adder to simulate the schematic and layout as well as compare the schematic and layout for the purpose of determining precise design limitations. As part of this, we are going to perform the simulation of the CMOS full adder using T-SPICE of Tanner EDA and its layout design using the Microwind tool. The parameters such as power consumption, Area, Propagation Delay, and Power Delay Product (PDP) are evaluated to analyze the proposed one-bit full adder

Performance Comparison of CMOS and NMOS GNRFET Full Adder

Transistor makes up the cornerstone of modern computing. In this work, a SPICE model of GNRFET was used to simulate the performance of a NMOS and CMOS binary full adder. The performance of this adder was evaluated in terms of its average power consumption and propagation delay. Three variables, namely the resistance value, dimer lines and channel length were manipulated and the impact on its performance was assessed. It was observed that a linear improvement in propagation delay was accompanied by an exponential increase in power consumption and only a small range of values of resistance was able to deliver a relatively reasonable trade-off between power consumption and propagation delay. These values range from approximately 110 kΩ to 130 kΩ. When the dimer lines were varied from 12 to 8 and channel length was varied from 32 nm to 16 nm, the results showed that a channel length of 16 nm was superior to that of a channel length of 32 nm as it showed 25.25 % of improvement in propagation delay at approximately similar power consumption. On the other hand, the choice of dimer lines and circuit architecture was required to be evaluated on a case-by-case basis. For a compute-intensive application with a controlled environment, NMOS logic with 8 dimer lines should be chosen, while for less compute-intensive applications and portable devices, CMOS logic with 12 dimer lines should be utilised. A NMOS logic was chosen for the former due to a reasonable trade-off of 30.94 % of power consumption for a 35.03 % of propagation delay was established When the performance of these full adders are compared to that of a MTGB based ternary gate in terms of their performance, it was found that the CMOS and NMOS logic full adder performed better than a MTGB based ternary full adder.

Simulation and Analysis of different CMOS Full Adders for Delay Optimisation

Abstract: Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.

Design and evaluation of hybrid SHE+STT-MTJ/CMOS full adder based on LIM architecture

This work aimed at developing a full adder using hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) based on the logic-in-memory architecture (LIM). LIM has emerged as the most promising alternative to the standard von-Neumann architecture in the impeding post-CMOS era. Performance of the hybrid full adder is evaluated in terms of power, delay, power delay product (PDP), and device count. These results are compared with the existing double pass transistor logic-based clocked CMOS (DPTL-C2MOS) full adder. Further, Monte-Carlo simulations on both variants of full adders were conducted to study their performance. Simulation results reveal that the hybrid full adder is superior to the DPTL-C2MOS full adder and can be used in low power and high throughput computing systems in the near future.

Realization of Strong CMOS Conforming Full Adder Circuit Using Symmetric Function Lattice Structure

Due to the physical limit that the IC industry may face in the future that transistors size may not be able to shrink anymore,a lot of work had been done to minimize the number of transistors used, instead of shrinking them. One of the highly researched standard circuit to reduce transistor count is the full adder as it appears in almost all computing circuits. In this paper, an alternative to CMOS technology using symmetric Boolean function lattice structure is presented to produce full adder. Symmetric functions are the functions that are invariant under input permutation. Theyhaveaspecialwayofrealizationthat offerssomepossibility to reducethe number oftransistors used. Full adder falls into this classof functions. It has been found that the right full adder lattice structure based circuit only requires 22 transistors to produce the correct function for the sum and c out output. This is a saving of 6 transistors as compared to the standard 28-transistor CMOS full adder. The output delay is around 3.0 ns for the c out output, and around 4.5 ns for the sum output.

Comparison between CMOS full adder and PTL full adder

In electronic industry the level of integration is an important aspect as makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, area occupied and delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Designing of full adder using conventional CMOS design and PTL has been shown in this paper. A comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Mentor Graphics Tool is used in design and simulation of the full adder. The PTL full adder has a smaller number of transistors and lower power dissipation compared to CMOS full adder. With all the comparison made it will be concluded that the PTL full adder performance is better than the CMOS full adder.

Low Power NAND Gate–based Half and Full Adder / Subtractor Using CMOS Technique

In recent years, low power consumption has been an important consideration for the design of system since there is a high demand for consumer electronics such as cellphones for a longer battery life. This paper presents the simulation of half adder, half subtractor, full adder, and the full subtractor. The presented circuit contains NAND gates combining the NMOS and PMOS. These CMOS circuitries has the advantage of lower voltage, lower power consumption, and higher energy efficiency. The NMOS and PMOS were bridge together to produce the desired output. This design provides the CMOS half adder, half subtractor, full adder, and full subtractor using the Tanner EDA software tool. The complete CMOS circuit schematic are described in this paper. The design methods and principles are described thereafter. Simulations have been done with the use of the Tanner EDA tool in a CMOS technology standard and response output was verified comparing the obtained waveform along with its truth table. In comparison with conventional logic truth table, T-Spice output simulation matches with theoretical expectations.

Low power CMOS full adder design with body biasing approach

In this paper, five different low power full adders using XOR/XNOR gates and multiplexer blocks with body biasing have been presented. In the first methodology, the adder depicts minimum power dissipation of 204.09μW and delay of 5.9849 ns. In the second, an improvement in power consumption has been reported at 128.92μW with delay of 5.9875 ns by using voltage biasing of two PMOS (P1 &P2) along with substrate biasing. In the third methodology, adder gives minimum power dissipation of 0.223nW with a delay of 5.2352 ns. Further, in fourth, it shows minimum power consumption of 0.199nW with a delay of 5.1002 ns and finally in fifth methodology, minimum power reduces to 0.192nW.Moreover, power delay product (PDP) results also have been compared for these methodologies. Comparisons have been made with earlier reported circuits and proposed circuits show better performance in terms of power consumption and delay.

Performance of Different Full Adder Structures for Optimized Design

Design of high performance and energy efficient digital systems are one of the most important research areas in VLSI system design which is suitable for real-time applications. One of the functional elements used in complex arithmetic circuits is an adder. To design an energy efficient adder one-bit full adder cell is designed based on adiabatic logic. The proposed ALFA cell is designed using adiabatic logic which results with the negligible amount of exchange of energy with the surrounding environment. Therefore, the application circuits based on this logic will have negligible energy loss due to heat dissipation. It requires 24 transistors to get the true and complimentary arithmetic sum and carry output. The proposed adiabatic logic based full adder (ALFA) cell processes the three single bit inputs and provides the output as sum, carry, sum bar and carry bar in a single architecture. The proposed ALFA cell reduces the power consumption by 98.49%, 90.93%, and 89.37%, respectively, when compared to CMOS full adder, 14T pass-transistor logic (PTL) with transmission gate (TG) full adder and 16T PTL with TG full adder.

Transmission Gate and Hybrid Cmos Full Adder Characterization and Power-Delay Product Estimation Based on Mathematical Model

Abstract The demand for low power CMOS VLSI circuit design is increasing due to the ever-increasing demand for portable devices. A Full Adder (FA) is the basic building block of many VLSI subsystems, and it affects the performance of VLSI subsystems. The Transmission Gate (TG) and hybrid CMOS FA designs can achieve low Power Delay Product (PDP) compared to other FA designs, hence these FA designs are suitable for portable devices. A large number of repetitive simulations are required for thorough characterization of the FA design. A method to develop the mathematical model (based on 2nd degree polynomial equation) of the FA is proposed here, which satisfactorily estimates the Power Delay Product (PDP) of TG and hybrid CMOS FAs for non-simulated parameter combinations within given parameter range. Main aim of proposed method is to reduce characterization effort by estimating PDP using mathematical model, rather than estimating it through simulation. Also, mathematical model can be used to estimate the transistor widths to achieve low PDP for particular operating condition. Further, the effect of individual polynomial term, number of parameters, and number of points per parameter, on the accuracy of mathematical model is also studied.

Implementation of Low Power and Area Efficient Vedic Multiplier

Designing a low power consuming and area efficient Vedic Multiplier using Hybrid Full Adder. In this paper, Conventional CMOS (CCMOS) Full Adders involved in a conventional Vedic multiplier is replaced with Hybrid Full adders to achieve reduction in power consumption and area. In the proposed system ripple carry adders involved in Vedic multiplier are designed using Hybrid Full Adder. The design is done for 2-bit and it is extrapolated to 16-bit. Performance parameters such as power consumed and area between Vedic multiplier involving CCMOS and Hybrid Full Adder is done and a comparative study over them is made. Significant improvement is achieved in this implementation and the layout design is also implemented for the 2-bit, 4-bit, 8-bit and 16-bit Vedic multiplier for both Conventional CMOS and Hybrid Full-Adder logic styles. The implementation is carried out using Tanner EDA tool under 250-nm technology.

Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor

The full adder is a key component for many digital circuits like microprocessors or digital signal processors. Its main utilization is to perform logical and arithmetic operations. This has empowered the designers to continuously optimize this circuit and ameliorate its characteristics like robustness, compactness, efficiency, and scalability. Carbon Nanotube Field Effect Transistor (CNFET) stands out as a substitute for CMOS technology for designing circuits in the present-day technology. The objective of this paper is to present an optimized 1-bit full adder design based on CNTFET transistors inspired by new CMOS full adder design [1] with enhanced performance parameters. For a power supply of 0.9V, the count of transistors is decreased to 10 and the power is almost split in two compared to the best existing CNTFET based adder. This design offers significant improvement when compared to existing designs such as C-CMOS, TFA, TGA, HPSC, 18T-FA adder, etc. Comparative data analysis shows that there is 37%, 50%, and 49% amelioration in terms of area, delay, and power delay product respectively compared to both CNTFET and CMOS based adders in existing designs. The circuit was designed in 32nm technology and simulated with HSPICE tools.

Energy and Error Analysis Framework for Approximate Computing in Mobile Applications

In this brief, we propose a framework that enables us to analyze energy and error for mobile applications when run on systems with approximate circuits. Approximate circuits have conventionally been used in image/video processing applications, which are mostly limited to 8-bits. To the best of our knowledge this is the first work where approximate circuits have been evaluated on a 32-bit processor running real mobile applications. We observe that in approximate adders where Carry is approximated, with 2-bit approximation in LSB, the absolute average error in image processing applications is ~ 3. However, in mobile applications approximation in Carry can lead to an overflow. Hence, approximate adders with Carry approximation are not suitable for mobile computing. We also show the role of data-dependent switching in energy consumption and highlight which input pattern should not be approximated to obtain lesser error. In this brief, we also propose design of three energy-efficient approximate hybrid CMOS full-adders with varying levels of inaccuracies. The adder designs are implemented in UMC 65-nm technology using Cadence Virtuoso. Compared to existing approximate adders, on an average, the proposed adders consume 44% lesser energy and have ${2\times }$ lesser energy delay product. Our proposed adder designs have similar leakage power as compared to the existing adders.

Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures

A Full Adder (FA) is the basic building block of many VLSI sub-systems, and generally it falls into the critical path of the system. Several Transmission Gate (TG) and hybrid CMOS FA designs have been proposed in literature to achieve low Power Delay Product (PDP). But, their performance degrades when used in chain and tree structures, mainly due to poor driving capability. This paper introduces new design approach, a triplet design, to improve performance of TG and hybrid CMOS FA designs in chain and tree structures without inserting buffers. Two new hybrid CMOS FA designs, which are suitable for triplet design approach are also proposed in this paper. Six different FA designs (TG and hybrid CMOS FAs) are chosen to build 4, 8 and 16 bit Ripple Carry Adders (RCA) and multipliers, and we also studied the improvement in PDP using triplet design approach. Schematics and layouts of RCA and multiplier are designed in Cadence Virtuoso using gpdk045 library, and compared based on PDP.

VLSI implementation of ultra power optimized adiabatic logic based full adder cell

Design of high performance and energy efficient digital systems are one of the most important research areas in VLSI system design which is suitable for real-time applications. One of the functional elements used in complex arithmetic circuits is an adder. To design an energy efficient adder one-bit full adder cell is designed based on adiabatic logic. The proposed ALFA cell is designed using adiabatic logic which results with the negligible amount of exchange of energy with the surrounding environment. Therefore, the application circuits based on this logic will have negligible energy loss due to heat dissipation. It requires 24 transistors to get the true and complimentary arithmetic sum and carry output. The proposed adiabatic logic based full adder (ALFA) cell processes the three single bit inputs and provides the output as sum, carry, sum bar and carry bar in a single architecture. The proposed ALFA cell reduces the power consumption by 98.49%, 90.93%,and 89.37%, respectively, when compared to CMOS full adder, 14T pass-transistor logic (PTL) with transmission gate (TG) full adder and 16T PTL with TG full adder.