CMOS Four-quadrant Analog Multiplier Research Articles

Wide bandwidth CMOS four-quadrant mixed mode analogue multiplier using a second generation current conveyor circuit

This paper presents a new realization for a CMOS four-quadrant analogue multiplier. The proposed circuit is composed of three second generation current conveyor circuits (CCII), two NMOS transistors operating in the linear region, and four passive resistances. It can be operated in current mode and voltage mode without changing the circuit topology. The simulations results of the proposed mixed mode multiplier are verified by TSPICE simulator based on the BSIM3v3 transistor model for TSMC 0.18 $\mu $m CMOS process available from MOSIS at 25 $^{\circ}$C with $\pm $0.8 V supply voltage. Through the use of resistive compensation with different passive resistance values, the voltage mode responses present $\pm $0.25 V dynamic range with THD less than 0.114% and wide bandwidth extended from 3.42 GHz to 4.1 GHz. The current mode responses show $\pm $150 $\mu $A dynamic range with a maximum THD value about 0.083% and large bandwidth expanded from 2.67 GHz to 3.12 GHz.

Design of a high-linear, high-precision analog multiplier, free from body effect

In this paper, a new CMOS four-quadrant analog multiplier circuit is proposed, based on a pair of dual- translinear loops. The signicant features of the circuit are its high accuracy and high linearity as well as its body effect-free operation, owing to the fact that the circuit relies on a new dual-translinear topology. In addition, harmonic distortions are precisely discussed due to their conceivable mismatches, including transconductance and threshold voltage of the transistors. HSPICE postlayout simulation results are presented to verify the validity of the theoretical analysis, where under a supply voltage of 2.8 V, the bandwidth of the proposed multiplier is 137 MHz, and the corresponding maximum linearity error remains as low as 1.12%. Moreover, the power dissipation of the proposed circuit is found to be 521 W. The presented multiplier is expected to be useful in the design of various analog signal processing applications such as modulators and frequency doublers, as illustrated in this paper.

A Four-Quadrant Analog Multiplier Based on CMOS Source Coupled Pair

A novel structure for CMOS four-quadrant analog multiplier is presented. The multiplier is based on the square law of MOSFET. To enlarge the input impedance and improve the linearity, CMOS source coupled pair was employed. Also active attenuator was used to enhance the input range. Compared with the traditional multipliers based on Gilbert cell, the proposed circuit features high linearity, high input range. Circuit simulation using HSPICE with 0.5μm CMOS technology shows that under ±2.5V supply the proposed multiplier provides linear range of more than 50% of the voltage supply, THD is 0.3% at 100kHz and 0.8% at 1MHz, -3dB bandwidth is 2.5MHz, and the power consumption is 5mW.

Design of a CMOS low-power and low-voltage four-quadrant analog multiplier

A New CMOS four-quadrant analog multiplier is presented in this paper. The proposed multiplier is suitable for low supply-voltage operation and its power consumption is also very low. The proposed circuit has been simulated with the HSPICE and simulation results are given to confirm the feasibility of the proposed analog multiplier. According to the simulation results, under the supply voltage of 1.5 V, the input range of the proposed multiplier can be 120 mV and the corresponding maximum linearity error is less than 3.2%. Moreover, the power dissipation of the proposed circuit is only 6.7 μW. The proposed circuit is expected to be useful in analog signal processing applications.

LV/LP CMOS Four-Quadrant Analog Multiplier Cell in Modified Bridged-Triode Scheme

A new LV/LP CMOS four-quadrant analog multiplier designed in a modified bridged-triode scheme (MBTS) is presented. Its bi-directional bridged structure brings several benefits in terms of good line...

A Symmetric Complementary Structure for RF CMOS Analog Squarer and Four-Quadrant Analog Multiplier

A symmetric complementary structure for CMOS analog squarer and four-quadrant multiplier is proposed and analyzed. Analog squarer and a four-quadrant analog multiplier by utilizing the square-algebraic identity in the MOS triode region are presented. The squarer has a symmetric complementary configuration of the push-pull source follower and provides high performance in terms of linearity, power consumption, frequency response and total harmonic distortion (THD). The squarer, with −3 dB bandwidth of 1.3 GHz, had a nonlinearity error less than 1% over input signal range of ±1 V. The multiplier is basically constructed by voltage subtractors (for differential function of inputs) and sum-squaring as well as difference-squaring core circuits (for multiplication of two differential inputs signals). The multiplier has a nonlinearity error less than 1% over ±0.5 V input range. The circuit provides a −3 dB bandwidth higher than 1.3 GHz and exhibits a THD lower than 1% with a 1 V peak-to-peak input voltage, which dissipating 2.6 mW. The second-order effects including mismatch effects are discussed. The proposed circuits will be useful in various RF analog signal-processing applications.

A parallel structure for CMOS four-quadrant analog multipliers and its application to a 2-GHz RF downconversion mixer

A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8 /spl mu/m N-well double-poly-double-metal CMOS technology. Experimental results have shown that, under a single 1.2 V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500 mV/sub p-p/ at both multiplier inputs. The -3 dB bandwidth is 2.2 MHz and the DC current is 2.3 mA. By using the proposed multiplier as a mixer-core and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5 /spl mu/m single-poly-double-metal N-well CMOS technology. The experimental results have shown that, under 3 V supply voltage and 2 dBm LO power, the mixer has -1 dB conversion gain, 2.2 GHz input bandwidth, 180 MHz output bandwidth, and 22 dB noise figure. Under the LO frequency 1.9 GHz and the total DC current 21 mA, the third-order input intercept point is +7.5 dBm and the input 1 dB compression point is -9 dBm.

Design and analysis of a ±1 V CMOS four-quadrant analogue multiplier

The design and analysis of a ±1 V CMOS four-quadrant analogue multiplier and a frequency doubler for low-voltage low-power applications are presented. The design is based on the current-mode approach and the square-law characteristics of an MOS transistor in saturation. The multiplier utilises I–V converters, a current mirror and four matched transistors to achieve a transresistance gain of 73 dBΩ, a –3 dB bandwidth of 4.3 MHz, a total harmonic distortion below 1% and a maximum power dissipation of 130 µW. Design guidelines have been set to link the circuit performance, in terms of the gain, the input operating range, the fabrication area, and the device aspect ratios, to key device and technology parameters. The scope for further performance improvement using BiCMOS is also highlighted. The experimental results obtained from the chip were found to be in close agreement with the simulated results.

Four-quadrant analogue CMOS multiplier cell for VLSI signal and information processing

A CMOS four-quadrant analogue multiplier cell for VLSI signal and information processing based on a transconductor and associated circuitry to cancel nonidealities is presented. It is designed to operate in the triode region. This multiplier is modular, has a large dynamic input range, high linearity, low power dissipation and can provide either a differential output current or voltage. The design was fabricated using a 1.2 µm CMOS process. Simulation and experimental results are presented and discussed.

Low-voltage CMOS four-quadrant analogue multiplier for RF applications

A CMOS four-quadrant multiplier consisting of four MOS transistors operating in the saturation region is introduced. The circuit exploits the quadratic relation between the current and voltage of the MOS transistor in saturation. Simulation results show that, for a supply voltage of 1.2 V multiplication can be performed at a frequency of 1.8 GHz, achieving better performances than a recently proposed similar architecture.

A CMOS four-quadrant analog multiplier with single-ended voltage output and improved temperature performance

An all-MOS, four-quadrant analog multiplier with single-ended voltage output and good temperature performance is presented. It is based on a linear MOS transconductor with extended operation range to four quadrants and on a linear MOS resistor. The temperature behavior of the multiplier is improved by a factor of 10. The multiplier was realized using a 3- mu m p-well self-aligned contact CMOS (SACMOS) process. A linearity better than 1% for each of the input voltages of 5 V/sub p-p/, a bandwidth from DC to 1.2 MHz, and output noise 73 dB below full scale were achieved. The active chip area is 210 mil/sup 2/ and power consumption is 6 mW. A new approach for implementing a temperature-independent analog multiplier is proposed. >

Comments on `Wide dynamic range four-quadrant CMOS analog multiplier using linearized transconductance stages' [and reply

For the original article see ibid., vol.SC-21, no.6, p.1120-2 (1986). Recently, S.L. Wong et al, have described a CMOS four-quadrant analog multiplier based on linearized transconductance stages. The commentator points out that the `linearizing' of the Y-input port is unnecessary and does not offer any advantage over using a simple differential pair for the Y-input. The right approach for improving the Y-input dynamic range would be to try to increase the input signal range of the simple differential pair without altering the nature of its transfer characteristics. The original authors disagree, stating that the commenter's point would be valid if the input voltage (V/SUB Y/) range was only restricted by one of the input transistors entering cutoff, but that this is not so. They claim that since the multiplier requires wide X- and Y-input ranges, the use of the linearized Y-cell is necessary.