Four-quadrant analogue CMOS multiplier cell for VLSI signal and information processing

Abstract

A CMOS four-quadrant analogue multiplier cell for VLSI signal and information processing based on a transconductor and associated circuitry to cancel nonidealities is presented. It is designed to operate in the triode region. This multiplier is modular, has a large dynamic input range, high linearity, low power dissipation and can provide either a differential output current or voltage. The design was fabricated using a 1.2 µm CMOS process. Simulation and experimental results are presented and discussed.