CMOS-compatible Lateral Bipolar Transistors Research Articles

An analytical model of the VBE-dependence of current-splitting in CMOS-compatible lateral bipolar transistors

An analytical model of the VBE-dependence of current-splitting in CMOS-compatible lateral bipolar transistors

A very low-noise CMOS preamplifier for capacitive sensors

A CMOS preamplifier optimized for piezoelectric transducers is presented. The extensive use of CMOS-compatible lateral bipolar transistors (CLBTs) and careful layout leads to a very low noise along with good untrimmed DC and AC characteristics. These features make it competitive with bipolar and JFET realizations. In addition, long coaxial lines can be driven without significant alteration of performance using the two uncommitted on-chip buffers. This circuit was fabricated in a standard 3- mu m p-well CMOS technology, opening perspectives to monolithic integration of data acquisition subsystems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

CMOS-compatible lateral bipolar transistor for BiCMOS technology. I. Modeling

A CMOS-compatible lateral bipolar transistor having neither an epitaxial layer nor n/sup +/-buried layers is proposed. The simulation indicates that the BiCMOS gate delay time shows a weak dependence on the metallurgical base width W/sub B/, (and hence on f/sub Tmax/, since f/sub T/ varies as 1/W/sub B//sup 2/) and strong dependence on the effective base width W/sub B(eff)/, where W/sub B(eff)/ nearly equals the distance between the emitter and the n/sup +/ collector, d/sub E-C/. This is because bipolar transistors in BiCMOS circuits are operated in high-level injection during the switching transient. Therefore, it is possible to build a high-speed BiCMOS gate using lateral bipolar devices with short d/sub E-C/. The transistor has a structure similar to that of an n-channel MOSFET. The emitter and collector are formed simultaneously and self-aligned to a polysilicon base electron like the source and drain in a MOSFET. >

CMOS-compatible lateral bipolar transistor for BiCMOS technology. II. Experimental results

For Pt.I see ibid., vol.39, no.4, p.948-51 (1992). Characteristics of a CMOS-compatible lateral bipolar transistor suitable for low-cost and high-speed BiCMOS LSIs are described. The proposed transistor has a structure analogous to that of the NMOS transistor, which employs a source and drain self-aligned structure to form an emitter and collector. The obtained values of h/sub FE/, BV/sub CEO/, R/sub CS/, f/sub Tmax/, and r/sub bb'/, are 20, 7 V, 50 Omega , 6.3 GHz, and 450 Omega , respectively. Moreover, delay times of a two-input NAND BiCMOS gate circuit are 0.28 ns when unloaded, and 0.42 and 0.53 ns when load capacitances are 1 and 2 pF, respectively. These values are comparable to those for BiCMOS circuits using the conventional vertical bipolar transistors. >

Fully differential operational amplifiers using CMOS compatible ateral bipolar transistors with improved common-mode regulation

A new bias circuit for a CMOS compatible lateral bipolar transistor differential pair is presented. The circuit compensates for all process and bias dependent variations of the lateral collector current to emitter current ratio α. Experimental results show that its application to a fully differential amplifier improves the precision of the common-mode output voltage regulation by at least an order of magnitude.

A high performance CMOS compatible 8-bit current scaling D/A convertor

An 8-bit current scaling D/A convertor has been implemented in a standard 3 mu m p-well CMOS process. This convertor requires an active area of 1 mm/sup 2/ and is capable of operating at full scale currents ranging from 50 nA to 1 mA. High linearity at low full-scale (FS) currents is achieved by using CMOS compatible lateral bipolar transistors rather than MOS transistors or precision resistors to create the weighted currents. High switching speed is obtained at low current levels through improved current switch design. Test results show that differential nonlinearity is typically +or-0.1% FS, integral nonlinearity is +or-0.07% FS and the settling time is 35 ns. Two complementary output currents with high output impedance and high voltage compliance are provided.

Monolithic optical position encoder with on-chip photodiodes

A system that combines light sensors and analog and digital parts on the same CMOS chip has been fabricated. The optical and electrical properties of various photodiodes, which are fully compatible with a standard CMOS technology, are discussed. The current comparators use CMOS-compatible lateral bipolar transistors. The optical encoder also comprises a signal processor for code conversion, a serial or parallel output, and a self-test function. A 14-channel circuit which senses light signals at 880 nm with a power of 0.3-3 mW/cm/sup 2/ has been fabricated. Response time is shorter than 1 mu s at all illumination levels. This circuit operates in the temperature range -55 to +125 degrees C. Its current consumption is 8 mA at 5 V.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Precision compressor gain controller in CMOS technology

A precision gain-control compressor which makes use of a CMOS compatible lateral bipolar transistor is described. Two similar circuits are presented that enable raises to positive as well as negative powers. These circuits are specifically designed for use in CMOS hearing-aid systems.

CMOS voltage references using lateral bipolar transistors

Two bandgap references are presented which make use of CMOS compatible lateral bipolar transistors. The circuits are designed to be insensitive to the low beta and alpha current gains of these devices. Their accuracy is not degraded by any amplifier offset. The first reference has an intrinsic low output impedance. Experimental results yield an output voltage which is constant within 2 mV, over the commercial temperature range (0 to 70/spl deg/C), when all the circuits of the same batch are trimmed at a single temperature. The load regulation is 3.5 /spl mu/V//spl mu/A, and the power supply rejection ratio (PSRR) at 100 Hz is 60 dB. Measurements on a second reference yield a PSRR of minimum 77 dB at 100 Hz. Temperature behaviour is identical to the first circuit presented. This circuit requires a supply voltage of only 1.7 V.