CMOS Active Pixel Image Sensor Research Articles

Multi-MGy Radiation Hard CMOS Image Sensor: Design, Characterization and X/Gamma Rays Total Ionizing Dose Tests

A Radiation Hard CMOS Active Pixel Image Sensor has been designed, manufactured and exposed to X and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{60}{\rm Co}\,\, \gamma $</tex></formula> -ray sources up to several MGy of Total Ionizing Dose (TID). It is demonstrated that a Radiation-Hardened-By-Design (RHBD) CMOS Image Sensor (CIS) can still provide useful images after <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$10~\hbox{MGy}({\rm SiO}_2)$</tex></formula> (i.e. 1 Grad). This paper also presents the first detailed characterizations of CIS opto-electrical performances (i.e. dark current, quantum efficiency, gain, noise, transfer functions, etc.) in the MGy range. These results show that it is possible to design a CIS with good performances even after having absorbed several MGy. Four different RHBD photodiode designs are compared: a standard photodiode design, two well known RHBD layouts and a proposed improvement of the gated photodiode design. The proposed layout exhibits the best performances over the entire studied TID range and further optimizations are discussed. Several original MGy radiation effects are presented and discussed at the device and circuit levels and mitigation techniques are proposed to improve further the radiation hardness of future Rad-Hard CIS developments for extreme TID applications (e.g. for nuclear power plant monitoring/dismantling, experimental reactors (e.g. ITER) or next generation particle physics experiments (e.g. CERN)).

CAMERA-ON-A-CHIP: TECHNOLOGY TRANSFER FROM SATURN TO YOUR CELL PHONE

The invention of the CMOS active pixel image sensor “camera-on-a-chip” at the NASA Jet Propulsion Laboratory at Caltech and its subsequent development and commercialization via the spinoff company Photobit Corporation are discussed. The article traces the arc of the technology from innovation, technology transfer, and entrepreneurial startup to its use today in nearly all mobile phone cameras, tablet and web cameras, medical and automotive cameras, and many other applications.

A Single-Transistor Active Pixel CMOS Image Sensor Architecture

A single-transistor CMOS active pixel image sensor (1 T CMOS APS) architecture is proposed. By switching the photosensing pinned diode, resetting and selecting can be achieved by diode pull-up and capacitive coupling pull-down of the source follower. Thus, the reset and selected transistors can be removed. In addition, the reset and selected signal lines can be shared to reduce the metal signal line, leading to a very high fill factor. The pixel design and operation principles are discussed in detail. The functionality of the proposed 1T CMOS APS architecture has been experimentally verified using a fabricated chip in a standard 0.35 μm CMOS AMIS technology.

A charge pump for driving CMOS active pixel reset

To overcome the limitation of low image signal swing range and long reset time in four transistor CMOS active pixel image sensor, a charge pump circuit is presented to improve the pixel reset performance. The charge pump circuit consists of two stage switch capacitor serial voltage doubler. Cross-coupled MOSFET switch structure with well close and open performance is used in the second stage of the charge pump. The pixel reset transistor with gate voltage driven by output of the pump works in linear region, which can accelerate reset process and complete reset is achieved. The simulation results show that output of the charge pump is enhanced from 1.2 to 4.2 V with voltage ripple lower than 6 mV. The pixel reset time is reduced to 1.14 ns in dark. Image smear due to non-completely reset is eliminated and the image signal swing range is enlarged. The charge pump is successfully embedded in a CMOS image sensor chip with 0.3 × 106 pixels.

Photodiode Peripheral Utilization Effect on CMOS APS Pixel Performance

A photodiode (PD)-type CMOS active pixel sensor (APS) pixel is comprised of a reverse-biased p-n-junction diode (PD) for photon conversion and charge storage, and a number of MOS transistors. Junction capacitance of the PD has two major components; bottom plate (area) and side wall (periphery). Both play important roles in the electro-optical performance of PD-APS pixels. This paper reports PD peripheral junction utilization effects on the pixel's electro-optical performance, full-well capacity and spectral response for an 18times 18 mum CMOS PD-APS pixel were improved by opening multiple circular holes in the PD diffusion layer. A prototype CMOS APS imager was designed, fabricated, and tested in 0.5-mum, 5 V, 2P3M CMOS process, containing a 424 times 424 pixel array with smaller sub-arrays for multiple pixel designs. Four test pixels with 7, 11, 14, and 17 circular, 1.6-mum-diameter holes were placed on one pixel array, with one control pixel for reference. Pixel characteristics, dark current, PD capacitance, quantum efficiency, sensitivity, and pixel full-well capacity were measured. It was found that increased PD junction peripheral would potentially help to improve total capacitance of the PD, with the expense of higher dark current. We also found that increased PD peripheral capacitance improves spectral response up to 12% of the PD-APS pixel, especially at short wavelengths.

Reduced Human Perception of FPN Noise of the Pyramidal Readout CMOS Image Sensor

A novel CMOS active pixel sensor imager, called pyramidal readout architecture, is presented in which the 1D row sampling of a classical imager is replaced by a 2D ring sampling and diagonal output buses. The first characteristic resulted in enhancement of the readout speed of the imager, while the second characteristic is shown here to make fixed pattern noise (FPN) less perceptible to the human visual system (HVS). This observation exploits the relatively poor sensitivity of the HVS to obliquely distributed patterns, known as the oblique effect. The effect was modeled using a spatial filter derived from measured characteristics of the HVS, and applied to the obliquely distributed FPN-dominated images of the pyramidal CMOS imager.

High speed SOI CMOS image sensor with pinned photodiode on handle wafer

We have fabricated SOI CMOS active pixel image sensor with pinned photodiode on handle wafer. The structure of one pixel is a four-transistor type active pixel image sensor, which consists of a reset and a source follower transistor on seed wafer, and is comprised of a photodiode, a transfer gate, and a floating diffusion on handle wafer. The photodiode could be optimized for better quantum efficiency and low dark currents because the process of a photodiode on handle wafer is independent of that of transistors on seed wafer. Most of the wavelengths are absorbed within the visible range, because the optimized photodiode is located on the handle wafer. The response time of SOI CMOS active pixel sensor was about 2 times faster than that of bulk CMOS active pixel image sensor.

LOW VOLTAGE SOI CMOS IMAGE SENSOR WITH PINNED PHOTODIODE ON HANDLE WAFER

We have fabricated 32 × 32 SOI CMOS active pixel image sensor with pinned photodiode on handle wafer in order to reduce dark current, transfer charge completely, and improve spectral response. The four transistor type active pixel image sensor is comprised of reset and source follower transistors on SOI seed wafer, while the pinned photodiode, transfer gate, and floating diffusion are fabricated on SOI handle wafer. The pinned photodiode could be optimized because the process of the photodiode on SOI handle wafer is independent of the transistor process on SOI seed wafer. The optimized pinned photodiode is simulated in order to understand complete charge transfer at 3.3 V and 2.5 V of transfer gate voltage, respectively. We also investigated the optical response of fabricated active pixel image sensor under different illumination density conditions from He - Ne laser source at 3.3 V and 2.5 V of transfer gate voltage.

A CMOS active pixel sensor based DNA micro-array with nano-metallic particles detection protocol

A DNA micro-array (DMA) for DNA detection is reported. The DMA combines a standard CMOS active pixel image sensor with a DNA detection protocol utilizing the binding of DNA targets and probes functionalized with gold nano-particles that can modify the opaqueness at the detection site. The DMA has been fabricated using a 0.5 μm CMOS process together with on-chip timing control and correlated double sampling. Experimental results show that the system can detect DNA samples with extremely low concentration down to 10 pM using ordinary light source.

A 1.5-V 550-μW 176 x 144 autonomous CMOS active pixel image sensor

This paper addresses the development of a micropower 176/spl times/144 CMOS active pixel image sensor that dissipates one to two orders of magnitude less power than current state-of-the-art CMOS image sensors. The chip operates from a 1.5-V voltage source and the power consumption measured for the chip running from an internal 25.2-MHz clock yielding 30 frames per second is about 550 /spl mu/W. This amount enables the sensor to run from a watch battery. In order to achieve design goals, a low-power sensor design methodology is applied throughout the design process from system-level to process-level, while realizing the performance to satisfy the design specification. As an autonomous sensor, it can be operated with only three pads [GND, VDD (1.2-1.7 V), DATAOUT]. The die occupies 4 mm/sup 2/ of silicon.

Transversal-readout architecture for CMOS active pixel image sensors

Novel architecture for CMOS active pixel image sensors (APSs), which eliminates the vertically striped fixed pattern noise (FPN), is presented. There are two kinds of FPN for CMOS APSs. One originates from the pixel-to-pixel variation in dark current and source-follower threshold voltage, and the other from the column-to-column variation in column readout structures. The former may become invisible in the future due to process improvements. However, the latter, which results in a vertically striped FPN, is and will be conspicuous without some subtraction because of the correlation in the vertical direction. The pixel consists of a photodiode, a row- and column-reset transistor, a source-follower input transistor, and a column-select transistor instead of the row-select transistor found in conventional CMOS APSs. The column-select transistor is connected to a signal line that runs horizontally instead of vertically. An experimentally fabricated 320/spl times/240-pixel CMOS APS employing the transversal-readout architecture exhibited neither vertically nor horizontally striped FPN. A buried-photodiode device with the transversal-readout architecture is also proposed.

An ultra-low dark current CMOS image sensor cell using n/sup +/ ring reset

We present in this letter for the first time a new CMOS image sensor cell using n/sup +/-ring-reset structure, which can isolate the photon-sensing area from the defective field oxide edge. The experimental results demonstrate that the severe dark current degradation of the conventional CMOS active pixel image sensor fabricated by a standard CMOS logic process is significantly alleviated. Through optimizing the layout arrangement, as high as 45% fill factor can be obtained. The dynamic range of this new cell can thus be improved by more than 10/spl times/ compared to a conventional cell.

Readout circuit for CMOS active pixel image sensor

The design and simulation results of a new readout circuit for a CMOS active pixel image sensor are presented. This scheme removes the fixed pattern noise and reduces the signal degradation while offering an increase in readout speed, compared with the conventional approach.

Analysis and reduction of signal readout circuitry temporal noise in CMOS image sensors for low-light levels

In this paper, analytical noise analysis of correlated double sampling (CDS) readout circuits used in CMOS active pixel image sensors is presented. Both low-frequency noise and thermal noise are considered. The results allow the computation of the output RMS noise versus MOS transistor dimensions with the help of SPICE-based circuit simulators. The reset noise, the influence of floating diffusion capacitance on output noise and the detector charge-to-voltage conversion gain are also considered. Test circuits were fabricated using a standard 0.7 /spl mu/m CMOS process to validate the results. The analytical noise analysis in this paper emphasizes the computation of the output variance, and not the output noise spectrum, as more suitable to CDS operation. The theoretical results are compared with the experimental data.

A Stacked CMOS Active Pixel Image Sensor for Charge Particle Detection and the Application to SIMS

A stacked CMOS active pixel image-sensor (APS) has been developed for detecting various kinds of charged particles and its noise performance has been measured and analyzed. The sensitivity for ions and electrons with keV energy level utilizes for ion microscopy such-as SIMS and electron microscopy, respectively.Charge particles such as ions and electrons with kinetic energy of keV order are useful probes for surface analysis of material. A measurement system which yields two-dimensional image of charge particles is highly demanded. The conventional two-dimensional detection system is composed of a micro channel plate, a florescent plate which receives multiplied secondary electrons and generates a visible image, and a visible image sensor. However, its limited dynamic range and non-linearity in the ion-electron-to-photon conversion process make a quantitative measurement difficult. The proposed system using a stacked CMOS APS has several advantages over the conventional system such as high spatial resolution, no insensitive time, high S/N, wide dynamic range, nondestructive readout capability, high robustness, and low power consumption.

Non-stationary noise responses of some fully differential on-chip readout circuits suitable for CMOS image sensors

CMOS active-pixel image sensors, as well as charge-coupled devices, generate both white noise and 1/f/sup /spl alpha//-noise over several decades depending on biasing current, operating temperature, and the characteristics of the process used, limiting the detector dynamic range. Three readout circuits, based on a fully differential cascode operational transconductance amplifier, designed and realized on a standard CMOS 0.7-/spl mu/m single polysilicon/double metal process, are proposed for CMOS active-pixel imagers. The first is an uncompensated switched capacitor (SC) voltage amplifier; the second, an offset compensated SC amplifier; and the third, a commutable bandpass filter. All three amplifiers allow correlated double sampling and double delta sampling for pixel and column fixed pattern noise suppression, respectively. The amplifiers offer up to 10-Mpixels/s readout rates. A detailed theoretical analysis of the amplifiers response to white noise and low-frequency excess noise is given, considering nonstationary nature of the output signals. An original method based on diffusive Markovian representation of 1/f/sup /spl alpha//-noise is used. The theoretical results are compared with experimental data.

CMOS active pixel image sensors fabricated using a 1.8-V, 0.25-μm CMOS technology

This paper reports the experimental results of the first CMOS active pixel image sensors (APS) fabricated using a high-performance 1.8-V, 0.25-/spl mu/m CMOS logic technology. No process modifications were made to the CMOS logic technology so that the impact of device scaling on the image sensing performance can be studied. This paper highlights the device and process design considerations required to enable CMOS as an image sensor technology.

CMOS active pixel image sensors for highly integrated imaging systems

A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-/spl mu/m CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression of fixed pattern noise to less than 0.1% saturation are demonstrated. The baseline design achieved a pixel size of 40 /spl mu/m/spl times/40 /spl mu/m with 26% fill-factor. Array sizes of 28/spl times/28 elements and 128/spl times/128 elements have been fabricated and characterized. Typical output conversion gain is 3.7 /spl mu/V/e/sup -/ for the p-well devices and 6.5 /spl mu/V/e/sup -/ for the n-well devices. Input referred read noise of 28 e/sup -/ rms corresponding to a dynamic range of 76 dB was achieved. Characterization of various photogate pixel designs and a photodiode design is reported. Photoresponse variations for different pixel designs are discussed.

CMOS active pixel image sensor with simple floating gate pixels

A new pixel structure using a simple floating gate (SFG) has been proposed. The pixel consists of a coupling capacitor, a photogate, a barrier gate and a MOS transistor. It features complete reset that results in no kTC noise and no image lag, high blooming overload protection, nondestructive readout (NDRO), and CMOS compatibility. Its basic operation has been confirmed with a 32(H)/spl times/27(V) pixel area array. Since the pixel structure is relatively simple, small pixel size is feasible. >

CMOS active pixel image sensor

A new CMOS active pixel image sensor is reported. The sensor uses a 2.0 /spl mu/m double-poly, double-metal foundry CMOS process and is realized as a 128/spl times/128 array of 40 /spl mu/m/spl times/40 /spl mu/m pixels. The sensor features TTL compatible voltages, low noise and large dynamic range, and will be useful in machine vision and smart sensor applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>