Clustered Fault Research Articles

Temporal and spatial earthquake clustering revealed through comparison of millennial strain-rates from 36Cl cosmogenic exposure dating and decadal GPS strain-rate

To assess whether continental extension and seismic hazard are spatially-localized on single faults or spread over wide regions containing multiple active faults, we investigated temporal and spatial slip-rate variability over many millennia using in-situ 36Cl cosmogenic exposure dating for active normal faults near Athens, Greece. We study a ~ NNE-SSW transect, sub-parallel to the extensional strain direction, constrained by two permanent GPS stations located at each end of the transect and arranged normal to the fault strikes. We sampled 3 of the 7 seven normal faults that exist between the GPS sites for 36Cl analyses. Results from Bayesian inference of the measured 36Cl data implies that some faults slip relatively-rapidly for a few millennia accompanied by relative quiescence on faults across strike, defining out-of-phase fault activity. Assuming that the decadal strain-rate derived from GPS applies over many millennia, slip on a single fault can accommodate ~ 30–75% of the regional strain-rate for a few millennia. Our results imply that only a fraction of the total number of Holocene active faults slip over timescales of a few millennia, so continental deformation and seismic hazard are localized on specific faults and over a length-scale shorter than the spacing of the present GPS network over this time-scale. Thus, (1) the identification of clustered fault activity is vital for probabilistic seismic hazard assessments, and (2) a combination of dense geodetic observations and palaeoseismology is needed to identify the precise location and width of actively deforming zones over specific time periods.

Herringbone-Based TSV Architecture for Clustered Fault Repair and Aging Recovery

Three-dimensional integrated circuits (3D ICs) utilizing through-silicon via (TSV) technology have many advantages over 2D ICs including high bandwidth, high density, and low power consumption. However, TSV, which is a key feature of 3D ICs, has not only problems due to defects in the manufacturing process, but also potential problems due to aging. Various solutions have been proposed to address each of these issues, but no one solution has been proposed considering both. In practice, to improve the overall reliability of the TSV, the two problems should be solved together, not separately. In this paper, a new TSV architecture is proposed to cope with both issues. The proposed TSV architecture uses redundant TSVs (RTSVs) to repair faulty TSVs due to manufacturing defects and uses unused RTSVs in this way to solve the aging-related problems. Experimental results show that the proposed architecture achieves similar repair rate with less than 1% difference in less than 6 clustered faults using smaller hardware overhead, and also shows that unused RTSVs are available with a 98.5% high probability, resulting in a 1.5 times improvement in lifetime.

Flexible scheme for reconfiguring 2D mesh-connected VLSI subarrays under row and column rerouting

In the mesh-connected processors, some processor elements (PEs) become ineffective due to high temperature, overload and other factors, which can affect the stability of the system. This paper deals with the problem of reconfiguring the largest possible subarray from the processor with faults under the row and column rerouting constraint. Firstly, a flexible routing scheme, based on dynamic programming, is proposed to construct the local optimal logical columns. Secondly, we discuss and revise the PEs that cannot be connected between every two logical columns under this scheme. Finally, an efficient algorithm is presented to construct the maximum subarray in polynomial time. The experimental results show that, both on the random and clustered fault scenarios, the proposed algorithm under flexible rerouting scheme is capable of constructing the larger scale logical arrays. On a 48 × 48 host array with 15% fault density, the improvement on the use of fault-free PEs is up to 6.22% for random faults. On a 256 × 256 host array, the improvement can be up to 85.60% for clustered faults. Moreover, the proposed algorithm runs faster than previous algorithms under different size arrays and fault densities, the average improvement in running time is up to 99% compared with state-of-the-art.

Global block level redundancy scheme for repair of clustered fault cells

Global block level redundancy scheme for repair of clustered fault cells

Optimal Reconfiguration of High-Performance VLSI Subarrays with Network Flow

A two-dimensional mesh-connected processor array is an extensively investigated architecture used in parallel processing. Massive studies have addressed the use of reconfiguration algorithms for the processor arrays with faults. However, the subarray generated by previous algorithms contains a large number of long interconnects, which in turn leads to more communication costs, capacitance and dynamic power dissipation. In this paper, we propose novel techniques, making use of the idea of network flow, to construct the high-performance subarray, which has the minimum number of long interconnects. First, we construct a network flow model according to the host array under a specific constraint. Second, we show that the reconfiguration problem of high-performance subarray can be optimally solved in polynomial time by using efficient minimum-cost flow algorithms. Finally, we prove that the geometric properties of the resulted subarray meet the system requirements. Simulations based on several random and clustered fault scenarios clearly reveal the advantage of the proposed technique for reducing the number of long interconnects. It is shown that, for a host array of size $512 \times 512$ , the number of long interconnects in the subarray can be reduced by up to 70.05 percent for clustered faults and by up to 55.28 percent for random faults with density of 1 percent as compared to the-state-of-the-art.

Reconfiguration algorithms for power efficient VLSI subarrays with four-port switches

Techniques to determine subarrays when processing elements of VLSI arrays become faulty have been investigated extensively. These tend to identify the largest subarray that is possible without concentrating on the power efficiency of the resulting subarray. In this paper, we propose new techniques, based on heuristic strategy and dynamic programming, to minimize the interconnect length in an attempt to reduce power dissipation without performance penalty. Our algorithms show that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing the size of the subarray. Our evaluations show that, for a VLSI array of size 256/spl times/256, the number of long interconnects in the subarray can be reduced by up to 95 percent for clustered faults and up to 50 percent and 73 percent for a random fault with density of 10 percent and 0.1 percent, respectively, when compared with the most efficient implementation cited in the literature. The interconnect power saving for a VLSI array of size 512/spl times/512 is by up to 11 percent for a random fault. We have also shown that interconnect power savings of up to 14 percent are possible for the cases investigated. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques for power efficient realizations. In addition, the lower bound of the performance has been proposed to demonstrate that the proposed algorithms are nearly optimal for the cases considered in this paper.

Power Efficient Sub-Array in Reconfigurable VLSI Meshes

Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.

Fault-simulation programs for integrated-circuit yield estimations

Three programs are described here which have been used for integrated-circuit yield modeling at the IBM facility in Essex Junction, Vermont. The first program generates negative binomial distributions which are used to represent the frequency distribution of the number of faults per chip. Calculations with the generalized combination function A ! B in APL are limited to simulations of up to 99,999 faults, and can take too much computer time to run. These limitations are eliminated when the calculations make use of the scan function. The second program simulates clustered fault locations on a map. The clusters are initially generated using a radial Gaussian probability distribution. Each fault location is stored as a complex number, which facilitates the use of cluster-shaping programs that are also described. In a third program, another simulator of fault maps, faults are added as a function of time. This program also results in fault distributions that are clustered. In addition, it produces frequency distributions that very closely approximate negative binomial distributions.

Simulation of spatial fault distributions for integrated circuit yield estimations

Two methods used in fault simulation for integrated circuit modeling are described. Both methods simulate clustered fault locations on a map. In the first approach, the clusters are initially generated using a radial Gaussian probability distribution. The results are consequently passed through cluster shaping programs, which produce clusters that resemble those observed on actual integrated circuit wafers. In the second approach, faults are added to the chips as a function of time. The probability that additional faults are created during any interval of time is assumed to be related to the number of faults already on the chip, as well as the number of faults on adjacent chips. This technique generates frequency distributions of the number of faults per chip that closely resemble those observed in actual integrated circuits. >