Clock Logic Research Articles

A low-power common-mode insensitive rail-to-rail dynamic comparator for ADCs

This paper presents a low-power, high-speed dynamic comparator with a rail-to-rail input common-mode (Vi,cm) range. The proposed comparator has high-speed performance throughout the 0-Vdd Vi,cm range, thus attributing common-mode insensitivity. This work introduces a merger of NMOS and PMOS dynamic pre-amplifiers with a modified latch to achieve the rail-to-rail Vi,cm operation. A novel activation clock logic is also proposed, activating only one pre-amplifier based on the Vi,cm value and ensuring low-power consumption and provides reduction of 17% in the energy per conversion as compared to the comparator without activation clock logic. The proposed comparator is designed using 65-nm CMOS technology with a 1.2 V supply voltage and is operating at 1 GHz frequency. We have presented the analytical models of the delay and offset which is verified with the rigorous post-layout simulation results. To validate the robustness of the proposed comparator, the PVT corner analysis with Monte Carlo simulation is also performed for different Vi,cm.

An Integrated Approach towards VLSI Implementation of SFQ Logic using Standard Cell Library and Commercial Tool Suite

Abstract The semiconductor industry seeks energy-efficient alternatives as Moore’s law nears its limits. The Single Flux Quantum (SFQ) integrated circuits (ICs) using thousands of niobium Josephson junctions (JJs) and operating at 4 K show great promise for digital computing circuits at high speed (>20 GHz) and low power (a few nW per junction). The leading logic families are Rapid Single Flux Quantum (RSFQ), and its energy-efficient variant (ERSFQ). IARPA’s SuperTools program aims to develop integrated design tools for superconductor electronics, targeting SFQ and Adiabatic Quantum-Flux-Parametron (AQFP) logic families. This paper presents a passive transmission line (PTL) based standard cell library for SFQ logic, designed with Synopsys Electronic Design Automation (EDA) software tools for MIT-LL 100μA/μm2 SFQ5ee fab node. The dual RSFQ/ERSFQ standard cell library facilitates seamless integration of SFQ RTL-to-GDS design flow with Synopsys Fusion Compiler, an automated design tool. The SFQ RTL-to-GDS flow entails logic synthesis, checking, placement, clock synthesis, and routing. Row-based placement for library cells and H-tree clock tree structures are employed. Fusion Compiler’s effectiveness is validated with Hypres designs such as finite impulse response (FIR) filters, scalable multiply-accumulate (MAC) units, and memory arrays, comparing single and dual clocking schemes. The synergy between Hypres and Synopsys achieves a milestone by demonstrating the design of a digital superconducting circuit with over 10 million JJs, facilitated by a fully automated design tool for the first time. Challenges in very large-scale SFQ scaling are also discussed.

A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique

This paper presents a low-jitter and low-phase noise type-II charge pump and switched-loop filter-based (SLF) phase-locked loop (PLL) with a fast phase error correction technique (FPEC) and a newly proposed dual-edge phase comparator (DEPC). To improve the phase noise, the bandwidth of the proposed PLL is extended to fREF/5 using the proposed DEPC. It consists of four D flip-flops in true single-phase clock (TSPC) logic, four current-mode logic-based inverters, and two logic OR gates. Unlike conventional DEPCs, the proposed DEPC has a small reset pulse width duration and negligible blind zone, and due to this, it can perform at higher frequencies along with an increased phase detection range. The proposed architecture is implemented for a 2.4 GHz output frequency that embodies DEPC and SLF using the FPEC technique in an 180-nm Semi-Conductor Laboratory (SCL) CMOS process. The proposed DEPC can work up to a maximum of 3.45 GHz frequency with 145 ps of reset delay. The proposed PLL accomplishes the 40 MHz bandwidth with a 200 MHz reference clock. The simulated rms jitter integrated from 10 kHz to 100 MHz and the phase noise of the output signal at an offset of 1 MHz are 860 fs and −122 dBc/Hz respectively. The proposed architecture occupies an area of 0.032 mm2 and consumes 8.2 mW from 1.8 V power supply.

High-precision Time Synchronization Algorithm for Unmanned Aerial Vehicle Ad Hoc Networks based on Bidirectional Pseudo-range Measurements

The increasing demand for missions involving unmanned aerial vehicles (UAVs) raises the need for reliable and accurate time synchronization in ad hoc networks. Time synchronization plays a crucial role in coordinating the actions of multiple UAVs, particularly when it comes to positioning, coordination, and data fusion. However, achieving high-precision time synchronization is challenging due to the difficult-to-estimate communication transmission delay, measurement noise, relative motion, and clock source characteristics in wireless ad hoc networks formed by UAVs. To address this issue, this paper proposes a fully distributed high-precision network time synchronization algorithm that is suitable for multi-hop dynamic ad hoc networks. The proposed algorithm is based on bidirectional pseudo-range measurements, graph theory, and random matrix correlation theory. It is composed of relative clock skew estimation, logic clock skew compensation and logic clock offset compensation. The algorithm is rigorously derived, requiring no central node, and it is capable of obtaining relative clock skew even when nodes broadcast clock information asynchronously. In addition, the proposed algorithm enables real-time elimination of transmission delays and has noise-resistant capabilities. Simulation results validate the effectiveness of the algorithm, demonstrating that the time synchronization accuracy in UAV ad hoc networks can reach the sub-nanosecond level.

Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency divider

Abstract Pre-scalers are electronic circuits used in phase-locked loops to multiply frequencies. This is achieved by dividing the high-frequency signals generated from a voltage-controlled oscillator. The high-frequency operation of pre-scaler circuits leads to significantly higher power consumption. To address this, D flip-flops (D-FF) realized using true-single phase clocking (TSPC) logic. The work suggests incorporating the Adaptive Voltage Level Source (AVLS) circuit with the Dual Modulus Pre-Scaler (DMPS) circuit to reduce power consumption. In addition to the incorporation of the AVLS circuit, pass transistor logic (PTL) used in the feedback, further minimizes transistors and power. This paper proposes three different designs for divide-by-32/33 DMPS circuit. The proposed-1 design combines regular TSPC-based D-FF with PTL in the feedback and an AVLS circuit, resulting in an average power reduction of 36.5%. The proposed-2 design employs split-path TSPC-based D-FF with logic gates and an AVLS circuit, achieving a power reduction of 46.9%. The proposed-3 design employs split-path TSPC-based D-FF with PTL in the feedback and an AVLS circuit, achieving a significant power reduction of 47.8% compared to the existing DMPS circuit and transistor count by 9.1%. The proposed circuits are realized using a CMOS 180 nm technology node. Cadence Virtuoso and Spectre tools are used. The proposed divide-by-32/33 DMPS circuits also realized in the CMOS 45 nm technology node to verify the functionality in the lower technology node. A power reduction of 46.86% observed when compared to the reference circuit. The proposed designs are both power- and area-efficient, making them promising solutions for minimizing power consumption in pre-scaler circuits.

A 1.38-mW 7-bit 1.7-GS/s Single-Channel Loop-Unrolled SAR ADC in 22-nm FD-SOI With 8.85 fJ/Conv.-Step for GHz Mobile Communication and Radar Systems

A 7-bit single-channel loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) with a sampling rate of 1.7 GS/s at a power consumption of 1.38 mW is presented. To prove the concept, the circuit was fabricated in a 22-nm fully depleted silicon-on-insulator (FD-SOI) technology. It achieves an effective number of bits (ENOB) of 6.52 and a Walden figure-of-merit () of 8.85 fJ/conv.-step. High sampling speed is achieved by introducing optimized logic, heavily employing dynamic logic for the critical building blocks as the memory cells and clock logic. Sharing of reset transistors between multiple memory cells further reduces the delay between comparator decision and switching of the capacitive digital-to-analog converter (CDAC) by 15%. For calibration of the comparator offset, tuning of the back-gate voltage available in the FD-SOI technology is investigated and employed. Compared with conventional approaches using a separate differential input pair, this reduces the comparator power dissipation by 5% and its noise by 10%. The ADC operates on a single 800-mV supply and uses an active area of 0.0022 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The ADC is the fastest <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula> 6-bit ENOB single-channel SAR (or pipelined SAR) ADC, while at the same time achieving the best for any previously reported ADC above 1 GS/s.

Asynchronous Single Flux Quantum Logic Gates Using Self-Clocking

We propose an asynchronous single flux quantum (SFQ) logic gate composed of a conventional clocked logic gate and an input signal merger that generates a self-clock for the clocked logic gate. By using this self-clocking, we can design any 0-preserving logic gate, including exclusive OR (XOR). The proposed asynchronous SFQ logic gates have adjustable allowable input skew by varying the delay between the merger and internal clock input for the clocked logic gate. We design and evaluate the asynchronous AND, OR, and XOR gates that have an allowable input skew of approximately 8 ps assuming the use of the 10 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Nb fabrication process using the proposed design method. We experimentally confirm the correct operation of the asynchronous SFQ XOR gate. We design a completely asynchronous 4-bit-input carry-lookahead adder (CLA) using the designed asynchronous gates. We found that the circuit area and number of Josephson junctions required to design a 4-bit-input CLA can be reduced by > 50% compared to that of the synchronous concurrent-flow 4-bit-input CLA without deterioration of the throughput.

An Extended Range Divider Technique for Multi-Band PLL

This paper presents a multiplexer-based extended range multi-modulus divider (ER-MMD) technique for multi-band phase locked loop (PLL). The architecture maintains a modular structure by using conventional 2/3 divider cells and a multiplexer without adding any extra logic circuitry. The area and power overhead is minimal. The 2/3 divider cells are designed using true single phase clock (TSPC) logic for ER-MMD to operate in the sub-10 GHz range. A division range of 2 to 511 is achieved using this logic. The ER-MMD operates at a maximum frequency of 6 GHz with a worst-case current of 625 μA when powered with a 1 V supply. A dual voltage controlled oscillator (VCO), L5/S band PLL for Indian Regional Navigation Satellite System (IRNSS) application is designed, which incorporates an ER-MMD based on the proposed approach as a proof of concept. This technique achieves the best power efficiency of 12 GHz/mW, among the state-of-the-art ER-MMD designs.

AVLS-based 32/33 Pre-scaler for frequency dividers

Pre-scalers are widely used in phase-locked loops (PLL) which are vital components in communication systems. The Dual Modulus Pre-Scaler (DMPS) has dual division capability, to divide the clock by N/N+1 cycles, which can be controlled by the designer based on the control circuitry. Pre-scaler circuits are used to divide the received signal to obtain integer multiples of the received signal. This paper proposes a power efficient 32/33 pre-scaler for high-frequency operation. DMPS is composed of a series of D Flip-flops (D-FF) and logic gates along with feedback connection between the different stages. Clock skew is of major concern in the D-FFs, which can be reduced by realizing D-FFs using true single-phase clock (TSPC) logic. Furthermore, the incorporation of an Adaptive Voltage Level Source (AVLS) circuit decreases the power consumption of the circuits. By integrating the AVLS circuit to divide-by-32/33 DMPS, low power consumption is achieved. At different operating frequencies, both divide-by-32 and -33 modes of the proposed 32/33 DMPS with AVLS were analyzed. In comparison to the reference pre-scaler circuit, the proposed pre-scaler consumes 35.65% less power at 1GHz. CMOS 180nm technology in Cadence Virtuoso is used to realize circuits and Cadence Spectre is used to simulate circuits.

Real-time experimental demonstration of a computationally efficient hybrid OFDM DFMA PON

This paper presents the first real-time experimental demonstration of a hybrid OFDM DFMA PON. The presented PON is validated for two channels (I or Q) occupying two subwavelength bands. The hybrid OFDM DFMA PON eliminates the need for a dedicated matching filter at the receiver for each individual channel, by employing a single FFT operation to recover all channels, thereby achieving lower computational complexity. The hybrid OFDM DFMA PON used in conjunction with a joint sideband processing technique, when compared to a DFMA PON under the exact same operating conditions, is shown to offer increased performance, including a lower received optical power of up to 1.2 dB for the adopted FEC limit at a given bit rate. The experimentally demonstrated PON is also proven to be significantly more tolerant to the symbol timing offset effect at the OLT receiver. Furthermore, compared to the DFMA PON’s OLT receiver, the implemented FFT-based receiver is shown to operate at a drastically reduced logic clock rate and with significantly lower DSP complexity. The hybrid OFDM DFMA PON is thus shown to have numerous advantages over the DFMA PON.

A High-Level Approach for Energy Efficiency Improvement of FPGAs by Voltage Trimming

Chip manufacturers define voltage margins on top of the “best-case” operational voltage of their chips to ensure reliable functioning in the worst-case settings. The margins guarantee correctness of operation, but at the cost of performance and power efficiency. Violating the margins is tempting to save energy, but might lead to timing errors. This article proposes an algorithmic solution that enables reliable removal of the margins by detecting errors on the fly. In contrast to previous approaches that require special hardware to detect timing errors, the proposed method is fully implementable using high-level synthesis tools without reliance on additional hardware. The approach is demonstrated using a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$32 \times 32$ </tex-math></inline-formula> matrix-matrix multiplication and a simple multilayer neural network implemented on two Xilinx ZC702 field-programmable gate array (FPGA) System-on-Chip (SoC) platforms, showcasing its utility in detecting errors that may originate from different sources of logic circuits, clock tree, or memory. Results show that the energy dissipation is halved, while the implementation is clocked at 2.5x faster than specified by the design tool of the vendor.

Evaluation of the systematic shifts of a $${}^{40}\text {Ca}^{+}$$–$${}^{27}\text {Al}^{+}$$ optical clock

Quantum-logic-based ${}^{27}\textrm{Al}^+$ optical clock has been demonstrated in several schemes as there are different choices of the auxiliary ion species. In this paper, we present the first detailed evaluation of the systematic shift and the total uncertainty of an ${}^{27}\textrm{Al}^+$ optical clock sympathetically cooled by a ${}^{40}\textrm{Ca}^+$ ion. The total systematic uncertainty of the ${}^{40}\textrm{Ca}^+ - {}^{27}\textrm{Al}^+$ quantum logic clock has been estimated to be $7.9 \times 10^{-18}$, which was mainly limited by the uncertainty of the quadratic Zeeman shift. By comparing the frequency of two counter-propagating clock beams on the same ion, we measured the frequency stability to be $3.7 \times 10^{-14} /\sqrt{\tau}$.

A 5-GHz 0.15-mm² Collision-Avoiding RFID Employing Complementary Pass-Transistor Adiabatic Logic With an Inductively Connected External Antenna in 0.18-μm CMOS

A low-power, small form factor, and collision avoiding RFID tag is proposed. By applying complementary passtransistor adiabatic logic (CPAL) and two-phase clock, not only the required power of operation is lowered, but also large capacitors necessary for stable operation are eliminated, which leads to a reduced chip size. Additionally, the external antenna used is inductively connected instead of solder-bonded, which contributes to a lower assembly cost. A collision avoidance system exploiting counter and bit shift is also proposed. Results show the proposed RFID is capable of communication twice as far as the one using conventional adiabatic logic with one-eighth of the reader’s transmission power, as well as having the whole chip downsized by 94%. It is also confirmed that collisions between three tags are avoided thanks to the collision avoidance system.

Reconfigurable Architectures with High-Frequency Noise Suppression for Wearable ECG Devices.

Recent advances in electronics and microelectronics have aided the development of low-cost devices that are widely used as well-being or preventive monitoring devices by many people. Remote health monitoring, which includes wearable sensors, actuators, and modern communication and information systems, offers effective programs that allow people to live peacefully in their own homes while also being protected in some way. High-frequency noise, power-line interface, and baseline drift are prevalent during the data-acquisition system of an ECG signal, and they can limit signal understanding. They (noises) must be isolated in order to provide an appropriate diagnostic of the patient. When removing high-frequency components (noise) from an ECG signal with an FIR filter, the critical path delay increases considerably as the filter's duration increases. To reduce high-frequency noise, simple moving average filters with pipelining and look-ahead transformation techniques are extensively used in this study. With the use of pipelining and look-ahead techniques, the only objective is to increase the clock speed of the designs. The moving average filters (conventional and proposed) were created on an Altera Cyclone IV FPGA EP4CE115F29C7 chip using the Quartus II software v13.1 tool. Finally, performance metrics such logic elements, clock speed, and power consumption were compared and studied thoroughly. The recursive pipelined 8-tap MA filter with look-ahead approach outperforms the other designs (685.48 MHz) in this investigation.

A Fully Integrated 64-Channel Recording System for Extracellular Raw Neural Signals

This paper presents a fully integrated 64-channel neural recording system for local field potential and action potential. It mainly includes 64 low-noise amplifiers, 64 programmable amplifiers and filters, 9 switched-capacitor (SC) amplifiers, and a 10-bit successive approximation register analogue-to-digital converter (SAR ADC). Two innovations have been proposed. First, a two-stage amplifier with high-gain, rail-to-rail input and output, and dynamic current enhancement improves the speed of SC amplifiers. The second is a clock logic that can be used to align the switching clock of 64 channels with the sampling clock of ADC. Implemented in an SMIC 0.18 μm Complementary Metal Oxide Semiconductor (CMOS) process, the 64-channel system chip has a die area of 4 × 4 mm2 and is packaged in a QFN−88 of 10 × 10 mm2. Supplied by 1.8 V, the total power is about 8.28 mW. For each channel, rail-to-rail electrode DC offset can be rejected, the referred-to-input noise within 1 Hz–10 kHz is about 5.5 μVrms, the common-mode rejection ratio at 50 Hz is about 69 dB, and the output total harmonic distortion is 0.53%. Measurement results also show that multiple neural signals are able to be simultaneously recorded.

A 125 GHz millimeter-wave phase lock loop with improved VCO and injection-locked frequency divider in 65 nm CMOS process

In this paper, a CMOS mm-wave phase locked loop (PLL) with improved voltage controlled oscillator (VCO) and injection-locked frequency divider (ILFD) at operational harmonic frequency 125 GHz is presented. The VCO structure uses the bulk effective and MOS varactor capacitor to adjust parasitic capacitor of the cross coupled pair. It obtains 2th harmonic frequency with 24% tuning range (110–140 GHz) by applying ± 1.2 V input voltage variation. The divide-by-4 ILFD circuit uses a cross coupled VCO with three injection transistors acting in linear and nonlinear regions. The frequency dividers such as divided-by-4 ILFD, subsequent current mode logic (CML) and true single phase clock (TSPC) as divider chain with ratio 1/256 are used to synthesize frequency 244 MHz which is compared to reference frequency, 244 MHz in the PLL. Simulation results of the proposed PLL circuit are obtained after extracting post layout (with total chip size of 0.29 mm2) in 65 nm CMOS standard technology and @ 1.2 V power supply voltage. The obtained results confirm theoretical relations and indicate that the proposed circuit has good figure of merit (FoM), and higher tuning range and lower die area than the recent designs.

Finding and Eliminating Noise and Interference in a Test Stand for Josephson Digital Chips

Sources of noise and interference in a test stand for Josephson digital integrated circuits have been identified and eliminated using a novel measurement technique. The digital output of the chip was fed into a spectrum analyzer while the output pattern was 1010. The DC bias was set at the boundary between correct and incorrect operation, a 50% bit error rate. Small AC noise currents on the bias made large changes in the bit error rate. This converted noise currents to amplitude modulation sidebands of the data pattern at half of the logic clock frequency, which was 625 MHz. AC currents were injected at 454 Hz to produce AM sidebands at 625 MHz ± 454 Hz. The sideband power was directly proportional to calibration tone power over the range 50 nA to 10 μA. Noise currents on the DC bias as small as 100 nA were clearly identified at 120 Hz. The largest noise currents in the test setup were found near 40 MHz. Their spectrum of evenly spaced tones indicated that the source was a switching power supply. When an idle relay controller was turned off, the noise tones immediately disappeared from the spectrum analyzer display, confirming the source of interference. This new and easy to use technique exploited bit error rate modulation to up convert AC noise currents from low frequencies to the range 625-675 MHz. The location of the noise currents was unambiguous, since only a 60 Hz noise current on the chip could produce an AM sideband at 625 MHz plus 60 Hz.

A 15-Gb/s 0.0037-mm² 0.019-pJ/Bit Full-Rate Programmable Multi-Pattern Pseudo-Random Binary Sequence Generator

This brief presents a compact low-power programmable multi-pattern pseudo-random binary sequence (PRBS) generator. It is capable of producing 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> - 1, 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> - 1, 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">23</sup> - 1 and 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> - 1 test patterns to meet multiple testing requirements. To reduce power and area, the full-rate architecture with the truly-single-phase clock logic (TSPC) D-flip-flops (DFF) instead of the current-mode logic (CML) DFF is adopted. The multiplexer (MUX) merged TSPC DFF is proposed to avoid the delay of the MUX in conventional multiple pattern PRBS generators. Hence, the critical path delay is reduced, and thus, the maximum data rate can be improved. Fabricated in a 40-nm CMOS process (260-GHz <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> f_T</i> ), this PRBS occupies a core active area of 0.0037 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and operates at a maximum data rate of 15 Gb/s. The measured power consumption is 8.778 mW with 1.1-V supply. The figure-of-merit (FoM) is 0.019 pJ/bit at the pattern length of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> - 1.

Observation of 1S0 → 3P0 Transition of a 40Ca+ - 27Al+ Quantum Logic Clock**Supported by the National Key R&D Program of China under Grant No 2017YFA0304401, the Strategic Priority Research Program of the Chinese Academy of Sciences under Grant No XDB21030100, and the Technical Innovation Program of Hubei Province under Grant No 2018AAA045.

We report the realization of quantum logic spectroscopy on the 1S0→ 3P0 clock transition of a single 27Al+ ion. This ion is trapped together with a 40Ca+ ion in a linear Paul trap, coupled by Coulomb repulsion, which provides sympathetic Doppler laser cooling and also the means for internal state detection of the clock state of the 27Al+ ion. A repetitive quantum nondemolition measurement is performed to improve the fidelity of state detection. These techniques are applied to obtain clock spectroscopy at approximately 45 Hz. We also perform the preliminary locking on the 1S0 → 3P0 clock transition. Our work is a fundamental step that is necessary toward obtaining an ultra-precision quantum logic clock based on 40Ca+-27Al+ ions.

A Platform of Resynthesizing a Clock Architecture Into Power-and-Area Effective Clock Trees

To trigger events for application-specific data transfer among registers in a multimillion-gate system-on-chip (SoC), various kinds of clock signals, selectively driven by different frequency-dependent sources and/or dividers (DIVs), are usually centralized in one or more clock generation modules, where clock gating cells (CGCs), multiplexers (MUXes) and DIVs are used to create the clocks required by different functional operations in an SoC. These modules will introduce uncommon and longer timing paths for clock propagations and further make the clock tree synthesis (CTS) process become more challenging due to the on-chip-variation (OCV) effects. In addition, high volume of switching activities in the increased number of clock logic cells will consume more power. In this article, a novel design platform, merging and replacing of multiple multiplexers and dividers (MRMMD), is developed to intelligently identify those suspicious clock architectures and resynthesize them into a power-and-area effective and less complicated clock structure. Using our resynthesis platform, not only the number of clock-related timing paths and their corresponding logic levels can be reduced, but also the corresponding analysis and implementations of clock skew minimizations during CTS become much easier. The experimental results implemented in TSMC 55- and 28-nm process nodes on optimizing some industrial clock architectures showed that significant reductions of area, power, latency, skew and clock path, logic level, OCV impact, total wire length, and implementation runtime are achieved using our MRMMD platform.