Abstract
Chip manufacturers define voltage margins on top of the “best-case” operational voltage of their chips to ensure reliable functioning in the worst-case settings. The margins guarantee correctness of operation, but at the cost of performance and power efficiency. Violating the margins is tempting to save energy, but might lead to timing errors. This article proposes an algorithmic solution that enables reliable removal of the margins by detecting errors on the fly. In contrast to previous approaches that require special hardware to detect timing errors, the proposed method is fully implementable using high-level synthesis tools without reliance on additional hardware. The approach is demonstrated using a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$32 \times 32$ </tex-math></inline-formula> matrix-matrix multiplication and a simple multilayer neural network implemented on two Xilinx ZC702 field-programmable gate array (FPGA) System-on-Chip (SoC) platforms, showcasing its utility in detecting errors that may originate from different sources of logic circuits, clock tree, or memory. Results show that the energy dissipation is halved, while the implementation is clocked at 2.5x faster than specified by the design tool of the vendor.
Highlights
E XPECTED global energy demand of the ICT sector is projected to be 7% of total consumption by 2030
The setup was used to investigate the potential of Algorithm Based Fault Tolerance (ABFT) in operating the FieldProgrammable Gate Arrays (FPGA) at reduced voltages
[13] with ABFT in matrix multiplications on the largest layers was synthesized on the FPGA
Summary
E XPECTED global energy demand of the ICT sector is projected to be 7% of total consumption by 2030. An increasing share of this energy is consumed for Deep Neural Networks training and inference [1] in data centers, or network infrastructure computations of wireless communications Thanks to their flexibility and high performance, FieldProgrammable Gate Arrays (FPGA) have found their way into high-performance System-On-Chips (SoC) as accelerators [2]. Gate level programmability of FPGAs and recent support of HLS based EDA tools enables approaching ASIC level performance with far smaller investment times. Dynamic power has a quadratic, and static power has a linear relation to the supply voltage (Vdd), so operating at a reduced voltage lowers total energy consumption [5]. A low-overhead error detection method is proposed to enable reliable reduction of operational voltage of FPGAs. The approach detects virtually all errors in matrixmatrix multiplications, regardless of whether they originate from the logic fabric or memory. In contrast to the state of the art methods [6], [10], the implementation is carried out using only High Level Synthesis (HLS) tools without any intervention in vendor provided EDA tools or the generated netlist
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
