Clock Servo Research Articles

A Fuzzy-PI Clock Servo with Window Filter for Compensating Queue-Induced Delay Asymmetry in IEEE 1588 Networks.

Clock synchronization is one of the popular research topics in Distributed Measurement and Control Systems (DMCSs). In most industrial fields, such as Smart Grid and Flight Test, the highest requirement for synchronization accuracy is 1 μs. IEEE 1588 Precision Time Protocol-2008 (PTPv2) can theoretically achieve sub-microsecond accuracy, but it relies on the assumption that the forward and backward delays of PTP packets are symmetrical. In practice, PTP packets will experience random queue delays in switches, making the above assumption challenging to satisfy and causing poor synchronization accuracy. Although using switches supporting the Transparent Clock (TC) can improve synchronization accuracy, these dedicated switches are generally expensive. This paper designs a PTP clock servo for compensating Queue-Induced Delay Asymmetry (QIDA), which can be implemented based on ordinary switches. Its main algorithm comprises a minimum window filter with drift compensation and a fuzzy proportional-integral (PI) controller. We construct a low-cost hardware platform (the cost of each node is within USD 10) to test the performance of the clock servo. In a 100 Mbps network with background (BG) traffic of less than 70 Mbps, the maximum absolute time error (max |TE|) does not exceed 0.35 μs, and the convergence time is about half a minute. The accuracy is improved hundreds of times compared with other existing clock servos.

Assessment of IEEE 1588-Based Timing System of the ITER Neutral Beam Test Facility

MITICA is one of the two ongoing experiments at the ITER Neutral Beam Test Facility (NBTF) located in Padova (Italy). MITICA aims to develop the full-size neutral beam injector of ITER and, as such, its Control and Data Acquisition System will adhere to ITER CODAC directives. In particular, its timing system will be based on the IEEE1588 PTPv2 protocol and it will use the ITER Time Communication Network (TCN) on a dedicated Ethernet LAN. Following the ITER device catalog, the National Instruments PXI-6683H PTP timing modules will be used to generate triggers and clocks synchronized with a PTP grandmaster clock. The “Lazy Trigger" technique, then, will be adopted to implement event-driven data acquisition without the need of any hardware link in addition to the Ethernet connections used to transfer data and timing synchronization. To evaluate the accuracy over time that can be achieved with different network topologies and configurations, a test system has been set-up consisting of a grand master clock, two PXI-6683H devices and two PTP aware network switches. In addition, a detailed simulation of the network and the involved devices has been performed using the OMNET++ discrete event simulator. The simulation parameters include not only the network and switches configuration, but also the PID parameters used in the clock servo controllers. A comparison between simulated and measured statistics is reported, together with a discussion on the possible optimal configuration strategies.

Subnanosecond Time Synchronization Using a 100Base-TX Ethernet Transceiver and an Optimized PI-Clock Servo

This work presents a real-time 100Base-TX Ethernet physical layer (PHY) transceiver chip implemented in a 180-nm technology. The PHY chip implements highly accurate hardware timestamping by using an 8-bit digital-to-phase converter (DPC) generating 256 phases of the 125 MHz system clock. Using these clock phases, spaced 31.25 ps apart from each other, phase relationships can be evaluated to timestamp ingress and egress frames with improved resolution. Connected by up to 120-m-long category five unshielded twisted-pair cables, two of these PHY chips are used to demonstrate the synchronization in a two-node scenario. A proportional-integral (PI)-clock servo is used at the slave for the synchronization. To optimize the performance, the parameters of the controller need to be chosen carefully. To do so, a simple model is used to find a suitable bandwidth of the controller as a tradeoff between the noise of the timestamping and the noise of the oscillator. All in all, a synchronization accuracy with a standard deviation of only 64 ps and a mean offset of well below 100 ps is achieved in the given scenario. To the best of our knowledge, this is the highest synchronization accuracy over copper-based Ethernet reported to date.

An Adaptive Fuzzy-PI Clock Servo Based on IEEE 1588 for Improving Time Synchronization Over Ethernet Networks

A network-based control system includes many connected devices, and time synchronization plays an important role in the unified operation of those systems. A clock servo needs a guarantee time offset and a clock rate to minimize the time difference between devices. This paper proposes an adaptive clock servo to improve time synchronization. This proposed algorithm uses a fuzzy-based proportional-integral clock servo (fuzzy-PI) based on IEEE 1588 to reduce the frequency of clock compensation. This method adapts the bandwidth and enhances noise reduction, improving both the time offset and rate difference between the slave and master. The node time can synchronize with the master time after just one cycle of synchronization. Experiments validated the effectiveness of the algorithm and demonstrated that the slave can track the master with the mean and standard deviation of the time offset are 0.432ns and 4.402ns. A cycle time of one second is used to ensure a low-bandwidth network. With these results, the number of nodes over a real-time network can be increased.

Feasibility of Time-Synchronization Attacks Against PMU-Based State Estimation

The emerging measurement technology of phasor measurement units (PMUs) makes it possible to estimate the state of electrical grids in real time, thus opening the way to new protection and control applications. PMUs rely on precise time synchronization; therefore, they are vulnerable to time-synchronization attacks (TSAs), which alter the measured voltage and current phases. In particular, undetectable TSAs pose a significant threat as they lead to an incorrect but credible estimate of the system state. Prior work has shown that such attacks exist against pairs of PMUs, but they do not take into consideration the clock adjustment performed by the clock servo, which can modify the attack angles and make the attacks detectable. This cannot be easily addressed with the existing attacks, as the undetectable angle values form a discrete set and cannot be continuously adjusted as would be required to address the problems posed to the attacker by the clock servo. Going beyond prior work, this article first shows how to perform undetectable attacks against more than two PMUs, so that the set of undetectable attacks forms a continuum and supports small adjustments. Second, it shows how an attacker can anticipate the operation of the clock servo while achieving her attack goal and remaining undetectable. Third, this article shows how to identify vulnerable sets of PMUs. Numerical results on the 39-bus IEEE benchmark system illustrate the feasibility of the proposed attack strategies.

Frequency-Tracking Clock Servo for Time Synchronization in Networked Motion Control Systems

With the application of internet in manufacturing, motion control system is tend to networking. Clock synchronization is a basic requirement to guarantee capability of coordination in networked motion control systems. In this paper, we propose a frequency-tracking clock servo (FTCS) to adjust the local clock to synchronize with the reference clock. The frequency of FTCS can rapidly lock onto the reference frequency and the offset can be fully compensated within a single synchronizing cycle. Simulations and experiments are performed to validate the feasibility and superiority of FTCS. Compared with the proportional-integral clock servo, FTCS can achieve the rapid synchronized speed and better precision with low frequency of sending synchronization messages.

A New Design of Clock Synchronization Algorithm

The introduction of Ethernet makes the distributed network system more flexible and efficient, but it also makes nodes which are far apart from each other unable to work in the same time basis due to the long distance. This is not allowed for the high performance requirements of the system synchronization, such as high-precision multiaxis machining system. This paper presents a high-precision network clock synchronization algorithm, namely, optimal PI clock servo, which imposes a PI controller in order to compensate for the clock drift of each network node. Then a simulation platform established by the toolbox TrueTime is used to verify the stability of the algorithm and compare it with the clock synchronization algorithm of EtherCAT. The results show that the new synchronization algorithm has higher synchronization precision and faster convergence rate.

A servo design for slave clock in IEEE 1588 synchronization networks

SummaryClock synchronization is critical for a variety of applications in communication networks. In this paper, we design a clock servo named VI_PID‐K, which consists of a variable integral PID controller and a Kalman filter. It is a pre‐correction mechanism for the skew based on feedback principle to compensate for the poor stability of local clocks in IEEE 1588 networks. Our contribution is establishing discrete differential equation models, bringing in a variable integral PID controller to adjust the skew error and a Kalman filter to act as a skew estimator to predict the skew during one synchronization interval. Simulation results demonstrate that VI_PID‐K provides a more stable disciplined clock, improves the speed of skew convergence, and reduces Allan variance in a large time scale when compared to PI method or Fixed_Integral method.VI_PID‐K can improve the stability of slave clock and reduce the frequency that master clock sends Sync messages, so the network overhead for clock synchronization can be reduced. Copyright © 2013 John Wiley & Sons, Ltd.

A New Time Synchronization Method for Reducing Quantization Error Accumulation Over Real-Time Networks: Theory and Experiments

In real-time network-based systems with long linear paths, the growth rate of time synchronization error is the major barrier to the scalability of systems even if a transparent clock mechanism of IEEE 1588 is used. This paper is devoted to designing a new time synchronization method for such systems. In the proposed algorithm, a proportional-integral (PI) clock servo is used to achieve the frequency compensation. In order to reduce the growth rate of synchronization error due to the quantization error in timestamping, a Kalman filter is designed based on a state-variable model, which is built for the PI controller-tuned slave clock. In addition, the quantization effect is analyzed and the variance of quantization error is quantitatively estimated for each slave node. Experiments are performed to validate its effectiveness and demonstrate that the peak-to-peak jitter is measured to be only 59.37 ns after four hops, and the growth rate of synchronization error can also be significantly reduced by the presented synchronization method. This indicates that the maximum number of networked nodes can be correspondingly increased.

Performance Analysis of Kalman-Filter-Based Clock Synchronization in IEEE 1588 Networks

Performances in network-based synchronization depend on several related factors, including the instability of local clocks, the rate at which timing information is exchanged, and the accuracy of the resulting correction estimates. This paper analyzes these effects and their relationships, showing how these may affect the design of an IEEE 1588 Precision Time Protocol synchronization scheme. This paper introduces a state-variable clock model for which realistic parameters can be obtained for different kinds of clocks from experimental measurements of Allan variance plots. A Kalman-filter-based clock servo employing this model is developed, and a simulation analysis of the behavior of clock regulation and the effect of parameter variations on its performances is presented.

Low-noise electronic design for the /sup 87/Rb coherent population trapping maser

In this paper we present the low-noise electronics for a prototype of rubidium maser based on the coherent population trapping (CPT) phenomenon. After an overview of the general architecture, we will focus our description on the main blocks of the equipment we implemented: the microwave synthesis chain, the detection apparatus, the clock servo system and the electronics devoted to control the laser and the temperature. For each part, we present the design, the implementation, and the characterization measurements we performed. The contribution to the CPT maser frequency stability of each part also has been evaluated, and the frequency stability of the clock is reported.

Corrections for Second-Order Doppler Shift and Cavity Phase Error in Cesium Atomic Beam Frequency Standards

From the measured static resonance curve of a cesium beam tube, corrections can be derived for second-order Doppler shift and cavity phase error. For the calculation Fourier transforms are used, which also produce the velocity distribution of the atoms. Data are given for the distortion of the resonance curve from which the corrections can be derived applicable in the case of very slow square wave frequency modulation. A method is also given for calculating corrections for faster modulation rates where the time-of-flight effects are no longer negligible. However, quadrature components will now occur in the beam signal, and their effect on the clock servo is discussed.