Clock Power Research Articles

State‐of‐the‐Art 3DES Pipelined Cryptographic Engine Design Against Side‐Channel Attacks

ABSTRACTIn this paper, a high‐speed, low‐latency, and high‐security hardware‐implemented triple data encryption standard (3DES) cryptographic algorithm is proposed for securing data privacy. In order to achieve a high throughput for the 3DES architecture, the whole circuit is optimized with a 24‐stage pipelined design at first. For breaking the correlation between the processed data and power dissipation of the 3DES circuit against differential power analysis (DPA) attacks, two pseudo‐random number generators (PRNGs) are embedded to randomly alter the number of pipelined stages and data substitution locations within the 3DES circuit, respectively. Under such a circumstance, the proposed 3DES circuit is able to achieve high performance and strong robustness against DPA attacks without causing much overhead. As shown in the results, under the synthesis of SMIC 14‐nm process design kits (PDK), the clock frequency, area, power dissipation, and throughput of the proposed 3DES circuit, respectively, are achieved as 1.2 GHz, 26,435 m2, 21.05 mW, and 64 Gbps. Furthermore, when DPA attacks are executed on the proposed 3DES circuit, the corresponding secret key cannot be revealed even if 2 million plaintexts are enabled. In contrast, only 40,000 plaintexts are adequate to disclose the secret key of a regular pipelined 3DES circuit.

PHOTONIC INTEGRATED CIRCUITS: GIANT LEAP IN COMPUTING TECHNOLOGY

There is a continued demand for increase in computing requirements from sensor, smartphones, to servers. However, the technology improvements in clock speed, power, and memory bandwidth from traditional electronic integrated circuits (EIC) has started to saturate. This has triggered further research in exploration of photon integrated circuits (PIC) that utilize photons (or particles of light) as opposed to electrons to form a functioning circuit. Research suggests that by integrating the benefits of EIC and PIC, one is able to harness the best of both worlds. The inherent advantages of photonics technology such as speed, energy-efficiency, and density, coupled with the advances in material technology, make them suitable to address the challenge of designing heterogeneous chips. This paper presents the fundamentals of the photonic technology, applicability to solving digital computing problems, ability to integrate into PICs, and its capability to complement electronic integrated circuits for powering the computing demands of emerging applications.

A power-efficient, single-phase, contention-free flip-flop with only three clock transistors

Flip-flop research in recent years has been motivated by power- and/or energy-efficient designs. Flip-flop power is based on data activity (DA), which in many applications ranges from 5 to 15%. In such cases, a substantial amount of clock power and energy is wasted. In this paper, a power-efficient, contention-free flip-flop with only three single-phase clock transistors is proposed, which has low-power consumption and eliminates unnecessary internal transitions in the circuit. This flip-flop is referred as 3CTSPC. Test-chip measurement results show that at VDD = 1 V, CK = 25 MHz, and DA = 12.5%, 3CTSPC is 11% and 58% more power-efficient than 18TSPC and TGFF, respectively.

Optimized power and speed of Split-Radix, Radix-4 and Radix-2 FFT structures

Fast Fourier transform (FFT) is a fundamental building block for digital signal processing applications where high processing speed is crucial. Resource utilization in implementing FFT structures can be minimized by optimizing the performance of multipliers and adders used within the design. FFTs are also widely used in various machine learning algorithms. To achieve increased processor efficiency and reduced resource utilization, we propose a hardware design for Radix-2, Radix-4, and Split-Radix FFT architectures that utilizes a novel parallel prefix adder. This design offers lower power consumption, smaller chip area, and faster operation compared to existing architectures. Our performance analysis focuses on metrics such as power consumption, clock speed, and hardware complexity for Radix-2, Radix-4, and Split-Radix FFT algorithms implemented with the proposed adder. We compare these metrics using our proposed arithmetic structure against existing adder designs. The results indicate that the Split-Radix FFT architecture achieves lower power consumption and smaller chip area compared to Radix-4 and Radix-2 methods. Additionally, the Split-Radix FFT exhibits a higher clock speed. Therefore, based on these findings, the Split-Radix algorithm appears to be a compelling choice for implementation on field-programmable gate arrays due to its high speed and lower power consumption.

Gate all around carbon nanotube field effect transistor espoused discrepancy cascode pass transistor adiabatic logic for ultra-low power application

Advances in wearable technology, IoT, and mobile applications have increased the demand for ultra-low-power electronic devices. Adiabatic Logic Circuit (ALC) is a design technique utilized in digital circuits to decrease the power consumption by decreasing the dynamic power dissipation. Current technologies face challenges in achieving both high performance and ultra-low power consumption. This research work introduces a novel approach in digital circuit design, specifically the Gate All-around Carbon Nanotube Field Effect Transistor with Discrepancy Cascode Pass Transistor Adiabatic Logic (GAA-CNTFET-DCPTAL), tailored for ultra-low power applications. This design operates efficiently with a four-phase Power Clock (PC) and demonstrates remarkable performance by achieving operation frequencies of up to 1 GHz while minimizing energy dissipation. GAA-CNTFET provides superior electrostatic control and high carrier mobility, reducing leakage currents and enhancing switching speeds. Simultaneously, Discrepancy Cascode Pass Transistor Adiabatic Logic (DCPTAL) uses adiabatic logic principles and a cascode structure to minimize energy dissipation during switching events. The technology node of proposed model is 10 nm. The software used for assessment is HSPICE is used for the simulation and validation of the proposed design. The proposed GAA-design attains 25.36 %, 14.28 %, and 16.06 % lower average power analyzed with existing techniques, such as Design with Evaluation of Clocked Differential Adiabatic Logic Families for the applications of low Power (DE-CDAL-LPA), Adiabatic logic-base strong ARM comparator for ultra-low power applications (AL-SARM-ULPA) and Analysis of 2PADCL Energy Recovery Logic for Ultra Low Power VLSI Design for SOC with Embedded Applications (2PADCL-ULP-VLSI) respectively.

Molten salt-mediated hierarchical porous carbon derived from biomass waste for high-performance capacitive storage

Biomass-derived carbon (BDC) materials are the suitable precursors for the fabrication of carbon electrodes of supercapacitors because of the sustainability, environmental friendliness, power capability, and structural diversity. The fabrication of BDC with low cost and excellent electrochemical properties is important for the practical applications of BDC in energy storage fields. Herein, ambrosia melon peels are used as carbon precursors for the fabrication of sustainable BDC electrodes through the molten salt-mediated pyrolysis procedure. The ambrosia melon peels-derived porous carbon (AMPPC) possesses high specific surface area of 529.9 m2 g−1. The AMPPC electrode shows the charge storage behavior of electrical double-layer capacitance with high ionic conductivity, high specific capacitance (218.3 F g−1 at 0.5 A g−1) and outstanding rate performance. In addition, the symmetric supercapacitor based on the AMPPC electrodes presents high specific energy density and specific power density (8 kW kg−1). It can be used as energy source to power helicopter model, clock, and calculator. Thus, the work gives an inspiration of design of BDC from the low-cost biomass waste and provides a simple way for the fabrication of BDC for the carbon electrodes of supercapacitors, lithium-ion batteries and so on.

P‐73: Gate Driver Circuit to generating Multi‐Frequency Pulses using LTPO Technology

This paper proposes a gate driver circuit for the implementation of multi‐region and multi‐refresh rates. A distinctive feature of this proposed circuit is the integration of a separate control block into the existing gate driver circuit. Another is the utilization of CMOS (a combination of n‐type IGZO and p‐type LTPS) to enhance circuit reliability and reduce power consumption. This gate driver circuit can be applied to an LTPO based pixel circuit which can be using with a variable refresh rate and implemented multi‐zone and multi‐refresh rates. Through circuit simulations, the paper verifies the successful operation of multi‐refresh rates based on control signals and establishes a reduction in clock power consumption. Consequently, the proposed gate driver circuit stands as a solution for achieving high resolution and low power consumption in displays.

Design and Implementation of Low Power and High Data Rate Edge Coded Signaling Architecture for IoT Devices

Abstract Edge coded signaling (ECS) is a recently introduced communication protocol designed for single-channel signaling among constrained internet of things (IoT) nodes. This study aims to enhance the data rate of ECS, without increasing the clock frequency or power consumption. The goal is to develop an improved protocol that maintains the inherent advantages of ECS while achieving a higher data rate. The proposed solution, double data rate ECS (DDR-ECS), leverages both pulse edges of the ECS pulse stream for information encoding, drawing an analogy to DDR memory systems. The study presents a detailed design of low-power architecture for the DDR-ECS transceiver. This design was synthesized using a 65 nm ASIC process to evaluate its performance in terms of power consumption, gate count, and data rate. The synthesis results demonstrate that the DDR-ECS transceiver preserves the key features of ECS, including tolerance to clock frequency variations and compatibility with lightweight cryptographic algorithms. It effectively doubles the dynamic data rate to the range of 12–73.5 Mb/s while consuming an equivalent power of 13 μW and occupying a compact form factor of only 1,755 gates. The introduction of DDR-ECS represents a significant advancement in the ECS protocol, offering a novel approach to doubling the data rate without increasing the clock frequency or power envelope. This innovation retains the simplicity and efficiency of ECS, providing an enhanced communication solution for constrained IoT nodes.

Decelerated Epigenetic Aging in Long Livers

Epigenetic aging is a hot topic in the field of aging research. The present study estimated epigenetic age in long-lived individuals, who are currently actively being studied worldwide as an example of successful aging due to their longevity. We used Bekaert’s blood-based age prediction model to estimate the epigenetic age of 50 conditionally “healthy” and 45 frail long-livers over 90 years old. Frailty assessment in long-livers was conducted using the Frailty Index. The control group was composed of 32 healthy individuals aged 20–60 years. The DNA methylation status of 4 CpG sites (ASPA CpG1, PDE4C CpG1, ELOVL2 CpG6, and EDARADD CpG1) included in the epigenetic clock was assessed through pyrosequencing. According to the model calculations, the epigenetic age of long-livers was significantly lower than their chronological age (on average by 21 years) compared with data from the group of people aged 20 to 60 years. This suggests a slowing of epigenetic and potentially biological aging in long livers. At the same time, the obtained results showed no statistically significant differences in delta age (difference between the predicted and chronological age) between “healthy” long livers and long livers with frailty. We also failed to detect sex differences in epigenetic age either in the group of long livers or in the control group. It is possible that the predictive power of epigenetic clocks based on a small number of CpG sites is insufficient to detect such differences. Nevertheless, this study underscores the need for further research on the epigenetic status of centenarians to gain a deeper understanding of the factors contributing to delayed aging in this population.

Adiabatic Power Management Techniques for Metal Oxide Silicon Field Effect Transistors in Digital Logic Circuits

Metal Oxide Silicon Field Effect Transistors are foundational components in electronics, mainly digital logic circuits. Effective power management in MOSFET-based logic circuits becomes more crucial as technology expands to sub-100-nanometer nodes. Four optimization techniques to reduce power losses during switching transitions are carefully examined in this article. With the first method, QSSERL, no additional timing control clocks are required, which results in significant energy savings, especially in high-frequency applications. In the second method, DFAL, split-level sinusoidal power clocks are used instead of diodes, significantly lowering voltage differentials and power dissipation. Building on DFAL, IDFAL employs control transistors to reduce leakage power, significantly lowering power dissipation and facilitating charge recovery. Lastly, FSOA, inspired by natural species' collective behaviour, enhances key components within MOSFET-based circuits. This paper examines numerous adiabatic logic topics. Developing energy-efficient MOSFET-based logic circuits is essential for improving electronics and satisfying the growing demand for energy-conscious technologies.

A robust low-power fsm cordic lms filter design for exponential noise removal in pacemaker

ABSTRACT Heart disease is identified to be the major reason for death worldwide as recorded by World Health Organization. The use of cardiac pacemakers was estimated to be around 1.14 million in the year 2016 and is expected to increase to 1.43 million by the year 2023. Based on the frequency of usage, the lifetime of a pacemaker can last between 6 to 10 years. To prolong the lifetime of the pacemaker, a low-power filter design is presented. The pulse that comes out of the pacemaker has exponential noise and myo-potential noise. The least mean square (LMS) filter with Co-ordinate Rotation Digital Computer (CORDIC) filters the exponential noise signal and retrieves the desired pace pulse. The CORDIC architecture used here is realised using FSM computational technique, because FSM offers a simple hardware circuitry. Digital circuits highly rely on clock signal to track the time and execution of functions that are programmed. This irreplaceable signal requires a control module that would make it more efficient and audacious. This is the prime reason for the evolution of clock gating technique. Similarly, the leakage power caused by the power source also requires attention. With the boom of deep submicron technologies, leakage power has started to occupy 30–50% of the total power consumption. Power gating technique helps to resolve this issue significantly. In this proposed method, integrated coarse-grained power and clock gating technique is employed to reduce the power dissipation of the LMS filter. A comparative study of Latch-, AND- and OR-based clock gating with forced transistor stacking and sleep transistor whose width and length are doubled from the rest of the complementary metal oxide semiconductors is also performed. The design is implemented using 250 nm CMOS technology. The implementation of clock gating technique has resulted in a 41.35% average reduction in dynamic clock power dissipation. The power gating technique has resulted in 26.08% reduction in static input power dissipation. The total power savings on integration of clock and power gating techniques are found to be 36.95% from the non-gated CORDIC LMS filter design.

A Novel Simulation Approach for Fault Injection Mechanism Assessing Dependability of Cybersecurity Attacks

Clock attacks and power attacks are used as common means to inject faults in embedded devices. Critical analysis of the properties and the components engaged with these fault injection methods is of high importance to assess the related dangers and furthermore to enhance the process of designing suitable counter-measures. This paper provides critical analysis of induced faults on combinational and sequential circuits and study effects of various attacks (over-clock, under clock, power attack). While doing analysis, it was revealed that clock attacks i.e., under and over clock attacks have similarity index of (80–90%). Also it was found that power attacks have results similar (60–70%) to clock attacks but they cause propagation delay in circuits affecting the output. Cadence virtuoso 45 nm technology node, Keil and Multi-sim software’s were used to generate various attacks. The comparative analysis reveals that the attack timing and frequency of the glitch is the key while inducing fault injection attacks. While performing this work, it is observed the sequential circuits get less impacted by attacks comparing to combinational circuits. This research is conducted from an attacker’s perspective instead of mitigation perspective.

Cross-Mesh Clock Network Synthesis

In the clock network design, the trade-off between power consumption and timing closure is an important and difficult issue. The clock tree architecture has a shorter wire length and better power consumption, but it is more difficult to achieve timing closure with it. On the other hand, clock mesh architecture is easier to satisfy the clock skew constraint, but it usually has much more power consumption. Therefore, a hybrid clock network architecture that combines both the clock tree and clock mesh seems to be a promising solution. In a normal hybrid mesh/tree structure, a driving buffer is placed in the intersection of mesh lines. In this paper, we propose a novel cross-mesh architecture, and we distribute the buffers to balance the overall switching capacitance, reducing the number of registers connected to a subtree, and the load capacitance of a buffer. With the average dispersion of the overall driving force, our methodology creates small non-zero skew clock trees. In addition, we integrate clock gating, register clustering, and load balancing techniques to optimize clock skew and load capacitance simultaneously. The proposed methodology has four stages: cross-mesh planning, register clustering, mesh line connecting, and load balancing. Experimental results show that our cross-mesh architecture has high tolerance for process variation, and is robust in all the operation modes. Comparing it to the uniform mesh architecture, our methodology and algorithms reduce 28.9% of load capacitance and 80.4% of clock skew on average. Compared to the non-uniform mesh architecture, we also reduce capacitance by 22.4% and skew by 76.7% on average. This illustrates that we can obtain a feasible solution effectively and improve both power consumption and clock skew simultaneously.

Superconducting pulse conserving logic and Josephson-SRAM

Superconducting digital pulse-conserving logic and Josephson static random access memory (JSRAM) memory together enable scalable circuits with energy efficiency 100× beyond leading-node CMOS. Circuit designs support high throughput and low latency when implemented in an advanced fabrication stack with high-critical-current-density Josephson junctions of 1000 μA/μm2. Pulse-conserving logic produces one single-flux-quantum output for each input and includes a three-input, three-output gate producing logical or3, majority3, and and3. Gate macros using dual-rail data encoding eliminate inversion latency and produce efficient implementations of all standard logic functions. A full adder using 70 Josephson junctions has a carry-out latency of 5 ps corresponding to an effective 12 levels of logic at 30 GHz. JSRAM memory uses single-flux-quantum signals throughout an active array to achieve throughput at the same clock rate as the logic. The unit cell has eight Josephson junctions, a signal propagation latency of 1 ps, and a footprint of 2 μm2. Projected density of JSRAM is 4 MB/cm2, and computational density of pulse-conserving logic is on par with leading node CMOS accounting for power densities and clock rates.

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Today, the current buffered router Synchronous Network on Chip architecture consumes significant chip area and power. Therefore, based on biased routing, buffer-less routers have recently been predicted as a possible solution, but they suffer from contiguous port assignments, slow critical paths, and increased latency. Asynchronous Network on Chip architecture emerges as the best option for avoiding glitches and consuming less power. A clock and data recovery circuit is used to recover the clock signal from the router-generated data and reduce power consumption in a Multiprocessor System on Chip. This paper proposes a clock and data recovery circuit design for an asynchronous Network on Chip. The proposed 4x4 Mesh router architecture implemented in this paper can process 64-bit of data samples with a depth of 64. When comparing the proposed architecture with the existing NoC architecture, the proposed architecture has shown a power reduction of 5times. The proposed architecture has consumed a total power of 0.103W.

Epigenetic clocks provide clues to the mystery of uterine ageing.

Rising maternal ages and age-related fertility decline are a global challenge for modern reproductive medicine. Clinicians and researchers pay specific attention to ovarian ageing and hormonal insufficiency in this regard. However, uterine ageing is often left out of the picture, with the majority of reproductive clinicians being close to unanimous on the absence of age-related functional decline in the uterine tissues. Therefore, most existing techniques to treat an age-related decline in implantation rates are based primarily on hormonal supplementation and oocyte donation. Solving the issue of uterine ageing might lead to an adjustment to these methods. A focus on uterine ageing and the possibility of slowing it emerged with the development of the information theory of ageing, which identifies genomic instability and erosion of the epigenetic landscape as important drivers of age-related decline in the functionality of most cells and tissues. Age-related smoothing of this landscape and a decline in tissue function can be assessed by measuring the ticking of epigenetic clocks. Within this review, we explore whether the uterus experiences age-related alterations using this elegant approach. We analyse existing data on epigenetic clocks in the endometrium, highlight approaches to improve the accuracy of the clocks in this cycling tissue, speculate on the endometrial pathologies whose progression might be predicted by the altered speed of epigenetic clocks and discuss the possibilities of slowing down the ticking of these clocks. Data for this review were identified by searches of Medline, PubMed and Google Scholar. References from relevant articles using the search terms 'ageing', 'maternal age', 'female reproduction', 'uterus', 'endometrium', 'implantation', 'decidualization', 'epigenetic clock', 'biological age', 'DNA methylation', 'fertility' and 'infertility' were selected. A total of 95 articles published in English between 1985 and 2022 were included, six of which describe the use of the epigenetic clock to evaluate uterine/endometrium ageing. Application of the Horvath and DNAm PhenoAge epigenetic clocks demonstrated a poor correlation with chronological age in the endometrium. Several approaches were suggested to enhance the predictive power of epigenetic clocks for the endometrium. The first was to increase the number of samples in the training dataset, as for the Zang clock, or to use more sophisticated clock-building algorithms, as for the AltumAge clock. The second method is to adjust the clocks according to the dynamic nature of the endometrium. Using either approach revealed a strong correlation with chronological age in the endometrium, providing solid evidence for age-related functional decline in this tissue. Furthermore, age acceleration/deceleration, as estimated by epigenetic clocks, might be a promising tool to predict or to gain insights into the origin of various endometrial pathologies, including recurrent implantation failure, cancer and endometriosis. Finally, there are several strategies to slow down or even reverse epigenetic clocks that might be applied to reduce the risk of age-related uterine impairments. The uterine factor should be considered, along with ovarian issues, to correct for the decline in female fertility with age. Epigenetic clocks can be tested to gain a deeper understanding of various endometrial disorders.

Low Power ALU using Wave Shaping Diode Adiabatic Logic

The evolution of portable electronic devices and their widespread application has led to an increased focus on power dissipation as one of the critical parameters. An increase in functionality requirement and design complexity on a single chip has resulted in increased power dissipation. High power dissipation has motivated study and innovation on low power circuit design techniques. Adiabatic logic has been studied as one of the design techniques to reduce power dissipation by reusing the power that was getting dissipated in conventional designs. This paper presents the application of Wave Shaping Diode Adiabatic Logic (WSDAL) to implement an ALU and analyse the improvement in power dissipation as compared to the conventional CMOS design. The WSDAL design uses a slow and time-fluctuating 2-phase sinusoidal Power Clock (PC), which supplies power as well as a clock to the designs. WSDAL uses an Ultra-Low Power Diode (ULPD) structure that operates as a wave shaping device and reduces glitches at the output. The design has been implemented in OrCAD Capture and simulated using Pspice in TSMC 180nm technology. The simulations were performed at 200MHz PC frequency and power dissipation was studied over a range of voltages from 1.4V to 2.2V. The simulations show that WSDAL ALU dissipates less power than the CMOS design. This study indicates that WSDAL-based designs have the potential to be deployed for power dissipation reduction in portable devices.

A Clock Tree Prediction and Optimization Framework Using Generative Adversarial Learning

Modern physical design flows highly depend on design space exploration to find the commercial tools’ clock tree synthesis (CTS) parameters that lead to optimized clock trees. However, such exploration is often time-consuming and computationally inefficient. In this article, we overcome this drawback by proposing a novel framework named GAN-CTS, which utilizes conditional generative adversarial network (GAN) to predict and optimize CTS outcomes. Our framework is built upon three sequential learning stages. First, to precisely characterize distinct designs, we leverage transfer learning to extract netlist features directly from placement images. Second, we perform regression learning using various methods to predict the target CTS outcomes and demonstrate that the proposed multitask learning approach achieves better accuracy than the meta-modeling method adopted by previous works. To fully benefit from the predictions made by our framework, we further quantitatively interpret the importance of each CTS input parameter subject to various design objectives through attribution-based learning. Finally, generative adversarial learning is leveraged to optimize the target clock metrics with the guidance provided by the pretrained regression model. To substantiate the generality of our framework, we perform validations on four unseen netlists that are not utilized in the training process. The experimental results conducted on real-world designs demonstrate that our framework: 1) achieves an average prediction error of 3%; 2) improves the commercial tool’s auto-generated clock tree by 20.7% in clock power, 21.5% in clock wirelength, 36.1% in the worst skew; and 3) reaches an F1-score of 0.93 in the classification task of determining successful and failed CTS runs.

A 40-nm Low-Power WiFi SoC With Clock Gating and Power Management Strategy

ABSTRACT With the emerging of Internet of Things (IoT) industry, applications like smart power plugs, security ID tags, home automation and wearable electronic devices all make the demand for low-power WiFi chips impendency. In this paper, a low-power 2.4 GHz 802.11b/g/n WiFi system-on-chip (SoC) is designed and implemented with 40-nm CMOS process, with area of 8.1 mm2. The low-power SoC integrates 32-bit microcontroller, 802.11b/g/n WiFi baseband, 2.4 GHz RF transceiver, ample memory space, ADC, 6-channel PWM, flexible I/O interfaces, multi-stage power management module, etc.. It has several sleep modes with extremely low leakage current as 0.8 mA/12 µA in light/deep sleep mode and 0.4 µA in Shutdown mode to reduce the power consumption. High performance is demonstrated, including Pout (-28 dB/-30 dB EVM) of 20.1 dBm/19.1 dBm and RX sensitivity of -76 dBm/-74 dBm meanwhile the total current of 148.5 mA/146.5 mA (TX) for 54 Mbps OFDM/HT20 MCS7.

Design and implementation of power efficient clock gated dual-port SRAM

Synchronous clock gated Dual-port RAM has been designed in this paper. To increase the design’s power, a negative latch-based clock gating approach was used. On Xilinx Vivado ML Edition, the design was implemented on an XC7Z010ICLG225-1L device with a - 1-speed grade and the Zynq-7000 FPGA family. The Verilog HDL was used to create the design. A 2-bit AND gate is used to realize clock gating which takes the clock and enable signal as input thus clock become only high when enable is high which reduces the switching frequency and thus power consumption by the clock is reduced as power is directly proportional to (frequency)2. Apart from clock gating, the SRAM is Dual-Port based, allowing multiple reads or writes to occur simultaneously, or at approximately the same time, unlike single-port RAM, which permits only one access at a given time. The power consumption value of the clock signal with clock gating at 100 GHz is 627.61 mW as compared to power consumption without clock gating which is 1405 mW, at a clock frequency of 100 GHz, a 55 percent reduction in total clock power was achieved. Xilinx Vivado ML Edition’s XPower Analyzer tool was used to calculate the device’s power.