Minimum Clock Period Research Articles

Real-time Blood Pressure Prediction on Wearable Devices using Edge Based Deep Neural Networks: A Hardware-software Co-design Approach

This paper presents the hardware realization of a real-time blood pressure (BP) prediction model for wearable devices, utilizing long short-term memory (LSTM) deep neural networks (DNNs). The proposed system uses both electrocardiogram (ECG) and photoplethysmogram (PPG) signal values for BP prediction. It aims to address the limitations of traditional BP measurement methods, providing a low error, minimal computational overhead, more accurate and convenient alternative system for individuals with hypertension or at risk for cardiovascular diseases. The utilization of split matrix approach leads to a reduction in hardware complexity across the entire system. This technique involves breaking down the larger weight matrices used in the computations of DNNs into smaller matrices. This fragmentation results in a decrease in the complexity of the hardware responsible for performing matrix vector multiplications (MVMs) within LSTMs. The resultant architecture of the predictive model gains several advantages, including a lowered level of complexity in terms of the space occupied by individual cells, decreased processing delay, and reduced power consumption. Furthermore, this approach enables the achievement of a notably improved minimum achievable clock period of 2.972 ns. This prediction model can operate locally on wearable devices, reducing the reliance on cloud computing and improving privacy and security. The performance evaluations are carried out using both analytical and implementation results. The results indicate that the proposed model can be practically applied to real-world problems and can potentially enhance the accuracy of various machine-learning tasks.

Performance Enhancement Counter with Minimal Clock Period

A synchronous binary counter is a fundamental component in VLSI design which are used commonly. synchronous binary counter is fast and are used in many applications as it supports wide bit-width. Due to large fan-outs and long carry chains many previous counters have low counting rate when the size of the counters is large. A new fast structure has been suggested for synchronous binary counter with a very low delay for counter with size ranging from 8 to 128 bits. To reduce the complexity of hardware a 1-bit Johnson counter has been used and then duplicate it to minimise propagation delay induced by large fan-outs. The suggested design is realised with a small number of flip-flops, using a back carry propagation counter and a counter based on state look ahead logic, which reduces power and delay.

Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM

Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories. Recently, system-on-chips (SOCs) have been developed in nanotechnology, with most of the chip area occupied by memories. Generally, memories in SOCs contain various sizes with poor accessibility. Thus, it is not easy to repair these memories with the conventional external equipment test method. For this reason, memory designers commonly use the redundancy method for replacing rows–columns with spare ones mainly to improve the yield of the memories. In this manuscript, the Deep Q-learning (DQL) with Bit-Swapping-based linear feedback shift register (BSLFSR) for Fault Detection (DQL-BSLFSR-FD) is proposed for Static Random Access Memory (SRAM). The proposed Deep Q-learning-based memory built-in self-test (MBIST) is used to check the memory array unit for faults. The faults are inserted into the memory using the Deep Q-learning fault injection process. The test patterns and faults injection are controlled during testing using different test cases. Subsequently, fault memory is repaired after inserting faults in the memory cell using the Bit-Swapping-based linear feedback shift register (BSLFSR) based Built-In Self-Repair (BISR) model. The BSLFSR model performs redundancy analysis that detects faulty cells, utilizing spare rows and columns instead of defective cells. The design and implementation of the proposed BIST and Built-In Self-Repair methods are developed on FPGA, and Verilog’s simulation is conducted. Therefore, the proposed DQL-BSLFSR-FD model simulation has attained 23.5%, 29.5% lower maximum operating frequency (minimum clock period), and 34.9%, 26.7% lower total power consumption than the existing approaches.

64 Bit Binary Counter with Minimal Clock Period

Novel rapid formations of synchronous binary counting with single minimum period of counting for practical counters are developed in this project. A synchronous binary counter is required in many applications since it is rapid, also can help a broad bit-width. Basically, because of massive fan-outs and extensive carry chains, earlier counters have a limited counting rate, mainly when size of the counter is not modest. It employs a single bit Johnson counter to decrease whole hardware complications, then copy it to lessen the propagation latency caused by huge fan-outs. In this paper, re programmable the clock utilized in it for various applications functioning at different clock rates and there’ll be a variation within the delay values because the clock is reprogrammed the critical may varies for various rates. The counter output results are obtained for various bit up to 64 and therefore the design provides various clock rates with variations in area and delay.

Constant-Time Synchronous Binary Counter With Minimal Clock Period

A synchronous binary counter is one of the basic components widely used in VLSI design, and it is required to be fast and support a wide bit-width in many applications. However, most of the previous counters are associated with a limited counting rate due to large fan-outs and long carry chains, especially when the counter size is not small. This brief proposes a new fast structure for synchronous binary counting, which has a minimal counting period for practical counter sizes ranging from 8 to 128 bits. We first adopt an 1-bit Johnson counter to reduce the overall hardware complexity, and then duplicate the 1-bit Johnson counter to decrease the propagation delay caused by large fan-outs. Implementation results show that the proposed design can be realized with a small number of flip-flops, which is almost linear to the counter size, and it operates at a clock frequency of 2GHz in a 65nm CMOS technology, being limited only by the counting rate of the least significant bit.

QSSTA: A Statistical Static Timing Analysis Tool for Superconducting Single-Flux-Quantum Circuits

Superconducting single flux quantum (SFQ) technology is an ultra-high performance and low power technology. The technology, however, lacks many of the design automation tools and capabilities that are commonplace in CMOS technology. This article describes methods to efficiently find the conditional probability density function (PDF) of the minimum workable clock period of SFQ circuits in view of manufacturing-induced process variations and presents qSSTA, a statistical static timing analysis tool targeting SFQ circuits. Following a grid-based correlation model, qSSTA represents spatial correlation of SFQ gates at different positions with respect to process parameters. By approximating timing characteristics of SFQ gates in a linear model, qSSTA is able to estimate the clock period as a normal random variable. Furthermore, process variations that generally result in extra delays in CMOS circuits can result in functional errors in SFQ circuits. qSSTA derives the closed form of the conditional PDF of the clock period under the scenario where all SFQ gates in the circuit work correctly. Compared to Monte Carlo simulations on look-up tables, experimental results show that the average percentage errors are 0.89% for the mean values, 8.04% for the standard deviation, and 0.61% for the 98-percentile point, whereas the runtime of qSSTA is 83% faster on average.

A Dedicated Greedy Short Path Padding Solution Method for Error Resilient Circuit Designs

Resilient circuits represent promising approaches for improving both circuit performance and tolerance for dynamic variations. However, the short path padding problem becomes severe during the implementation, resulting in significant area overhead and even frequency degradation, which might nullify the benefits of resilience. The present work addresses this issue by proposing a progressive resilient design methodology, including a clock period prediction method that can accurately access the minimum clock period possible in an early stage and a short path padding method, based on the greedy heuristic algorithm to reduce both the total padding delay and the runtime. The runtime for the padding stage is further minimized by introducing an accelerated padding method that decreases the number of point visits required during the greedy padding process. The proposed methodology is applied to several benchmark circuits, decreasing averagely 26.1% in the total number of padding buffers and 38.1% in the runtime, compared to a present state of the art methodology. Thus, this proposal not only avoids iterations of padding assignments by early period prediction, but also is a feasible and effective short path padding methodology for resilient circuits.

Hardware Optimized and Error Reduced Approximate Adder

This paper presents a new hardware optimized and error reduced approximate adder (HOERAA), which is suitable for field programmable gate array (FPGA)- and application specific integrated circuit (ASIC)-based implementations. In this work, we consider a FPGA-based implementation using Xilinx Vivado 2018.3, targeting an Artix-7 FPGA. The ASIC-based realizations are based on a 32/28nm complementary metal oxide semiconductor (CMOS) process. Based on FPGA implementations, we note the following: (i) For 32-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 22% fewer look-up tables (LUTs) and 18.6% fewer registers while reducing the minimum clock period by 7.1% and reducing the power-delay product (PDP) by 14.7%, compared to the native accurate FPGA adder, and (ii) for 64-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 11% fewer LUTs and 9.3% fewer registers while reducing the minimum clock period by 8.3% and reducing the PDP by 9.3%, compared to the native accurate FPGA adder. Based on ASIC-style implementations, HOERAA is found to achieve the following reductions in design metrics compared to an optimum accurate carry-lookahead adder: (i) A 15.7% reduction in critical path delay, a 21.4% reduction in area, and a 35% reduction in PDP for 32-bit addition involving a 8-bit least significant inaccurate sub-adder, and (ii) a 15.3% reduction in critical path delay, a 10.7% reduction in area, and a 20% reduction in PDP for 64-bit addition involving a 8-bit least significant inaccurate sub-adder. Moreover, comparisons with other approximate adders show that HOERAA has a significantly reduced average error, mean average error, and root mean square error, while reporting near optimum design metrics.

Clock Period Minimization with Minimum Leakage Power

In the design of nonzero clock skew circuits, an increase of the short-path delay may improve circuit speed or reduce leakage power. However, the impact of increasing the short-path delay on the trade-off between circuit speed and leakage power has not been well studied. An analysis of previous works shows that they can be classified into two independent groups. One group uses extra buffers to increase the short-path delay for achieving the lower bound of the clock period; however, this group has a large overhead of leakage power. The other group uses the combination of threshold voltage assignment and gate sizing (TVA/GS) to increase the short-path delay as possible for reducing leakage power; however, this group often does not work with the lower bound of the clock period. Accordingly, this article considers the simultaneous application of buffer insertion and TVA/GS during clock skew scheduling. Our objective is to minimize the leakage power for working with the lower bound of the clock period. To the best of our knowledge, our approach is the first leakage-power-aware clock skew scheduling that guarantees working with the lower bound of the clock period. Benchmark data consistently show that our approach achieves good results in terms of both the circuit speed and the leakage power.

Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements

Post-silicon clock tuning elements are widely used in high-performance designs to mitigate the effects of process variations and aging. Located on clock paths to flip-flops, these tuning elements can be configured through the scan chain so that clock skews to these flip-flops can be adjusted after man- ufacturing. Owing to the delay compensation across consecutive register stages enabled by the clock tuning elements, higher yield and enhanced robustness can be achieved. These benefits are, nonetheless, attained by increasing die area due to the inserted clock tuning elements. For balancing performance improvement and area cost, an efficient timing analysis algorithm is needed to evaluate the performance of such a circuit. So far this evaluation is only possible by Monte Carlo simulation which is very timing- consuming. In this paper, we propose an alternative method using graph transformation, which computes a parametric minimum clock period and is more than 10 4 times faster than Monte Carlo simulation while maintaining a good accuracy. This method also identifies the gates that are critical to circuit performance, so that a fast analysis-optimization flow becomes possible.

Temperature variation aware multi-scale delay, power and thermal analysis at RT and gate level

Thermal effects are rapidly gaining importance in nanometer CMOS technologies. Increased power density, coupled with spatio-temporal variability of chip workloads, causes on-die temperature non-uniformities. The assumption of a uniform temperature for the delay and power analysis of a large CMOS circuit produces inaccurate results. For this reason, significant design margins are taken to ensure safe operation. To improve design quality, we need precise localization of hotspots at detailed spatial resolution which is very computationally intensive. Consequently, thermal analysis needs to be done at multiple levels of granularity using a versatile thermal floorplan. We propose MiMAPT, an approach for analyzing delay, power and temperature in digital circuits. MiMAPT integrates seamlessly into major industrial Front-end and Back-end chip design flows. It accounts for temperature non-uniformities and self-heating while performing analysis. Thermal analysis is done at register-transfer (RT) and then gate-level considering non-regular shapes of on-die units with multiple scales of resolution and speed. To demonstrate the capability of MiMAPT in temperature variation aware delay/power estimation, a widely used IP block is chosen and four different chips are implemented using 65nm and 40nm (LVT, HVT) technology nodes. Different temperature patterns are then applied to the design. Accuracy improvements of up to 28% for static power and 16% for minimum clock period are reported in comparison with uniform averaged temperature assumption. Evaluating the ability of MiMAPT in multi-scale thermal analysis, a speed-up of 98× is reported compared to fine-grained method, while keeping false negatives at zero and the error of temperature estimation below 0.05°C.

A novel framework for retiming using evolutionary computation for high level synthesis of digital filters

In this paper, design of a new algorithm and a framework for retiming the DSP blocks based on evolutionary computation process is explained. Optimal DSP blocks such as digital filter design is a high level synthesis problem which includes optimally mapping digital filter specifications on to FPGA (Field Programmable Gate Array) architecture. Retiming is the considered optimization method in this paper which gives optimality in terms of algorithm processing speed and digital filter operating frequency with register count as a constraint. The designed novel algorithm is for the synthesis of high speed digital filters for different signal processing applications based on nature inspired evolutionary computation method. The classical retiming algorithms such as clock period minimization and register minimization that are addressed in the literature provide a single heuristic solution based on the chosen optimization parameter such as clock period. However, for retiming which is multi-objective optimization, evolutionary approach can lead to better results. Using the designed evolutionary computation based retiming method, retimed solution database is generated with higher frequency and different output register counts by searching the digital block solution space. Depending on the clock period and register count constraint, designer can take a design decision. Here, various signal processing designs are used to facilitate the design analysis. Results also show that the CPU processing time needed to compute multiple solutions using the designed algorithm for filter circuits is reduced for designs whose maximum feasible solutions are less than 50. If the circuit is very big with the possible solution space greater than 50 solutions, then algorithm performs slower. A comparison is also provided in the Simulations section with respect to all the existing classical retiming methods in the literature such as clock period and register minimization retiming to prove the concept. Multi-objective genetic algorithms are the considered evolutionary computation method in this paper.

A practical evaluation of the performance of the Impulse CoDeveloper HLS tool for implementing large-kernel 2-D filters

Bidimensional convolution is a low-level processing algorithm which is of great interest in many areas, but its high computational cost limits the size of the kernels, especially in real-time embedded systems. This work describes the process of designing 2-D filters with large kernels (up to 50 × 50 coefficients) using the Impulse CoDeveloperTM high-level synthesis (HLS) tool. The purpose of this paper is twofold: first, to provide a practical guide for designers willing to make the most of an HLS tool like Impulse CoDeveloper, and second, to compare the results, in terms of area utilization, minimum clock period and power consumption, with implementations developed using lower-level design tools. The results show that RTL-based implementations can achieve higher throughputs (up to 44 % faster) than CoDeveloper-based ones. Nevertheless, CoDeveloper can also meet the high-performance requirements of the most demanding real-time applications, but with less effort and shorter design cycles.

Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms

In this paper, we present a novel circuit-level timing error mitigation technique, which aims to increase energy-efficiency of digital signal processing datapaths without loss of robustness. Timing errors are detected using razor flip-flops on critical-paths, and the error-rate feedback is used to control a dynamic voltage scaling control loop. In place of conventional razor error correction by replay, we propose a new approach to bound the magnitude of intermittent timing errors at the circuit level. A timing guard-band is created by shaping the path delay distribution such that the critical paths correspond to a group of least-significant bit registers. These end-points are ensured to be critical by modifying the topology of the final stage carry-merge adder, and by using tool-based device sizing. Hence, timing violations lead to weakly correlated logical errors of small magnitude in a mean-squared-error sense. We examine this approach in an finite-impulse response (FIR) filter and a 2-D discrete cosine transform implementation, in 32-nm CMOS. Power saving compared to a conventional design at iso-frequency is 21%-23% at the typical corner, while retaining a voltage guard-band to protect against fast transient changes in switching activity and supply noise. The impact on minimum clock period is small (16%-20%), as it does not necessitate the use of ripple-carry adders and also requires only a bare minimum of additional design effort.

Statistical Timing Analysis for Latch-Controlled Circuits With Reduced Iterations and Graph Transformations

Level-sensitive latches are widely used in high- performance designs. For such circuits efficient statistical timing analysis algorithms are needed to take increasing process vari- ations into account. But existing methods solving this problem are still computationally expensive and can only provide the yield at a given clock period. In this paper we propose a method combining reduced iterations and graph transformations. The reduced iterations extract setup time constraints and identify a subgraph for the following graph transformations handling the constraints from nonpositive loops. The combined algorithms are very efficient, more than 10 times faster than other existing methods, and result in a parametric minimum clock period, which together with the hold time constraints can be used to compute the yield at any given clock period very easily.

Incremental min-period retiming algorithm for FPGA synthesis based on influence of fan-outs

An improved linear-time retiming algorithm is proposed to incrementally optimize the clock period, especially considering the influence of the in-out degree of the critical combinational elements. Firstly, the critical elements are selected from all the critical combinational elements to retime. Secondly, for the nodes that cannot be performed with such retiming, register sharing is implemented while the path delay is kept unchanged. The incremental algorithm can be applied with the technology mapping to minimize the critical path delay and obtain fewer registers in the retimed circuit with the near-optimal clock period. Compared with Singh’s incremental algorithm, experiments show that the proposed algorithm can reduce the flip-flop count by 11% and look-up table(LUT) count by 5% while improving the minimum clock period by 6%. The runtime is also reduced by 9% of the design flow.

Iterative timing analysis based on nonlinear and interdependent flipflop modelling

In this paper, the authors build a new modelling framework for the timing behaviour of a flipflop by putting the clock-to-q delay into a nonlinear functional relationship with the data/clock alignment of the flipflop. This new framework opens new perspectives into the functioning of a digital circuit by viewing it as a fully interconnected and interdependent system. Consequently, the traditional method for timing analysis is rendered insufficient. An iterative timing analysis method is then developed to solve two related problems. One is to check whether a circuit can work at a given clock period; the other is to determine the minimal clock period of a circuit. Experimental results show that a reduction of the clock period is achieved and its significance is observed especially when process variation is considered.

Reducing sequencing complexity in dynamical quantum error suppression by Walsh modulation

We study dynamical error suppression from the perspective of reducing sequencing complexity, with an eye toward facilitating the development of efficient semiautonomous quantum-coherent systems. To this end, we focus on digital sequences where all interpulse time periods are integer multiples of a minimum clock period and compatibility with digital classical control circuitry is intrinsic. We use so-called Walsh functions as a unifying mathematical framework; the Walsh functions are an orthonormal set of basis functions which may be associated directly with the control propagator for a digital modulation scheme. Using this insight, we characterize the suite of resulting Walsh dynamical decoupling sequences---including both familiar and novel control sequences---and identify the number of periodic square-wave (Rademacher) functions required to generate the associated Walsh function as the key determinant of the error-suppressing features. We also show how Walsh modulation may be employed for the protection of certain nontrivial logic gates. Based on these insights, we identify Walsh modulation as a digital-efficient approach for physical-layer error suppression.

Minimum Inserted Buffers for Clock Period Minimization

It is well known that the combination of clock skew scheduling and delay insertion can achieve the lower bound of sequential timing optimization. Previous works focus on the minimization of required inserted delay. However, from the viewpoint of design clo- sure, minimizing the number of inserted buffers is also very important. In this paper, we propose an MILP (mixed integer linear programming) approach to minimize the number of inserted buffers under the constraints on the lower bound of sequential timing optimization and the lower bound of required inserted delay. Note that our MILP approach guarantees obtaining the optimal solution. Experimental results consistently show that our MILP ap- proach can greatly reduce the number of inserted buffers.

STATISTICAL TIMING ANALYSIS OF THE CLOCK PERIOD IMPROVEMENT THROUGH CLOCK SKEW SCHEDULING

Statistical static timing analysis (SSTA) methods, which model process variations statistically as probability distribution function rather than deterministically, have been thoroughly performed on traditional zero clock skew circuits. In the traditional zero clock skew circuits, the synchronizing clock signal is designed to arrive in phase with respect to each register. However, designers will often schedule the clock skew to different registers in order to decrease the minimum clock period of the entire circuit. Clock skew scheduling imparts very different timing constraints that are based, in part, on the topology of the circuit. In this paper, SSTA is applied to nonzero clock skew circuits in order to determine the accuracy improvement relative to their zero skew counterparts, and also to assess how the results of skew scheduling might be impacted with more accurate statistical modeling. For 99.7% timing yield (3σ variation), SSTA is observed to improve the accuracy, and therefore increase the timing margin, of nonzero clock skew circuits by up to 2.5×, and on average by 1.3×, the amount seen by zero skew circuits.