Clock Harmonics Research Articles

Near-Field Backscattering-Based Sensing for Hardware Trojan Detection

This article presents the near-field measurement setup and the sensor topology used to measure the backscattered signal from a small spot of $\sim 1$ mm on an FPGA to enable hardware Trojan (HT) detection. The novel sensor topology used in the setup contains a combination of $E$ - and $H$ -field probes with a tip diameter of 0.2 mm, which is used to excite a carrier and receive the modulated scattered signal that carries a signature of the inspected logic circuit. As a proof of concept and to develop insight, an EM-circuit co-simulation is presented to show that the received signal contains a signature of the logic circuit under test, which is imprinted on the relative power levels of the modulated scattered clock harmonics. The received modulated scattering signature was successfully used to detect the presence of an HT in the original circuit with 100% accuracy without false positives. The effects of using $E$ - and $H$ -field probes in very close proximity, such as resolution and mutual coupling, are analyzed and discussed. It is shown that there is a 12% decrease in resolution and less than 0.01 dB impact on invasiveness. The frequency band of operation for the measurement setup is 3–5 GHz. The probe combination is shown to have a spot size of ~1 mm, a coupling isolation better than 20 dB over the whole band and 30 dB for the design frequency.

On the performance of digital adaptive spur cancellation for multi-standard radio frequency transceivers

This study deals with the asymptotic performance of a multiple-spur cancellation scheme. Radio frequency transceivers are now multi-standard and specific impairment can occur. The clock harmonics, called spurs, can leak into the signal band of the reception stage, and thus degrade the performance. The performance of a fully digital approach is presented here. A one-spur cancellation scheme is first described, for which we exploit the a priori knowledge of the spur frequency to create a reference of the polluting tone with the same frequency. A least-mean-square (LMS) algorithm block that uses this reference to mitigate the polluter is designed. However, due to imperfections in the physical components, there is a shift between the a priori frequency and the actual frequency of the spur, and the spur is affected by Brownian phase noise. Under these circumstances, we study the asymptotic and transient performance of the algorithm. We next improve the transient performance by adding a previously proposed adaptive-step-size process. In a second part of this paper, we present a multiple-spur parallel approach that is based on the one-spur cancellation scheme, for which we provide a closed-form expression of the asymptotic signal-plus-noise interference ratio in the presence of frequency shifts and phase noise.

A model of the leakage in the frequency domain and its application to CPA and DPA

This paper introduces a leakage model in the frequency domain to enhance the efficiency of side channel attacks of CMOS circuits. While usual techniques are focused on noise removal around clock harmonics, we show that the actual leakage is not necessary located in those expected bandwidths as experimentally observed by Mateos and Gebotys (A new correlation frequency analysis of the side channel, p 4, 2010). We start by building a theoretical modeling of power consumption and electromagnetic emanations before deriving from it a criterion to guide standard attacks. This criterion is then validated on real experiments, both on FPGA and ASIC, showing an impressive increase of the yield of SCA.

Impact of electromagnetic noise from PCs on performance of multiband-OFDM UWB systems

Since personal computers (PCs) radiate radio noise in a wide frequency range, wireless devices added to PCs may be subjected to interference from PC noise. Investigations were carried out on what impact clock harmonics radiating from a PC had on the bit error rate (BER) of multiband OFDM (MB-OFDM) UWB devices. The results indicated that clock harmonics cause considerable BER degradation in UWB devices especially those operated in high-bitrate communication modes. It was also found that the frequency modulation of a PC clock signal, i.e., so-called spread spectrum clocking (SSC), had no effect on mitigating BER degradation, even though SSC techniques are commonly used in PCs for reducing the power spectral density of radiated noise. Discussions were further made on a possible scheme of mitigating interference by using Viterbi decoding with channel state information (CSI) that is obtained by estimating the instantaneous frequency of clock signal directly provided by the PC to the UWB device.

Impact of Frequency-Modulated Harmonic Noises From PCs on OFDM-Based WLAN Systems

Theoretical and numerical analyses are conducted on the bit error rate (BER) of orthogonal frequency division multiplexing (OFDM)-based wireless LAN (WLAN) systems that are subjected to electromagnetic interference (EMI) caused by radiated noises from personal computers (PCs). The aim of the analysis is to investigate the impact of frequency- modulated harmonic noises generated by spread-spectrum clock (SSC) systems in PCs. SSC techniques are commonly employed in order to reduce the spectral amplitude of clock harmonics measured in EMI compliance tests. The results of the analysis revealed that: (1) BER can be seriously affected in an actual situation where a WLAN antenna installed in or placed very close to a PC receives noise generated by the PC itself; (2) the forward error correction (FEC) in IEEE802.11 a/g becomes less effective as the frequency variation rate of the harmonic increases; and (3) frequency-modulated clock harmonics have a greater negative effect on BER than unmodulated harmonics do. Thus, SSC does not necessarily reduce the impact of clock harmonics on OFDM-based WLAN systems, even if the spectral amplitude of the harmonics is reduced. The impact of clock harmonics on WLAN is compared with that of other wideband noises. Discussion is further extended to cover how to mitigate the interference.

Interference potential of PC noises on MB-OFDM UWB systems

Since PC noises in the UWB frequency band mainly comprise the harmonics of clock signals, a numerical analysis is made on the influence of clock harmonics on the bit error rate (BER) of multiband OFDM (MB-OFDM) UWB systems. Results show that clock harmonics cause a considerable BER degradation when a UWB terminal is placed close to a PC. They further show that frequency modulation of a PC clock signal, so-called spread spectrum clocking (SSC), has no effect for mitigating BER degradation, though SSC techniques are commonly used in PCs for reducing the power spectral density of radiated clock harmonic noises

Estimating the Amplitude Reduction of Clock Harmonics Due to Frequency Modulation

Simple formulae were theoretically derived for estimating the reduction in amplitude of clock harmonics, as measured in electromagnetic interference (EMI) tests, due to clock frequency modulation (FM). They show how the amplitude reduction is related to the clock FM parameters and resolution bandwidth (RBW) in spectrum measurement. Numerical simulations and experiments clearly demonstrated the validity of this analysis. Because clock FM does not reduce the actual power of the clock harmonics, the apparent decrease in the harmonic amplitude must be carefully treated when evaluating the potential of the radiated harmonics interfering with wireless systems

Evaluation of BER in Bluetooth Wireless Systems Disturbed by Radiated Noise from Spread Spectrum Clock Systems

Frequency-modulated clock signals are widely used in personal computers to reduce the amplitude of the clock harmonic noise, as measured using an electromagnetic interference (EMI) test receiver. However, the power of the clock harmonics is not decreased with this technique called spread spectrum clocking (SSC). Hence, the impact of the harmonics of a frequency-modulated clock on the bit error rate (BER) and packet error rate (PER) of a Bluetooth system is theoretically analyzed. In addition, theoretical analysis covers the effectiveness of a frequency hopping spread spectrum (FH-SS) scheme and forward error correction (FEC) in mitigating the degradation in the BER and PER caused by clock harmonic interference. The results indicate that the BER and PER strongly depend on the modulating frequency and maximum frequency deviation of the clock harmonic. They also indicate that radiated clock harmonics may considerably degrade the BER and PER when a Bluetooth receiver is very close to a personal computer. Frequency modulating the clock harmonics slightly reduces the BER while it negligibly reduces the PER.

Digital ground bounce reduction by supply current shaping and clock frequency Modulation

In a synchronous clock-distribution network, digital circuits switch simultaneously on the clock edge; therefore, they generate ground bounce due to sharp peaks of the supply current. We demonstrate an effective combination of two methodologies for ground-bounce reduction based on shaping the supply current: 1) introducing intentional skews to the synchronous clock network and 2) frequency modulation of the system clock. The former technique reduces the time-domain peaks as well as the spectral power of the supply current by spreading the simultaneous switching activities. The latter technique reduces the power contained in the clock harmonics by spreading this power into the side lobes formed around the clock harmonics without any change in the spectral power of the supply current. We also describe an analytical framework to analyze the impact of cycle-to-cycle variations of the supply current on the ground-bounce voltage. Simulation results for a 40K-gates circuit in a 0.18-/spl mu/m 1.8-V CMOS process on a bulk-type substrate show around 26 dB reduction in the spectral peaks of the ground-bounce spectrum at the circuit resonance and factors of 3.04/spl times/ and 2.64/spl times/ reduction in the peak-to-peak and RMS values, respectively, of the ground bounce in the time domain when these two techniques are combined. These two techniques are believed to be good candidates for the development of digital low-noise designs in CMOS technologies.

A 22-mA 3.0-dB NF direct conversion receiver for 3G WCDMA

A 2-GHz single-chip direct conversion receiver achieves a 3.0-dB double-sideband noise figure, -14-dBm IIP3 and +17-dBm IIP2 with 60-mW power consumption from a 2.7-V supply. The receiver is targeted for the third generation UTRA/FDD WCDMA system. The low power consumption has been achieved with a proper partitioning and by avoiding buffering between blocks. In the differential RF front end, current boosted quadrature mixers follow the variable-gain low-noise amplifier. At the baseband, on-chip ac-coupled highpass filters are utilized to implement amplification with variable gain having small transients related to gain steps. The outputs of the analog channel selection filters are sampled directly by the two single-amplifier 6-bit pipeline A/D converters. The spurious tones due to the feedthrough of clock harmonics to the RF input increase the noise figure less than 0.1 dB. The receiver has been fabricated with a 0.35-/spl mu/m 45-GHz f/sub T/ SiGe BiCMOS process.