Clock Feedthrough Research Articles

A Low Mismatch Current Charge Pump Applied to Phase-Locked Loops.

This paper presents a charge pump circuit with a wide output range and low current mismatch applied to phase-locked loops. In this designed structure, T-shaped analog switches are adopted to suppress the non-ideal effects of clock feedthrough, switching time mismatch, and charge injection. A source follower and current splitting circuits are proposed to improve the matching accuracy of the charging and discharging currents and reduce the current mismatch rate. A rail-to-rail high-gain amplifier with a negative feedback connection is introduced to suppress the charge-sharing effect of the charge pump. A cascode current mirror with a high output impedance is used to provide the charge and discharge currents for the charge pump, which not only improves the current accuracy of the charge pump but also increases the output voltage range. The proposed charge pump is designed and simulated based on a 65 nm CMOS process. The results show that when the power supply voltage is 1.2 V, the output current of the charge pump is 100 μA, the output voltage is in the range of 0.2~1 V, and the maximum current mismatch rate and current variation rate are only 0.21% and 1.4%, respectively.

An ultrahigh input impedance low noise analog front‐end design for epilepsy brain recording system

SummaryThis paper presents an ultrahigh input impedance, low noise, and wide bandwidth four‐channels analog front‐end (AFE) for low‐power neural recording systems. To achieve high input impedance, the buffer channels are placed between the electrodes and the main amplifier stage of the AFE. The buffer is designed with low noise and low power consumption to obtain high input impedance of overall AFE while maintaining low input‐referred noise and low power consumption. A chopper capacitively coupled chopper instrumentation amplifier (CCIA) is placed after the buffer as the main amplifier stage of the AFE to improve the common mode rejection ratio (CMRR) and the input‐referred noise of the overall AFE design. A new chopper stabilization control technique is proposed and used in the CCIA stage to reduce the charge injection and clock feedthrough and consequently the high‐frequency ripple of the AFE output signal. A programmable gain amplifier (PGA) is designed as the third stage to adjust the overall gain of the AFE. Benefiting from PGA, the AFE can adapt its gain with both action potential and local field potential signals. To reduce the number of the electrode to be implanted and reduce the impedance mismatch that causes the degradation on overall CMRR performance, two AFE channels shared a reference electrode followed by a reference buffer. The proposed AFE is designed and simulated using a standard 180 nm CMOS process and operates in a wide frequency band of 2.1 to 2500 Hz with low input‐referred noise of 1.6 μVrms and a CMRR over 80 dB at 2.1 Hz. The total power consumption is lower than 4.3 μW per channel. With the proposed structure of AFE, the input impedance is 35 GΩ @ 21 Hz and the minimum impedance over operational bandwidth is 75 MΩ @ 2.5 kHz.

Design of a charge-sensitive amplifier for MEMS piezoelectric hydrophone

Hydrophone is an important part of sonar system and convert acoustic signal into electrical signal. However, the electrical signal generated by the hydrophone is relatively weak and cannot be directly used for underwater detection and communication. Therefore, it is necessary to preprocess the generated electrical signal. In this paper, a switched capacitor charge-sensitive amplifier for MEMS piezoelectric hydrophone is designed. In the structure, two single-channel charge amplifiers are used for time-division multiplexing. The noise sampling and charge amplification are performed separately in the same half cycle to achieve the effect of alternating output, thereby increasing the sampling rate and solving the problem of discontinuous output of the switched capacitor circuit. In the circuit design, virtual switch and two-phase non-overlapping clock are adopted to reduce the error caused by charge injection and clock feedthrough effect of CMOS switch. What’s more, the correlated double sampling technique is used to reduce the offset and low frequency noise of the circuit. The gain of the charge-sensitive amplifier designed in this study is 26 dB, the bandwidth is 0.8Hz∼17.6kHz, the equivalent input noise power spectral density is 115.6 nV/Hz at 0.1Hz, and the charge sensitivity is 2 mV / pC. The fitting line between the input charge and the amplitude of the output curve is similar to the theory. The simulation results show that the charge-sensitive amplifier proposed in this study meets the design requirements of the MEMS piezoelectric hydrophone readout circuit.

Design of a 0.4 V, 8.43 ENOB, 5.29 nW, 2 kS/s SAR ADC for Implantable Devices

This paper presents a 9-bit differential, minimum-powered, successive approximation register (SAR) ADC intended for implantable devices or sensors. Such applications demand nanowatt-range power consumption, which is achieved by designing the SAR ADC with a proposed bootstrap switch, bespoke split-capacitive DAC, customized comparator and a modified dynamic bit-slice unit for SAR logic. The linearity of the ADC is improved by introducing a bootstrap switch with a low clock feedthrough and threshold voltage variations along with the disseminated attenuation capacitor in the split-capacitive DAC. The dynamic comparator is customized to be simple in terms of the number of transistors to gain the advantage of low power and is also designed to have a low dynamic offset voltage. The stacking concept is embedded in the bit-slice unit of SAR logic to achieve reduced leakage power. This paper is concerned with how to contribute to low power consumption in all the aspects possible related to the implementation of the SAR ADC. With a 0.4 V supply and at 2 kS/s, the proposed ADC achieves an SNDR of 52.52 dB and a power consumption of 5.29 nW, resulting in a figure of merit (FOM) of 7.66 fJ/conversion-step.

A Wideband and Low Reference Spur PLL with Clock Feedthrough Suppressed and Low Current Mismatch Charge Pump and Symmetrical CML Divider

This paper presents the design and performance analysis of a wideband charge-pump phase-locked loop (CPPLL) characterized by low reference spur and low phase noise. The proposed CPPLL, operating as a wideband phase-locked loop (PLL) with a reference frequency of 100 MHz, achieves a wide tuning range of 40% from 2.0 GHz to 3.0 GHz. A clock feedthrough suppressed charge pump with additional bias current branches is used to reduce the PLL’s loop reference spur. The 4-stage current mode logic (CML) divide-by-2/3 circuit is utilized in the frequency divider to achieve high-speed frequency division. The circuit of an AND gate and latch in the 2/3 divider adopts a full differential symmetric structure to minimize the phase error of high-frequency differential signals. The voltage-controlled oscillator (VCO) is designed to provide a wide tuning range while optimizing the trade-off between the phase noise and power consumption. The fabricated PLL is implemented using a 0.13 µm CMOS process. Experimental measurements reveal a reference spur of −74.39 dBc at an oscillation frequency of 2.4 GHz. Moreover, the CPPLL achieves phase noise of −102.55 dBc/Hz@100 kHz and −127.15 dBc/Hz@1 MHz, while consuming 33.6 mW under a 1.2 V supply voltage. The integrated root-mean-square (rms) jitter, measured from 10 kHz to 10 MHz, is 340.99 fs, and the figure-of-merit (FoM) is −234.08 dB at a carrier frequency of 2.4 GHz, highlighting the potential of the proposed PLL for integrated circuit applications.

Design of a CMOS Image Sensor with Bi-Directional Gamma-Corrected Digital-Correlated Double Sampling

We present a 640 × 480 CMOS image sensor (CIS) with in-circuit bi-directional gamma correction with a proposed digital-correlated double sampling (CDS) structure. To operate the gamma correction in the CIS, the transfer function of the analog-to-digital converter can be changed by controlling the clock frequency of the counter using analog CDS. However, the analog CDS is vulnerable to capacitor mismatch, clock feedthrough, etc. Therefore, we propose a digital-CDS method with a hold-and-go counter structure to operate the bi-directional gamma correction in the CIS. The proposed CIS achieves a 10-bit resolution using a global log-exponential counter and configurable column reset counter with a resolution of 8/9 bits. The sensor was fabricated in a 0.11 μm CIS process, and the full chip area was 5.9 mm × 5.24 mm. The measurement results showed a maximum SNR improvement of 10.41% with the proposed bi-directional gamma-corrected digital-CDS with the hold-and-go counter. The total power consumption was 6.3 mW at a rate of 16.6 frames per second with analog, pixel, and digital supply voltages of 3.3 V, 3.3 V, and 1.5 V, respectively.

A Highly Reliable, Dynamic Logic-Based Hybrid MTJ/CMOS Magnetic Full Adder for High-Performance and Low-Power Application

At deep sub-micrometer technology, CMOS circuits suffer from high leakage and have reliability issues due to process variation. Hybrid magnetic tunnel junction (MTJ)/CMOS circuits have been proposed to overcome these challenges. MTJs have zero standby power and are compatible with CMOS technology. In this article, a dynamic logic-based hybrid MTJ/CMOS magnetic full adder (MFA) has been proposed, which eliminates the error voltage appearing on output due to charge injection and clock feedthrough phenomenon, thereby enhancing the performance of MFA and making it more reliable. This effect is induced by the pMOS transistor, which is used as a switch to precharge the output nodes. The proposed MFA uses two dummy transistors, whose drain and source terminals are shorted to make them act as MOS capacitors, to absorb the error voltage introduced by the switch pMOS transistor due to charge injection and clock feedthrough, when turned OFF. Eliminating the error induced due to charge injection and clock feedthrough makes the amplification process faster and reduces the dynamic power consumption. Results are verified by performing transient and Monte Carlo simulations using cadence virtuoso with UMC 40 nm CMOS technology kit and compact model of perpendicular magnetic anisotropy (PMA) MTJ, which validates that the proposed MFA is highly reliable as it provides the error-free output and imparts better power–delay product (PDP) compared to previously proposed MFA.

A high-precision interface for tunneling magnetoresistance sensors with 0.15 nT/√Hz resolution

The tunneling magnetoresistance (TMR) with high-resolution digital output is widely used in military and civil fields. In this work we proposed a low-noise read-out circuit and a four-order fully differential sigma-delta modulator for TMR sensors. In the read-out circuit, we used symmetrical cascade for good matching. We used correlated double sampling (CDS) technique to improve the conversion accuracy of the modulator. In switched capacitor circuits we used time-division multiplexing to suppress charge injection and clock feedthrough. The high-precision application specific integrated circuit (ASIC) chip was fabricated by a 0.35 [Formula: see text]m CMOS process from Shanghai Huahong foundry. The TMR sensor was placed in an environment of three-layer magnetic shielding for test. The active area of the ASIC is only about [Formula: see text]. At a sampling frequency of 20 kHz, the TMR magnetometer consumes 77 mW from a single 5 V supply; the sigma-delta modulator for TMR can achieve an average noise floor of −141 dBV. The magnetometer works at a full scale (FS) of [Formula: see text], it can achieve a nonlinearity of 0.2% FS and a resolution of 0.15 nT/Hz[Formula: see text] over a signal bandwidth.

A 100-GS/s Four-to-One Analog Time Interleaver in 55-nm SiGe BiCMOS

We demonstrate a four-to-one 100-GS/s time interleaver realized in a 55-nm BiCMOS technology. The interleaver comprises two stages of two-to-one sub-interleavers. Each sub-interleaver is implemented using a return-to-zero generation and summing architecture. This sub-interleaver architecture ensures lower clock feedthrough and contains an inherent feed-forward equalizer. Effective number of bits (ENOB) measurements have been performed revealing the interleaver's ENOB of 4.9 at 3 GHz. In addition, the transfer function is measured to show the capabilities of the inherent feed-forward equalizer of the sub-interleavers. The measured analog output bandwidth of the four-to-one interleaver is 73 GHz. Finally, a 100-GBd PAM-4 (200 Gb/s) signal is generated by interleaving four 25-GBd PAM-4 streams while consuming 700 mW.

A 32-GS/s Front-End Sampling Circuit Achieving >39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS

This paper presents a 32-GS/s front-end sampling circuit (FESC) in 65-nm CMOS. The FESC is designed for a 32-channel time-interleaved analog-to-digital converter (ADC), and the [Formula: see text] two-stage interleaving structure leads to a good trade-off between bandwidth and linearity. The analysis and cancellation of charge injection, clock feedthrough, and signal feedthrough are presented. Inductor peaking technique is adopted to extend the bandwidth of the buffer between the first and the second stage. Based on the simulation results, the proposed FESC consumes 136[Formula: see text]mW at 32 GS/s, and the signal-to-noise ratio (SNDR) is up to 39.55 dB at Nyquist input, achieving a state-of-the-art power efficiency.

Analysis and modeling of magnetic-free broadband circulator based on three switched reflection delay lines

Magnetic-free broadband circulator structure based on three switched reflection type delay lines with a total electrical length of 180-degree at the switching frequency is investigated. The nonreciprocal transmission property is modeled and simulated, the impedance mismatching property and reconfigurable direction are studied. A prototype magnetic-free circulator circuit is designed and fabricated using coaxial cables and switches driving by switching frequency of 7.94 MHz with tolerance of ±10%. The nonreciprocal scatter parameters are measured in 300kHz ∼ 100 MHz. It shows that the circulator direction can be reconfigured by changing the switching frequency, and the maximum operating bandwidth equals 1.5f s which is limited by clock feedthrough and spectrum aliasing.

A Four-Level Switching Scheme for SAR ADCs with 87.5% Area Saving and 97.85% Energy-Reduction

In this paper, a new highly energy-efficient switching scheme is presented for successive approximation register analogue-to-digital converters. The proposed method applies a four-level switching strategy to reduce the switching energy to one of the lowest levels reported yet. Also, the controller of this method has low complexity compared to the other procedures. In contrast to the conventional scheme, the switching energy is reduced by 97.85% and the total capacitor size is decreased by 87.5%. Moreover, under the condition of the 50-times Monte-Carlo simulation for capacitor mismatch and reference voltages mismatch (Vref/2 and Vref/4), the mean value of the effective number of bit (ENOB) with standard deviation of 1% is 7.4 and 7.33 bits, respectively, while the ENOB value without any mismatches is 7.51 bits with sampling frequency of 1MS/s. It is noteworthy that the Monte-Carlo simulations are performed in Spectre simulator in Cadence with consideration all of non-idealities such as transistor charge injection, clock jitter and clock feedthrough. In other words, accurate and electrical simulation is performed instead of behavioral simulation. As a result, the bar graph of the ENOB values is plotted in MATLAB. In addition, the maximum and minimum of DNL/INL values are between − 0.3/0.3 LSB.

A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and Low-Noise Dynamic Comparator Technique

This paper presents a linearity improved 10-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with high-speed and low-noise dynamic comparator. A gate cross-coupled technique is introduced in boost sampling switch, the clock feedthrough effect is compensated without extra auxiliary switch and the linearity of sampling switch is enhanced. Further, substrate voltage boost technique is proposed, the absolute values of threshold voltage and equivalent impedances of MOSFETs are both depressed. Consequently, the delay of comparator is also reduced. Moreover, the reduction of threshold voltages for input MOSFETs could bring higher transconductance and lower equivalent input noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 1.5[Formula: see text]mW from 1[Formula: see text]V power supply with a SNDR [Formula: see text][Formula: see text]dB and SFDR [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.021[Formula: see text]mm2, and the corresponding FoM is 24.4 fJ/conversion-step with Nyquist frequency.

A Delay Spread Cancelling Waveform Characterizer for RF Power Amplifiers

A two channel 65-nm CMOS RF-waveform characterizer is presented that enables multi-harmonic adaptive matching networks or adaptive digital pre-distortion in RF-power amplifiers. The characterizer measures the dc component and the first 3 harmonics of RF signals by applying a DFT to 8 (ideally) equally spaced quasi-dc output voltages. Conventionally in these types of systems accuracy is limited by sample timing accuracies, which in our case are mainly due to delay cell mismatch. We introduce a novel way to cancel delay cell mismatch, that significantly increases measurement accuracy at the cost of only a small power and area increase. The RF-waveform characterizer achieves 6.8-bit measurement linearity together with a (clock feedthrough limited) 24 dB SFDR. The measured power consumption for our proof-of-principle demonstrator is 18.6 mW at a maximum input signal frequency of 1.1 GHz under continuous operation.

High‐speed analogue sampled‐data signal processing for real‐time fault location in electrical power networks

The emulation of low-loss or lossless one-dimensional (1D) or 2D transmission mediums using analogue sampled-data signal processing is presented. Based on discrete-time wave propagation simulation, transmission lines are emulated with many elementary identical delay elements, implemented by simple equivalent switched-capacitor (SC) circuits. The accuracy and limitations of this discrete time model are studied in the frame of power network fault location using electromagnetic time-reversal principle. The sensitivities to non-ideal effects usually plaguing analogue CMOS SC circuits, such as amplifier finite open-loop gain, offset, and parasitic charge injection due to clock feedthrough, are evaluated in the same context. It is shown that the SC line emulation is well suited to the presented fault location technique and considerably reduces the fault location time (by a factor up to 100) in comparison to standard digital solutions, allowing fault location resolutions of typically 1% within a few hundred milliseconds. These expectations are confirmed by measurements realised on the presented line model integrated-circuit, implemented in an AMS 0.35 μm CMOS process. The speed improvement obtained through the presented method is essential, potentially allowing real-time fault management in power grids.

A 0.55-V, 28-ppm/°C, 83-nW CMOS Sub-BGR With UltraLow Power Curvature Compensation

This paper proposes an ultralow power, high precision sub bandgap voltage reference (sub-BGR) for low-voltage self-powered devices. A novel ultralow power curvature compensation circuit is proposed to improve the temperature coefficient over a wide temperature range. A switch capacitor voltage divider with improved leakage current reduction switches is used to obtain a high accuracy and a low power. To minimize the clock feedthrough and charge injection in the switches, a clock scaling down circuit is proposed, that effectively improves the line sensitivity (LS) of the sub-BGR. The proposed sub-BGR is implemented in a 0.18- $\mu \text{m}$ standard CMOS process with a total area of 0.061 mm2. After measuring 30 chips, the average power consumption is 83 nW at 0.55 V of supply at 27 °C. In the supply voltage range of 0.55 to 1 V, the LS is 0.059%/V, and the error is ±0.75% ( $3\sigma $ ) after trimming.

A novel analog switch for high‐precision switched‐capacitor applications

SummaryThe performance of a switched‐capacitor circuit strongly depends on its analog switches. This paper introduces a new technique to design a high‐precision analog metal‐oxide‐semiconductor switch for switched‐capacitor applications. The accuracy of analog switches is a critical parameter to determine overall performance of the discrete‐time analog systems. To satisfy the accuracy requirements of the switch, a novel technique to minimize the charge injection and clock feedthrough errors by using a very simple structure is proposed. Moreover, an innovative approach to increase the OFF resistance of the switch and consequently minimizing its leakage current is presented. To evaluate the performance of the proposed switch, simulations are done in TSMC 0.18μm standard complementary metal‐oxide‐semiconductor technology with BSIM3V3 device models. The ON and OFF resistances of the switch are one of the most important factors that should be considered while investigating analog switches. The ON resistance of the proposed switch is less than 560Ω over entire input signal range which completely satisfies the tracking bandwidth requirements. In addition, since the proposed switch provides an ultrahigh OFF resistance in the range of several GΩs, the leakage current of the proposed switch is negligible. Simulation results also show that switch‐induced errors are significantly eliminated by using the proposed cancellation technique. The output error charge due to charge injection and clock feedthrough over a wide range of input signal variation is very low (less than 1.6 fC). Moreover, simulation results show that the proposed switch achieves signal to noise plus distortion ratio of 80.55 dB, effective number of bits of 13.08, total harmonic distortion of −81.41 dB, and spurious‐free dynamic range of 87.7 dB for a 2.5‐MHz sinusoidal input of 800‐mV peak‐to‐peak amplitude at 200‐MHz sampling rate with a 1.8‐V supply voltage. Consequently, the simulation results verify that the proposed switch can significantly improve the dynamic and static performances of a switched‐capacitor circuit.

A Low-Power High-Speed Hybrid ADC With Merged Sample-and-Hold and DAC Functions for Efficient Subranging Time-Interleaved Operation

An 8-bit 1-GS/s hybrid analog-to-digital converter (ADC) for high-speed low-power applications is introduced. It has a subranging architecture with a 3-bit flash ADC as a first stage and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. In each channel, a merged sample-and-hold and capacitive digital-to-analog converter (SHDAC) performs the sampling and residue generation for the subranging operation. The effects of the parasitic capacitances on the SHDAC linearity are analyzed, and a linearity correction method is introduced to enable power-efficient high-speed operation in the presence of parasitics because the design approach allows reducing the sampling capacitance in the SHDAC. Furthermore, the sampling network configuration incorporates an error reduction technique to alleviate the clock feedthrough of bootstrap switches. The offsets of the comparators in the flash ADC are calibrated using a built-in reference signal via an extra sampling channel. According to postlayout simulations at 1 GS/s in 130-nm CMOS, the ADC has an effective number of bits higher than 7.37 bits up to the Nyquist frequency while consuming 13.3 mW from a 1.2-V supply.

Implementation of integrated circuit and design of SAR ADC for fully implantable hearing aids.

The hearing impaired population has been increasing; many people suffer from hearing problems. To deal with this difficulty, various types of hearing aids are being rapidly developed. In particular, fully implantable hearing aids are being actively studied to improve the performance of existing hearing aids and to reduce the stigma of hearing loss patients. It has to be of small size and low-power consumption for easy implantation and long-term use. The objective of the study was to implement a small size and low-power consumption successive approximation register analog-to-digital converter (SAR ADC) for fully implantable hearing aids. The ADC was selected as the SAR ADC because its analog circuit components are less required by the feedback circuit of the SAR ADC than the sigma-delta ADC which is conventionally used in hearing aids, and it has advantages in the area and power consumption. So, the circuit of SAR ADC is designed considering the speech region of humans because the objective is to deliver the speech signals of humans to hearing loss patients. If the switch of sample and hold works in the on/off positions, the charge injection and clock feedthrough are produced by a parasitic capacitor. These problems affect the linearity of the hold voltage, and as a result, an error of the bit conversion is generated. In order to solve the problem, a CMOS switch that consists of NMOS and PMOS was used, and it reduces the charge injection because the charge carriers in the NMOS and PMOS have inversed polarity. So, 16 bit conversion is performed before the occurrence of the Least Significant Bit (LSB) error. In order to minimize the offset voltage and power consumption of the designed comparator, we designed a preamplifier with current mirror. Therefore, the power consumption was reduced by the power control switch used in the comparator. The layout of the designed SAR ADC was performed by Virtuoso Layout Editor (Cadence, USA). In the layout result, the size of the designed SAR ADC occupied 124.9 μm × 152.1 μm. The circuit verification was performed by layout versus schematic (LVS) and design rule check (DRC) which are provided by Calibre (Mentor Graphics, USA), and it was confirmed that there was no error. The designed SAR ADC was implemented in SMIC 180 nm CMOS technology. The operation of the manufactured SAR ADC was confirmed by using an oscilloscope. The SAR ADC output was measured using a distortion meter (HM 8027), when applying pure tone sounds of 94 dB SPL at 500, 800, and 1600 Hz regions. As a result, the THD performance of the proposed chip was satisfied with the ANSI. s3. 22. 2003 standard. We proposed a low-power 16-bit 32 kHz SAR ADC for fully implantable hearing aids. The manufactured SAR ADC based on this design was confirmed to have advantages in power consumption and size through the comparison with the conventional ADC. Therefore, the manufactured SAR ADC is expected to be used in the implantable medical device field and speech signal processing field, which require small size and low power consumption.

Modeling and simulation of an eight-bit auto-configurable successive approximation register analog-to-digital converter for cardiac and neural implants

An analog-to-digital converter (ADC) is a critical block of the sensing unit of all implants and for measurements of various biophysiological signals that cover distinct portions of the frequency spectrum and signal bandwidths. However, the conventional methodology of direct transistor-level implementation of the ADC for any application does not guarantee the accuracy to meet the desired specifications. For this purpose, the behavioral modeling approach facilitates the designer to set up an environment to extract various electric and dynamic parameters with a good level of accuracy. Based on this, behavioral modeling of a new architecture of an eight-bit auto-configurable successive approximation register (SAR) ADC has been proposed in this paper for application in both cardiac and neural implants, such as pacemakers, deep brain stimulators, etc. All the building blocks of the SAR ADC have been modeled in such a way that the ADC can operate either in the voltage mode or the current mode and the various non-idealities, such as clock jitter, clock feedthrough, and thermal and flicker noise, among others, have been incorporated into the design to make it as realistic as possible and estimate the response of the ADC with high accuracy. Based on the simulations for both ideal and non-ideal scenarios, it is observed that the proposed eight-bit auto-configurable SAR ADC works efficiently for applications in both cardiac and neural implants and achieves a signal-to-noise ratio as high as 48.943 dB and effective number of bits of 7.838 bits with very low distortion of only −62.549 dB.