Clock Feedthrough Noise Research Articles

마이크로 전력의 축차근사형 아날로그-디지털 변환기를 위한 시간 도메인 비교기

본 논문에서는 저전압 고해상도 축차근사형 아날로그-디지털 변환기를 위한 시간-도메인 비교기를 제안한다. 제안하는 시간-도메인 비교기는 클럭 피드-스루 보상회로를 포함한 전압제어지연 변환기, 시간 증폭기, 그리고 바이너리 위상 검출기로 구성된다. 제안하는 시간-도메인 비교기는 작은 입력 부하 캐패시턴스를 가지며, 클럭 피드-스루 노이즈를 보상한다. 시간-도메인 비교기의 특성을 분석하기 위해 다른 시간-도메인 비교기를 가지는 두 개의 1V 10-bit 200-kS/s 축차근사형 아날로그-디지털 변환기가 0.18-<TEX>${\mu}m$</TEX> 1-poly 6-metal CMOS 공정에서 구현된다. 11.1kHz의 아날로그 입력신호에 대해 측정된 SNDR은 56.27 dB이며, 제안된 시간-도메인 비교기의 클럭 피드-스루 보상회로와 시간 증폭기가 약 6 dB의 SNDR을 향상시킨다. 구현된 10-bit 200-kS/s 축차근사형 아날로그-디지털 변환기의 전력소모와 면적은 각각 10.39 <TEX>${\mu}W$</TEX>와 0.126 mm2 이다. In this paper, a time-domain comparator is proposed for a successive approximation (SA) analog-to-digital converter (ADC) with a low power and high resolution. The proposed time-domain comparator consists of a voltage-controlled delay converter with a clock feed-through compensation circuit, a time amplifier, and binary phase detector. It has a small input capacitance and compensates the clock feed-through noise. To analyze the performance of the proposed time-domain comparator, two 1V 10-bit 200-kS/s SA ADCs with a different time-domain comparator are implemented by using 0.18-<TEX>${\mu}m$</TEX> 1-poly 6-metal CMOS process. The measured SNDR of the implemented SA ADC is 56.27 dB for the analog input signal of 11.1 kHz, and the clock feed-through compensation circuit and time amplifier of the proposed time-domain comparator enhance the SNDR of about 6 dB. The power consumption and area of the implemented SA ADC are 10.39 <TEX>${\mu}W$</TEX> and 0.126 mm2, respectively.

A 1V 200kS/s 10-bit Successive Approximation ADC for a Sensor Interface

A 200kS/s 10-bit successive approximation (SA) analog-to-digital converter (ADC) with a rail-to-rail input signal is proposed for acquiring biosignals such as EEG and MEG signals. A split-capacitor-based digital-to-analog converter (SC-DAC) is used to reduce the power consumption and chip area. The SC-DAC's linearity is improved by using dummy capacitors and a small bootstrapped analog switch with a constant on-resistance, without increasing its area. A time-domain comparator with a replica circuit for clock feed-through noise compensation is designed by using a highly differential digital architecture involving a small area. Its area is about 50% less than that of a conventional time-domain comparator. The proposed SA ADC is implemented by using a 0.18-µm 1-poly 6-metal CMOS process with a 1V supply. The measured DNL and INL are +0.44/-0.4 LSB and +0.71/-0.62 LSB, respectively. The SNDR is 55.43dB for a 99.01kHz analog input signal at a sampling rate of 200kS/s. The power consumption and core area are 5µW and 0.126mm2, respectively. The FoM is 47fJ/conversion-step.

Optimal design of CMOS pseudoactive pixel sensor (PAPS) structure for low-dark-current and large-array-size imager applications

In this paper, a pixel structure called the optimal pseudoactive pixel sensor (OPAPS) is proposed and analyzed for the applications of CMOS imagers. The shared zero-biased-buffer in the pixel is used to suppress both dark current of photodiode and leakage current of pixel switches by keeping both biases of photodiode and parasitic pn junctions in the pixel bus at zero voltage or near zero voltage. The factor of photocurrent-to-dark-current ratio per pixel area (PDRPA) is defined to characterize the performance of the OPAPS structure. It is found that a zero-biased-buffer shared by four pixels can achieve the highest PDRPA. In addition, the column sampling circuits and output correlated double sampling circuits are also used to suppress fixed-pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of the proposed OPAPS CMOS imager with the format of 352/spl times/288 (CIF) has been designed and fabricated by using 0.25-/spl mu/m single-poly-five-level-metal (1P5M) N-well CMOS process. In the fabricated CMOS imager, one shared zero-biased-buffer is used for four pixels where the PDRPA is equal to 47.29 /spl mu/m/sup -2/. The fabricated OPAPS CMOS imager has a pixel size of 8.2/spl times/.2 /spl mu/m, fill factor of 42%, and chip size of 3630/spl times/3390 /spl mu/m. Moreover, the measured maximum frame rate is 30 frames/s and the dark current is 82 pA/cm/sup 2/. Additionally, the measured optical dynamic range is 65 dB. It is found that the proposed OPAPS structure has lower dark current and higher optical dynamic range as compared with the active pixel sensor (APS) and the conventional passive pixel sensor (PPS). Thus, the proposed OPAPS structure has high potential for the applications of high-quality and large-array-size CMOS imagers.

A New CMOS Pixel Structure for Low-Dark-Current and Large-Array-Size Still Imager Applications

A pixel structure for still CMOS imager application called the pseudoactive pixel sensor (PAPS) is proposed and analyzed in this paper. It has the advantages of a low dark current, high signal-to-noise ratio, and a high fill factor over the conventional passive pixel sensor imager or active pixel sensor imager. The readout circuit called the zero-bias column buffer-direct-injection structure is also proposed to suppress both the dark current of the photodiode and the leakage current of row switches by keeping both biases of photodiode and the parasitic p-n junction in the column bus at or near zero voltage. The improved double delta sampling circuits are also used to suppress fixed pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of the proposed PAPS CMOS imager with the format of 352/spl times/288 (CIF) has been fabricated by using a 0.25-/spl mu/m single-poly-five-level-metal (1P5M) n-well CMOS process. The pixel size is 5.8 /spl mu/m/spl times/5.8 /spl mu/m. The pixel readout speed is from 100 kHz to 10 MHz, corresponding to the maximum frame rate above 30 frames/s. The proposed still CMOS imager has a fill factor of 58%, chip size of 3660 /spl mu/m/spl times/3500 /spl mu/m, and power dissipation of 24 mW under the power supply of 3.3 V. The experimental chip has successfully demonstrated the function of the proposed new PAPS structure. It can be applied in the design of large-array-size still CMOS imager systems with a low dark current and high resolution.

N-path and pseudo-N-path cells for switched-current signal processing

Novel switched-current N-path and pseudo-N-path cells are proposed, which allow the transformation of a z-domain low-pass reference filter into a bandpass one. The three types of cells, a forward Euler, backward Euler, and bilinear integrator, perform the z/spl rarr/-z and z/spl rarr/-z/sup N/ transformations, which avoid clock-feedthrough noise in the realized filter passband. The pseudo-N-path cells operate on the circulating-delay principle, which avoids mirror-frequency noise due to path mismatches and require only standard biphase clocks to operate. The effects of circuit nonidealities are studied and performance comparisons are made with a conventional narrow-band bandpass filter. The robust frequency stability characteristic makes the cells suitable for narrow-band bandpass applications. Results of an HSPICE simulation example is given for a sixth-order pseudo-N-path filter.

Analogue to digital convertor architecture with a signal level detector

A new signal level detector for a flash-type A/D convertor is introduced. It operates like a comparator with the 1-of-n encoder of flash-type A/D convertors. Because the clock signal can be omitted in the application of the comparator, clock feedthrough noise is not a problem. A resolution of up to 8 bits in A/D conversion is feasible.

Novel switched-capacitor pseudo-N-path filter

An improved circuit for pseudo-N-path switched-capacitor filters (SCFs) is proposed. The circuit is faster than previously described low-noise circuits, and does not produce clock feedthrough noise in the centre of its passband. However, the number of amplifiers required is equal to the number of paths in its basic N-path cell. Computer simulation confirms the usefulness of the described circuit.

Differential charge-domain bilinear-Z switched-capacitor pseudo-N-path filters

The charge-domain bilinear-Z transformation is used in conjunction with a fully-differential pseudo-N-path filter design to create a design that has strong potential in the high-frequency bandpass domain. Both low-pass and high-pass N-path designs are examined theoretically and relative comparisons made of component and op-amp gain-sensitivity. Analysis by SWITCAP of component-sensitivity shows that the largest frequency-varying sensitivity is 0.064 dB per 1% component variation. A discrete prototype HP-two-path differential stray-insensitive filter was built as a test vehicle. Results are presented for a design with a bandpass center-frequency of two kHz and a bandwidth of 20 Hz. The clock feedthrough noise was shifted out of the passband by the use of z to z/sup -N/ transformation. Mirror frequency components were found to be about 55 dB below the signal level.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An 8-bit 2-ns monolithic DAC

An 8-bit resolution ultrahigh-speed monolithic digital-to-analog converter (DAC) is fabricated using super self-aligned process technology. In order to improve dynamic accuracy, which is determined by settling speed, clock feedthrough noise, and glitch, a number of circuit technologies are developed including a rise- and fall-time control switch driver, a low-noise flip-flop, and a differential buffer configuration. In addition, a chip assembly technology using a multilayer ceramic substrate is developed. The DAC exhibits a settling time to 8-bit accuracy of about 2 ns, a maximum conversion rate of 1 GHz, a glitch energy of 2 ps-V, and a 10-bit linearity error accuracy without trimming.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Simple formula for estimation of minimum clock-feedthrough error voltage

A simple approximating formula is derived for the prediction of clock-feedthrough noise in a switched-capacitor (SC) integrator. It can be used for estimating the achievable accuracy and dynamic range of SC circuits.