Clock Division Research Articles

A Mixed Approach for Clock Synchronization in Distributed Data Acquisition Systems.

Proper timing synchronization is important when data from sensors are acquired by different devices. This paper proposes a simple but effective solution for System on Chip (SoC) architectures that integrates a general-purpose Field Programmable Gate Array (FPGA) with a CPU. The proposed approach relies on a network synchronization protocol implemented in software, such as Network Time Protocol (NTP) or Precision Time Protocol (PTP), and uses the FPGA to generate a clock reference that is maintained in step with the synchronized system clock. The clock generated by the FPGA is obtained from the FPGA oscillator via appropriate fractional clock division. Clock drift is avoided via a software program that periodically compares the FPGA and the system counters, respectively, and adjusts the fractional clock divider in order to slightly adjust the FPGA clock frequency using a Proportional Integral controller. A specific implementation is presented on the RedPitaya platform, generating a 1 MHz clock in step with the NTP synchronized system clock. The presented system has been used in a distributed data acquisition system for fast transient recording in the neutral beam test facility for the ITER nuclear fusion experiment.

Accelerating Stochastic Computing Using Deterministic Halton Sequences

Deterministic approaches have recently been developed for accurate computation in stochastic computing (SC). They, however, suffer a long operation time. Fortunately, for applications that do not require completely accurate processing results, such as image processing, the time can significantly be reduced due to the better progressive precision in the bit-streams generated by these approaches. That means a computation can be terminated in time when its output accuracy is acceptable. Due to the fast convergence property of low-discrepancy sequences, we propose three deterministic Halton sequence (DHS)-based stochastic number generators (SNGs) for the first time by using, respectively, prime length, rotation, and clock division for accelerating computation in SC. Experimental results show that the proposed designs are more efficient than their counterparts. For multiplication, the proposed DHS-based designs perform up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$32\times $ </tex-math></inline-formula> faster than prior designs for a mean error of 0.1%. The speedup reaches <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$128\times $ </tex-math></inline-formula> for an edge detection algorithm. Three stochastic circuits are then designed by using the proposed DHS-based SNGs for the Bernsen binarization algorithm, which lead to more accurate results than existing designs at the same bit-stream length. Finally, the proposed designs show an excellent fault-tolerance against bit flipping errors.

Design of synchronous decimal counter using reversible Toffoli–Fredkin Netlist

Investigations in reversible computation have been one of the notable dimensions among the emerging research domains. Reversible circuits promise near-zero heat dissipation resulting in a considerable amount of literary proposals. This article proposes a reversible synchronous decimal counter using Toffoli and Fredkin gates. Decimal counter forms an important Boolean specification as they are used for clock generators, frequency dividers, clock division, integrated oscillation, etc. Although literature witnesses exhaustive research in reversible mod-2/4/8/16 counters, there is a void in the domain of reversible decimal counters. We propose three designs D1, D2, and D3. Design D1 and D2 are synchronous decimal up and down counters, respectively, using Toffoli Netlist. Design D3 is the integration of designs D1 and D2 using the Fredkin Gate array. The proposed designs have been checked using a state-of-the-art optimization algorithm in literature and the results reflect our design to be best optimized. Peer analysis reflects a summary of existing literary proposals exhibiting the uniqueness of the proposed designs.

Performing Stochastic Computation Deterministically

Stochastic logic performs computation on data represented by random bit-streams. The representation allows complex arithmetic to be performed with very simple logic, but it suffers from high latency and poor precision. Furthermore, the results are always somewhat inaccurate due to random fluctuations. In this paper, we show that randomness is not a requirement for this computational paradigm. If properly structured, the same arithmetical constructs can operate on deterministic bit-streams, with the data represented uniformly by the fraction of 1’s versus 0’s. This paper presents three approaches for the computation: relatively prime stream lengths, rotation, and clock division. Unlike stochastic methods, all three of our deterministic methods produce completely accurate results. The cost of generating the deterministic streams is a small fraction of the cost of generating streams from random/pseudorandom sources. Most importantly, the latency is reduced by a factor of $({1}/{2^{n}})$ , where $n$ is the equivalent number of bits of precision. When computing in unary, the bit-stream length increases with each level of logic. This is an inevitable consequence of the representation, but it can result in unmanageable bit-stream lengths. We discuss two methods for maintaining constant bit-streams lengths via approximations, based on low-discrepancy sequences. These methods provide the best accuracy and area $\times $ delay product. They are fast-converging and therefore offer progressive precision.

Agile Blocker and Clock Jitter Tolerant Low-Power Frequency Selective Receiver with Energy Harvesting Capability

In this article, a novel tunable, blocker and clock jitter tolerant, low power, quadrature phase shift frequency selective (QPS-FS) receiver with energy harvesting capability is proposed. The receiver’s design embraces and integrates (i) the baseband to radio frequency (RF) impedance translation concept to improve selectivity over that of conventional homodyne receiver topologies and (ii) broadband quadrature phase shift circuitry in the RF path to remove an active multi-phase clock generation circuit in passive mixer (PM) receivers. The use of a single local oscillator clock signal with a passive clock division network improves the receiver’s robustness against clock jitter and reduces the source clock frequency by a factor of N, compared to PM receivers using N switches (N≥4). As a consequence, the frequency coverage of the QPS-FS receiver is improved by a factor of N, given a clock source of maximum frequency; and, the power consumption of the whole receiver system can eventually be reduced. The tunable QPS-FS receiver separates the wanted RF band signal from the unwanted blockers/interferers. The desired RF signal is frequency down-converted to baseband, while the undesired blocker/interferer signals are reflected by the receiver, collected and could be energy recycled using an auxiliary energy harvesting device.

Investigation of optical clock division and demultiplexing based on a commercial lithium niobate‐intensity modulator

AbstractWe demonstrate and investigate a simple technique to realize multichannel optical clock division by using a commercial lithium niobate‐intensity modulator (LN‐IM). Optical clock division is achieved by controlling the driving and dc bias voltage of the LN‐IM. 20‐ to 10‐GHz optical clock division experiments of both single and double channel are implemented to verify the performance of the proposed optical clock divider. The phase noise of the extracted 10‐GHz optical clock is less than 95 dBc/Hz. The other function of this technique, demultiplexing of optical time division multiplexing (OTDM) signal is also demonstrated experimentally. The 20‐Gb/s PRBS OTDM signal is successfully demultiplexed to two 10 Gb/s with high quality. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:94–99, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26477

Phase spectrum algorithm for correction of time distortion in a wavelength demultiplexing analog-to-digital converter

An algorithm based on phase spectrum analysis is proposed that can be used to correct the timing distortion between the multiple parallel demultiplexed post-sampling pulse trains in wavelength demultiplexing analog-to-digital converters. The algorithm is theoretically presented and its operational principle is explained. The algorithm is then applied to two parallel demultiplexed post-sampling signals from a proof-of-principle system and fairly good results are obtained. This algorithm is potentially applicable in other opto-electronic hybrid systems where an interleaving and/or multiplexing mechanism is utilized, such as optical time-division multiplexing and optical clock division systems, photonic arbitrary waveform generators, and so on.

All‐optical clock division with simultaneous wavelength conversion using an optically injected Fabry‐Perot laser diode

AbstractThe authors propose and experimentally demonstrate a novel technique that uses a single Fabry‐Perot laser diode (FP‐LD) to perform simultaneous all‐optical clock division and wavelength conversion. By utilizing the nonlinear dynamical period‐one oscillation and the cross‐gain modulation effect of the light injection semiconductor laser, we achieve the all optical clock frequency division of 12.36 GHz to 6.18 GHz with simultaneous wavelength conversion from 1550.24 nm to 1545.91 nm. The phase noise of the extracted optical clock is less than −105 dBc/Hz. It was empirically found that the best clock division and wavelength conversion occurred when the injected signal power was approximately 2–2.5 times as the injected probe light power, and the range of optimum wavelength detuning was about from −0.01 nm to 0.06 nm. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2428–2431, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24626

Synchronisation and chaos in a laser diode driven by a resonant tunnelling diode

The authors report on a hybrid integration of a resonant tunnelling diode laser diode driver configuration that can operate as a self-oscillating circuit, and when externally perturbed shows regions of frequency division and frequency multiplication, quasi-periodic and chaotic oscillations, both in the optical and electrical outputs. The authors also demonstrate that this optoelectronic circuit is well described as a Liénard&apos;s oscillator. The synchronisation capabilities of the circuit have potentially novel functions for optical communications systems including clock recovery, clock division and data encryption.

Control of period-one oscillation for all-optical clock division and clock recovery by optical pulse injection driven semiconductor laser

The period-one oscillation produced by an external optical pulse injection driven semiconductor laser is applied to clock recovery and frequency division. By adjusting the repetition rate or injection power of the external injection optical pulses to lock the different harmonic frequencies of the period-one state, the clock recovery and the frequency division (the second and third frequency divisions) are achieved experimentally. In addition, in frequency locking ranges of 2 GHz and 1.9 GHz, the second and third frequency divisions are obtained with the phase noise lower than -100 dBc/Hz, respectively. Our experimental results are consistent well with the numerical simulations.

Subharmonic Optoelectronic Oscillator

I propose and demonstrate a subharmonic optoelectronic oscillator (SH-OEO), which contains a frequency divider in the feedback loop and performs optical clock division, prescaled optical clock recovery, and optical time-division demultiplexing in the absence of subharmonic tones in the input signals. Also, I propose a scheme that achieves divide-by-two optical clock recovery and serial-to-parallel conversion of optical data signals simultaneously using a polarization modulator-based SH-OEO.

Optical clock division based on dual-wavelength mode-locked semiconductor fiber ring laser

We have reported the optical clock division utilizing an injected mode-locked fiber ring laser incorporating semiconductor optical amplifiers (SOAs) and a dispersion compensation fiber (DCF). The clock division is mainly caused by the modulation competition between two wavelength components while both of them satisfy the harmonic mode-locking condition at the newly generated frequency. Stable second, third, and fourth clock divisions are obtained by properly adjusting the polarization controllers inside the ring cavity when a 10-GHz clock signal without any sub-harmonic frequency component is injected into the cavity. The radio-frequency spectra show good qualities of the obtained clock division trains.

A Wide-Range Mixed-Mode DLL for a Combination 512 Mb 2.0 Gb/s/pin GDDR3 and 2.5 Gb/s/pin GDDR4 SDRAM

A mixed-mode delay-locked loop (MDLL) for a 512 Mb graphics SDRAM is presented in this paper. The MDLL extends its lock range into the gigahertz realm by applying clock division and analog phase generation (APG). The divided clock from the MDLL is used for clocking logic and tracking deterministic access latency in the SDRAM. A short discussion of some of the side effects and advantages of using a divided, multi-phase clock for logic operation is presented. A low-power clock distribution network (CDN) based on the presented MDLL is also disclosed. Fabricated in a 1.5 V 95 nm triple-metal CMOS process, the MDLL achieves a measured RMS jitter of 4.6 ps and peak-to-peak jitter of 38 ps at GDDR4 mode with a 1 GHz clock. Power consumption for the entire MDLL-based CDN is 107 mW at 800 MHz and 1.5 V.

Frequency-tunable all-optical clock division using semiconductor laser subjected to external optical injection

All-optical time division was obtained in the frequency range from 9.0GHz to 19.8GHz. Nonlinear dynamics of a Fabry-Perot laser diode subjected to external optical injection is applied for all-optical clock division. The research results indicate that semiconductor laser subjected to external light injection performs period-one oscillation. We obtain the clock division of the signal pulses when the second harmonic frequency of the period-one oscillation approaches the repetition rate of the signal pulse, and the second harmonic and the fundamental frequency of the period-one oscillation were locked by the signal pulses simultaneously. Numerical simulation was performed on the all-optical time division with signal pulse injection using the rate equation of the semiconductor laser. The simulation result is in good agreement with the experiment. Phase noise level of the divided clock is observed to be smaller than -90 dBc/Hz over a frequency detuning range of 1.5GHz by changing the repetition rate of signal pulses under the fixed wavelength detuning value and input signal pulse power.

基于法布里-珀罗半导体激光器实现高重复频率光脉冲的时钟分频

基于法布里-珀罗半导体激光器实现高重复频率光脉冲的时钟分频

Clock division with optical injection semiconductor laser

Clock division with optical injection semiconductor laser

Pitfalls of Hierarchical Fault Simulation

Certain circuit structures, such as self-loop, asynchronous reset, and clock division, may not be visible in a hierarchical (mixed) simulation system. Since the simulator does not know about their existence, it cannot cope with them like it normally would in a flat circuit. If this leads to a logic-simulation problem, users can usually discover them easily during the validation process. However, if it only causes fault-simulation inaccuracy, it is hard to find the problem. In this paper, we show examples illustrating their existence. The examples negate an assumption that has been used in many papers on mixed-mode simulation. The examples have been abstracted from real industrial designs of microprocessors.

Optical clock recovery and clock division at 20 Gb/s using a tunable semiconductor fiber ring laser

Optical clock recovery and clock division is demonstrated from a pseudo-data pattern at 20 Gb/s, using a semiconductor optical amplifier fibre ring laser. The ring laser is capable of generating 4.7 ps pulses at 20 GHz repetition rate and less than 3 ps pulses at the divided clock frequencies of 10 and 5 GHz, over a 16 nm tuning range. The effect of the input data pattern on the recovered clock signal is investigated. The extinction ratio of the recovered clock signal to the clock sub-harmonics was found to be as high as 40 dB despite the long series of consecutive zeros of input pattern.

Optical control of period doubling in a gain-switched Fabry–Perot laser diode and its application in all-optical clock division

Optical injection is shown to be an effective means to suppress or to enhance period doubling of a gain-switched laser diode. The role that the injection plays depends on whether the laser resonance frequency is larger or smaller than half the modulation frequency. Reversible control of period doubling has been demonstrated experimentally using a modulated injection source. An injection power as low as 0.03 mW has been used to control the output pulse repetition frequency of the slave laser. The response time is measured to be shorter than 100 ps. The phenomenon has been applied successfully for use in all-optical clock frequency division. Replacing the electrical modulation with an input clock signal at 19.6 GHz, a frequency-halved output clock with a remarkable low-level phase noise (−87.7 dBc/Hz at 10 kHz offset frequency) has been obtained. The change in the phase noise level is observed to be smaller than 1 dB over a frequency detuning range of 400 MHz.

All optical clock division and multiplication by injection mode-locked laser based on SOA

Optical clock division and multiplication were realized with an injection mode-locked fiber ring laser based on semiconductor optical amplifier SOA owing to the relatively long recovery time of carriers in SOA and the rational harmonic mode-locking. Second frequency division and 1.5th frequency multiplication of 10 GHz , second and 3 4 th frequency division of 20 GHz optical pulse trains were realized, respectively, in the experiment.