Clock Distribution System Research Articles

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface

This paper describes a tri-modal asymmetric bidirectional differential memory interface that supports data rates of up to 20 Gbps over FR4 PCB channels while achieving power efficiency of 6.1 mW/Gbps at full speed. The interface also accommodates single-ended standard DDR3 and GDDR5 signaling at 1.6-Gbps and 6.4-Gbps operations, respectively, without package change. The compact, low-power and high-speed tri-modal interface is enabled by substantial reuse of the circuit elements among various signaling modes, particularly in the wide-band clock generation and distribution system and the multi-modal driver output stage, as well as the use of fast equalization for post-cursor intersymbol interference (ISI) mitigation. In the high-speed differential mode, the system utilizes a 1-tap transmit equalizer during a WRITE operation to the memory. In contrast, during a memory READ operation, it employs a linear equalizer (LEQ) with 3 dB of peaking as well as a calibrated high-speed 1-tap predictive decision feedback equalizer (prDFE), while no transmitter equalization is assumed for the memory. The prototype tri-modal interface implemented in a 40-nm CMOS process, consists of 16 data links and achieves more than 2.5 × energy-efficient memory transactions at 16 Gbps compared to a previous single-mode generation.

Modeling and Filtering Double-Frequency Jitter in One-Way Master–Slave Chain Networks

One-way master-slave (OWMS) chain networks are widely used in clock distribution systems due to their reliability and low cost. As the network nodes are phase-locked loops (PLLs), double-frequency jitter (DFJ) caused by their phase detectors appears as an impairment to the performance of the clock recovering process found in communication systems and instrumentation applications. A nonlinear model for OWMS chain networks with P+1 order PLLs as slave nodes is presented, considering the DFJ. Since higher order filters are more effective in filtering DFJ, the synchronous state stability conditions for an OWMS chain network with third-order nodes are derived, relating the loop gain and the filter coefficients. By using these conditions, design examples are discussed.

Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks

A dual-edge sense amplifier flip-flop (DE-SAFF) for resonant clock distribution networks (CDNs) is proposed. The clocking scheme used to enable dual-edge triggering in the proposed SAFF reduces short circuit power by allowing the precharging transistors to be switched on only for a portion of the clock period. The extracted circuit layout of the proposed DE-SAFF has been simulated in STMicroelectronics 90 nm technology with a resonant clock signal at a frequency of 500 MHz. Simulation results show correct functionality of the flip-flip under process, voltage and temperature variations. Two low-power clocking techniques, the dual-edge triggering method and the emerging resonant (sinusoidal) clocking technique, have been combined to enable further power reduction in the CDN. Modelling the resonant clock distribution system with the proposed flip-flop illustrates that dual-edge triggering can achieve up to 58% reduction in the power consumption of resonant clock networks.

Fully CMOS-Compatible On-Chip Optical Clock Distribution and Recovery

Clock distribution in the multi-gigahertz range is getting increasingly difficult due to more stringent requirements for skew and jitter on one hand and the deteriorating supply voltage integrity and process variation on the other hand. Global clock network, especially in nanometer CMOS designs with ever increasing die sizes, has become a prominent performance limiter. A potential alternative to traditional interconnect technology for achieving clock distribution beyond 10 GHz while maintaining required skew and jitter budgets is using on-chip optical interconnects. A practical on-chip optical clocking system must be CMOS compatible in order to provide attractive cost effectiveness for system level integration and ease of manufacturing. This paper presents the design of a fully CMOS compatible optical clock distribution and recovery system in a 3.3 V, 0.35- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex> </formula> m CMOS process. Experimental results from the test chip prove the feasibility of providing optical-electrical interface in devices and circuits in a fully CMOS compatible manufacturing environment. Although the test chips were designed in a mature CMOS process technology and the measured performance is low, the test chips demonstrated the feasibility of on-chip optoelectronic integration with fully CMOS compatible process. On-chip optical clock distribution is one of the natural applications of fully CMOS compatible on-chip optical interconnect technology.

The OPERA global readout and GPS distribution system

OPERA is an experiment dedicated to the observation of ν μ into ν τ oscillations in appearance mode using a pure ν μ beam (CNGS) produced at CERN and detected at Gran Sasso. The experiment exploits a hybrid technology with emulsions and electronics detectors. The OPERA readout is performed through a triggerless, continuously running, distributed and highly available system. Its global architecture is based on Ethernet-capable smart sensors with microprocessing and network interface directly at the front-end stage. A unique interface board is used for the full detector reading out ADC-, TDC- or Controller-boards. All the readout channels are synchronized through a GPS-locked common bidirectional clock distribution system developed on purpose in a PCI format. It offers a second line to address all channels and the off-line synchronization with the CNGS to select the events.

Fully Connected PLL Networks: How Filter Determines the Number of Nodes

Synchronization plays an important role in telecommunication systems, integrated circuits, and automation systems. Formerly, the masterslave synchronization strategy was used in the great majority of cases due to its reliability and simplicity. Recently, with the wireless networks development, and with the increase of the operation frequency of integrated circuits, the decentralized clock distribution strategies are gaining importance. Consequently, fully connected clock distribution systems with nodes composed of phase‐locked loops (PLLs) appear as a convenient engineering solution. In this work, the stability of the synchronous state of these networks is studied in two relevant situations: when the node filters are first‐order lag‐lead low‐pass or when the node filters are second‐order low‐pass. For first‐ order filters, the synchronous state of the network shows to be stable for any number of nodes. For second‐order filter, there is a superior limit for the number of nodes, depending on the PLL parameters.

Reachability of the synchronous state in a mutually connected PLL network

Second-order phase locked loops (PLLs) are devices that are able to provide synchronization between the nodes in a network even under severe quality restrictions in the signal propagation. Consequently, they are widely used in telecommunication and control. Conventional master–slave (M–S) clock-distribution systems are being replaced by mutually connected (MC) ones due to their good potential to be used in new types of application such as wireless sensor networks, distributed computation and communication systems. Here, by using an analytical reasoning, a nonlinear algebraic system of equations is proposed to establish the existence conditions for the synchronous state in an MC PLL network. Numerical experiments confirm the analytical results and provide ideas about how the network parameters affect the reachability of the synchronous state. The phase-difference oscillation amplitudes are related to the node parameters helping to design PLL neural networks. Furthermore, estimation of the acquisition time depending on the node parameters allows the performance evaluation of time distribution systems and neural networks based on phase-locked techniques.

Mutually connected phase-locked loop networks: dynamical models and design parameters

Distribution of timing signals is an essential factor for the development of digital systems for telecommunication networks, integrated circuits and manufacturing automation. Originally, this distribution was implemented by using the master–slave architecture with a precise master clock generator sending signals to phase-locked loops (PLL) working as slave oscillators. Nowadays, wireless networks with dynamical connectivity and the increase in size and operation frequency of the integrated circuits suggest that the distribution of clock signals could be more efficient if mutually connected architectures were used. Here, mutually connected PLL networks are studied and conditions for synchronous states existence are analytically derived, depending on individual node parameters and network connectivity, considering that the nodes are nonlinear oscillators with nonlinear coupling conditions. An expression for the network synchronisation frequency is obtained. The lock-in range and the transmission error bounds are analysed providing hints to the design of this kind of clock distribution system.

Wireless Clock Distribution System Using an External Antenna

A compact wireless clock distribution system with an external planar array antenna which can provide phase and amplitude distributions suitable for synchronizing circuits over a 35-mm diameter circular area at 3 GHz is proposed. The computer systems using this wireless clock distribution can have a comparable form factor as systems using a conventional clock network. The system is composed of a transmitter with an off-chip antenna, and multiple clock receivers with on-chip antennas distributed over an integrated circuit or over multiple ICs. The transmitter, which was fabricated in a 130-nm CMOS process, generates a 17-GHz clock signal which is periodically amplitude-modulated in order to initialize all of the receivers' clock dividers to the same clock phase. Besides increasing the synchronization area, this wireless approach effectively eliminates the dispersion problem in conventional clock networks. The experimental results presented show the feasibility and potential benefits of the wireless clock distribution system using an external antenna.

Dual-edge triggered storage elements and clocking strategy for low-power systems

This paper describes the classification, detailed timing characterization, evaluation, and design of the dual-edge triggered storage elements (DETSE). The performance and power characterization of DETSE includes the effect of clocking at halved clock frequency and impact of load imposed by the storage element to the clock distribution network. The presented analysis estimates the timing penalty and power savings of a system based on DETSE, and gives design guidelines for high-performance and low-power application. In addition, the paper presents a class of dual-edge triggered flip-flops with clock load, delay, and internal power consumption comparable to the fastest single-edge triggered storage elements (SETSE). Our simulated results show that by halving the clock frequency, dual-edge clocking strategy can save about 50% of the power consumed by the clock distribution network, and relax the design of clock distribution system, while paying virtually no penalty in throughput.

Clock Generation and Distribution for the 130-nm Itanium¯ 2 Processor With 6-MB On-Die L3 Cache

The clock generation and distribution system for the 130-nm Itanium 2 processor operates at 1.5 GHz with a skew of 24 ps. The Itanium 2 processor features 6 MB of on-die L3 cache and has a die size of 374 mm/sup 2/. Fuse-based clock de-skew enables post-silicon clock optimization to gain higher frequency. This paper describes the clock generation, global clock distribution, local clocking, and the clock skew optimization feature.

Modeling diffraction in free-space optical interconnects by the mode expansion method.

Free-space optical interconnects (FSOIs), made up of dense arrays of vertical-cavity surface-emitting lasers, photodetectors and microlenses can be used for implementing high-speed and high-density communication links, and hence replace the inferior electrical interconnects. A major concern in the design of FSOIs is minimization of the optical channel cross talk arising from laser beam diffraction. In this article we introduce modifications to the mode expansion method of Tanaka et al. [IEEE Trans. Microwave Theory Tech. MTT-20, 749 (1972)] to make it an efficient tool for modelling and design of FSOIs in the presence of diffraction. We demonstrate that our modified mode expansion method has accuracy similar to the exact solution of the Huygens-Kirchhoff diffraction integral in cases of both weak and strong beam clipping, and that it is much more accurate than the existing approximations. The strength of the method is twofold: first, it is applicable in the region of pronounced diffraction (strong beam clipping) where all other approximations fail and, second, unlike the exact-solution method, it can be efficiently used for modelling diffraction on multiple apertures. These features make the mode expansion method useful for design and optimization of free-space architectures containing multiple optical elements inclusive of optical interconnects and optical clock distribution systems.

Over GHz low-power RF clock distribution for a multiprocessor digital system

Conventional interconnections for digital clock distribution pose a severe power consumption problem for GHz clock distribution due to transmission line losses. Therefore, we have proposed an RF clock distribution (RCD) scheme for high-speed digital applications, in particular a multiprocessor system using global clocking. This paper first reports system power and signal integrity analysis results including skew, jitter, impedance mismatch, and noise for RF clock distribution,especially in the GHz range. Based on this analysis, a novel signal integrity design methodology for RF clock distribution systems is proposed. The clock skew created by process parameter variations are modeled and predicted. The system comprises a RF clock transmitter as a clock generator, an H-tree with junction couplers as a clock distributing network and a RF receiver as a digital clock-recovery module. Flip-chip interconnections for the chip-to-substrate assembly and 0.35 /spl mu/m TSMC CMOS technology for the RF clock receiver are assumed. EMI analysis for 2 GHz 16-node-board-level RF clock distribution networks is conducted using 3D full-wave EM simulation. Finally, the RCD as a low power and high performance clocking method is demonstrated using HP's Advanced Design System (ADS) simulation, considering microwave frequency interconnection models and process parameter variations. In addition, test vehicles for both 2 GHz 16-node and 5 GHz 64-node board-level RF clock distribution networks were implemented and measured using thin, low-loss, and low permittivity Rogers/sup /spl reg// RO3003 high-frequency organic substrate.

Surface emitting lasers by selective area epitaxy for optical clock distribution

The integration of a laser diode with a passive waveguide distribution network for use in an optical clock distribution system is demonstrated. The integration concept is demonstrated by utilising selective area epitaxy and etched surface gratings to create active and passive components for signal generation and distribution.

Optical reflectivity of micromachined {111}-oriented silicon mirrors for optical input - output couplers

In this work, bulk-micromachined -oriented silicon mirrors at have been fabricated in 20 wt% KOH solution at various temperatures and characterized with single-mode fibers (10/125 and 5/125). In fabricating the mirrors, the etch rate of the (100) silicon surface was widely varied from 5.3 to as the processing temperatures were varied from 40 to C. In spite of the tremendous variation of etch rate, the measured reflectivities of the mirrors showed fairly stable values of 63.7 - 58% at 1330 nm and 55.4 - 57.7% at 1550 nm. This paper describes the silicon mirror processing conditions, measured reflectivities, reflected beam profiles, and a prototype integrated optical I - O coupler with the realized mirrors. The results obtained from this work show that optical I - O couplers with mirrors on conventional (100)-oriented silicon wafers are feasible, enabling us to envisage a synchronized optical clock distribution system as well as a distributed remote optical sensing system with low manufacturing cost.

The clock and control signal distribution system for the NA48 experiment

In the NA48 experiment at CERN, several detector subsystems located at distances of up to 200 m between each other produce data on a continuous basis and feed them into pipelines. Triggers are produced after variable delay times by two different systems for charged and for all-neutral kaon decays. To allow the retrieval of the corresponding data from the various subsystems and their merging into complex events by means of timestamps, a special, highly stable global clock distribution system has been developed. The design principles and the setup of the clock system are described and results for clock stability monitoring and automated correction of the signal transmission speed are reported.

Tolerant design of a planar-optical clock distribution system

This paper describes a tolerant design for a planar optical clock distribution system. It uses a correction optics that consists of a sequence of lenses at regular distances similar to a lens waveguide. The correction optics greatly reduces detrimental effects due to the influence of substrate tolerances, variations of the wavelength and the temperature on the light propagation. Ray-tracing simulations are used to analyze the performance of the corrected system. Practical considerations for the design of the overall system are presented.

Optical matrix for clock distribution and synchronous operation in two-dimensional array devices

A scheme to generate an optical matrix from a mode-locked Nd:YAG laser has been theoretically explored and experimentally demonstrated. The matrix consists of highly synchronized and sequentially delayed optical pulses suitable for use with two-dimensional array optoelectronic devices and clock distribution system. The output pulses have the same state of polarization and no timing jitter is produced among the elements. Encoded outputs have been generated from the matrix using a set of photomasks. This technique can be applied to high-speed optical parallel processing.

Board level H-tree optical clock distribution with substrate mode holograms

This paper describes a design for a board-level free-space optical clock distribution system implemented with substrate mode holograms. The design uses an H-tree distribution scheme to balance propagation delays for different clock paths on each board. The H-component provides four diffracted output beams with /spl sim/11% efficiency for each output, and the required laser power for the clock distribution system is calculated. To provide 80 clock fan-out signals for a five-board system, the clock distribution system requires 4.7 mW of laser power with 10 /spl mu/W of received optical power at each node. The misalignment analysis for the free-space optical system is presented and design considerations are given. The factors causing clock skew and timing jitter in the optical clock distribution system are also examined. An experimental system was demonstrated with a 622-MHz clock signal distributed with 36 ps of timing jitter and less than 10 ps of clock skew. >

An integrated CMOS 0.15 ns digital timing generator for TDC's and clock distribution systems

This paper describes the architecture and performance of a new high resolution timing generator used as a building block for Time to Digital Converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with sub-gate delay resolution to be implemented in a standard digital CMOS process. The TDC function is implemented by storing the state of the timing generator signals in an asynchronous pipeline buffer when a hit signal is asserted. The clock alignment function is obtained by selecting one of the timing generator signals as an output clock. The proposed timing generator has been mapped into a 1.0 /spl mu/m CMOS process and a RMS error of the time taps of 48 ps has been measured with a bin size 0.15 ns. Used as a TDC device a RMS error of 76 ps has been obtained. A short overview of the basic principles of major TDC and timing generator architectures is given to compare the merits of the proposed scheme to other alternatives.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>