Design Of class-F Power Amplifier Research Articles

Modified Class-F power amplifier design with fundamental frequency output impedance load

A modified Class-F power amplifier with medium output power at 433 MHz was designed, simulated and implemented in this paper. The design process used a load condition of 1) output impedance of the amplifier at the fundamental frequency, 2) short-circuit loads at the even harmonics and 3) open-circuit loads at the odd harmonics. By biasing the circuit to be a typical Class-F, the circuit yielded moderate efficiency as the load condition was different from the optimum one. By strongly biasing the circuit toward that of Class-A, the load condition approached the optimum, but the circuit still yielded moderate efficiency due to the low efficiency nature of a Class-A amplifier. By proper choice of the operating point in Class-AB, a prototype circuit, with 9 dBm input power, yielded a maximum PAE of 68.5% with output power 21.8 dBm. Furthermore, at 11 dBm input power, the prototype yielded a better PAE 79.6% with 23.2 dBm output power. Our design procedure did not need expensive load-pull equipment.

A high-efficiency continuous class-F power amplifier design using simplified real frequency technique

The fourth-generation (4G) wireless communication has been deployed in many countries. However, there are still some problems such as spectrum crisis due to the increase of wireless mobile devices and servicing. Therefore, the fifth-generation (5G) communication system will be employed at some different spectrum other than 4G frequency band. The radio frequency power amplifier (RFPA) is the key component of the 5G system. In this paper, a broadband continuous class-F (CCF) RFPA is designed for the 5G frequency band from 3.3-4.3 GHz. The input and output matching network are designed using the simplified real frequency technique (SRFT). Using a 10W GaN CGH40010F Cree device, the efficiency of the RFPA achieved greater than 70.7% for the whole frequency band with a maximum of 81.5%. The output power and the gain are more than 40 dBm and 10 dB respectively

Seamless Integration of Active Antenna With Improved Power Efficiency

Loss reduction to improve the power efficiency in active integrated antenna (AIA) is a key design drive. This paper first analyzes the loss mechanism in a convention AIA structure. A new integration scheme of a GaN power amplifier (PA) transistor with an antenna without using any output matching network (OMN) and harmonic tuning network (HTN) is then proposed to construct a seamlessly integrated AIA. This is achieved by a novel design of a slot antenna with optimized input impedance at its fundamental frequency as well as for harmonic tuning, which essentially absorbs the OMN and HTN functions in the conventional Class-F power amplifier design. By eliminating these passive networks between the transistor and the antenna, the associated insertion and mismatch losses as well as the overall circuit size are reduced. For verification, two prototypes are designed, fabricated and measured, one with the integrated design and the other with a conventional design for comparison. Both AIAs operate between 3.4 and 3.6 GHz. Experimental results show that the power-added efficiency (PAE) of the seamlessly integrated AIA is over 52% within the operating band. Compared with the conventional cascaded design of a PA and an antenna, the PAE is improved by 14.2%.

High Efficiency 2.4 GHz CMOS Two Stages Class-F Power Amplifier for Wireless Transmitters

A design of CMOS class-F power amplifier (PA) at 2.4-GHz for wireless transmitters is presented. The class-F PA design is implemented by using 0.13-μm CMOS process. The proposed class-F PA employs cascade topology. The transistor’s on resistance is decreased by designing the transistors in parallel. Therefore, the efficiency is increased. The first stage is a common-source driver stage is biased in a class-AB to provide sufficient input voltage swing for the amplifier stage, while the amplifier stage is biased in cut-off region. Therefore, the transistor can operate as a switching-mode for high efficiency. The simulation results show that the power added efficiency (PAE) of 60% is obtained at 1.3 V power supply and the PA delivers 12 dBm output power. The chip area is 0.66 mm². Keywords: Cascade, class F, power added efficiency, power amplifier, wireless, output power.

High Efficiency Class-F Power Amplifier Design

High Efficiency Class-F Power Amplifier Design

Experimental class-F power amplifier design using computationally efficient and accurate large-signal pHEMT model

This paper presents an experimental high-efficiency class-F power amplifier (PA) design, which integrates Rhodes's efficient low-pass matching network topology with the charge conservative, robust, and accurate WREN/COBRA nonlinear pseudomorphic high electron-mobility transistor (pHEMT) model for optimal drain efficiency. Large-signal model verification is undertaken where one-tone, load-pull, and wireless code-division multiple-access baseband time-domain tests are compared for simulated and experimental cases. Following a detailed theoretical analysis, a class-F matching network is proposed that suppresses the necessary load harmonics and delivers maximum drain efficiency. Utilizing the GaAs pHEMT model in computer-aided design, a microstrip matching network layout was generated and built at 2 GHz. The drain efficiency recorded for the first-pass effort was 70.5% with the use of no post-fabrication circuit tuning. Excellent agreement is also observed between the PAs simulated and measured performance, thus highlighting the advantages of an accurate device model in PA design.

On the class-F power amplifier design

Power-amplifier class-F operation is investigated and revised, evidencing the fundamental importance of the harmonic-generating mechanism and the limitations imposed by the device input and output nonlinearities on the ideal class-F behavior. Closed-form expressions are derived for the major design quantities, together with the optimum fundamental and third-harmonic loading of the active device. A design procedure, making use of the derived expressions, is presented and the deviations from the ideal behavior are discussed. Sample designs, making use of a full nonlinear device model and commercial analysis software, are carried out to demonstrate the effectiveness of the analysis and the design procedure. It is shown, both analytically and using commercial nonlinear simulations, that blind application of commonly used, idealized class-F harmonic terminations can cause unexpected detrimental results. ©1999 John Wiley & Sons, Inc. Int J RF and Microwave CAE 9: 129–149, 1999