Class AB Mode Research Articles

Ultra-low-power super class-AB adaptive biasing operational transconductance amplifier with enhanced gain for biomedical applications

The operational transconductance amplifier (OTA) proposed in this article is a bulk-driven (BD), single-stage, super-class-AB, adaptive biasing, functioning in the subthreshold region (ST) with an enormously low power supply of ± 0.25 V, providing high-gain. The input core of the OTA circuit is composed of adaptively biased BD differential input pairs based on flipped voltage follower (FVF), which drive in class-AB mode with a partial positive feedback (PPF) approach. The circuit additionally employs FVF and self-cascode (SC)-based low-power current mirror loads at its output to obtain significantly high gain and unity gain frequency. In addition, using adaptive loads based on source-degenerated metal oxide semiconductor (MOS) resistors raises dynamic current more efficiently, consequently improving the slew rate and unity gain frequency (UGF) without drawing additional power. Employing the cadence spectre tool and the UMC 0.18 μm complementary metal oxide semiconductor (CMOS) process technology, the designed OTA has been simulated. The simulation outcomes substantiate that the amplifier provides high open loop DC gain of 75 dB, 18.75 kHz UGF with a phase margin of 63.93º, and input-referred noise (IRN) of 0.734 µV/Hz0.5 at 1 kHz frequency. The proposed OTA consumes just 60.15 nW of power. The performance results confirmed that the proposed OTA circuit is appropriate in biomedical applications.

CMOS Voltage-Controlled Oscillator with Complementary and Adaptive Overdrive Voltage Control Structures

This paper displays a voltage-controlled oscillator (VCO) with high performance implemented in 0.18 µm CMOS. The proposed CMOS VCO adopts a current-reused method, analog coarse and fine tuning mechanisms, and an adaptive overdrive voltage control structure to increase the overall performance, such as the power dissipation, phase noise, and tuning range, and has a robust start-up condition. The current-reused complementary structure with higher transistor transconductances is to save power consumption; the analog coarse and fine tuning mechanisms are to effectively widen the tuning range; and the adaptive overdrive voltage control technique is to change the transconductances of the transistors to improve power consumption by reasonably biasing the gate and body terminals in a class-AB mode to adjust the threshold voltage of the NMOS transistors. The proposed CMOS VCO adopts the class-AB mode to improve the overall performance and the start-up condition. The figure-of-merit (FOM) and FOM with tuning range (FOMT) are used in evaluating the CMOS VCO performance. The measured phase noise at 1 MHz and 10 MHz offsets is –130.34 dBc/Hz and –150.96 dBc/Hz at the 3.38 GHz operating frequency, respectively. The proposed CMOS VCO has a tuning range between 2.85 and 3.62 GHz corresponding to 23.8% for the fifth-generation (5G) wireless communication applications. The proposed CMOS VCO core using a 1.4-V supply consumes 7.5 mW DC power. The FOMs and FOMTs at 1- and 10-MHz offsets are −192.2, −192.8, −199.7, and −200.3 dBc/Hz, respectively, from the 3.38 GHz output frequency.

Bulk Cum QFG-Driven FVF Double Recycling Current Mirror Subthreshold OTA Based CCII+ Cell and Applications

This paper presents a low-voltage low-power second generation CCII+ cell using bulk-driven FVF class AB mode operated double recycling current mirror OTA. The OTA is used in the input core of CCII+ cell utilizes bulkcum Quasi Floating Gate (QFG)-based voltage to current converter and Partial Positive Feedback (PPF) to enhance the performance of the circuit. The circuit permits closely railto- rail input common mode range, high output current drive capability with low dual power supply of ± 0.25 V. This circuit produces low input referred noise of 1.65 μV/sqrt Hz, dissipates ultra-low power of 342 nW and is suitable for lowfrequency applications, such as bio-signal processing. Further, to validate this design, a MISO type voltage mode biquadratic filter and voltage mode two phase quadrature oscillator are currently being implemented using this CCII+ cells. The circuit is simulated in tanner EDA tools using 180 nm n-tub CMOS process technology with low bias current of 18 nA.

DC-10 GHz broadband linear power amplifier for 5G applications using 180 nm CMOS technology

This article suggests a broadband linear power amplifier (PA) for DC-10 GHz for Fifth-generation (5G) and multi-standard applications using 180 nm CMOS technology. The suggested radio frequency power amplifier is appropriate for wideband LTE, IoT, WSN, multi-standard, and 5G radio frequency transmitters. T-coil peaking and bridged-shunt-series peaking amplifiers are used for bandwidth extension and gain flatness. Also, the interstage matching inductors between common source and common gate transistors are applied to improve radio frequency achievement. The suggested PA consists of four stages as follows; input stage, two stages using the T-coil peaking technique, and the last stage utilizing bridged-shunt-series peaking topology. The input stage is a complementary current reuse (CCR) common gate with active shunt feedback (SFB) architecture. It is utilized to extend the matching of RF input impedance with agreeable linearity and power gain at little power consumption. The second stage works in class-C operation to enhance the efficiency and reduce DC power consumed whereas the class-AB mode is utilized in the third and fourth stages to improve the output power. The suggested PA obtains a peak constant power equal to 14.25 dBm, a maximum Power-Added-Efficiency (PAE) of 16 %, and a peak gain equal to 22 dB. The proposed power amplifier dissipates a DC power of 80 mW. The die size of the proposed power amplifier equals 1mm2, whereas the total chip size includes the pads is 1.62mm2.

Super-Gain-Boosted AB-AB Fully Differential Miller Op-Amp With 156dB Open-Loop Gain and 174MV/V MHZ pF/μW Figure of Merit in 130nm CMOS Technology

A fully differential Miller op-amp with a composite input stage using resistive local common-mode feedback and regulated cascode transistors is presented here. High gain pseudo-differential auxiliary amplifiers are used to implement the regulated cascode transistors in order to boost the output impedance of the composite input stage and the open-loop gain of the op-amp. Both input and output stages operate in class AB mode. The proposed op-amp has been simulated in a 130nm commercial CMOS process technology. It operates from a 1.2V supply and has a close to rail-to-rail differential output swing. It has 156dB DC open-loop gain and 63MHz gain-bandwidth product with a 30pF capacitive load. The op-amp has a DC open-loop gain figure of merit $FOM_{AOLDC}$ of 174 (MV/V) MHz pF/ $\mu \text{W}$ and large-signal figure of merit $FOM_{LS} $ of 3(V/ $\mu \text{s}$ ) pF/ $\mu \text{W}$ .

Subthreshold biased enhanced bulk-driven double recycling current mirror OTA

This paper presents a single-stage bulk-driven double recycling low-voltage low-power operational transconductance amplifier (OTA) operating in subthreshold region. The proposed OTA utilizes double recycling topology and provides enough open loop voltage gain, slew rate, and unity gain frequency (UGF). The flipped voltage follower-based adaptively biased input differential pair working in class AB mode has ensured dynamic current boosting and increased slew rate. Further, the proposed OTA has utilized partial positive feedback to mitigate some of the performance reduction caused by the bulk-driven topology. The simulation results of the proposed OTA have ensured open loop gain of 79.5 dB, UGF of 37.1 kHz, and phase margin of 64°. It operates with dual power supply of ± 0.25 V and consumes low power of 60 nW. These performance parameters validate its usefulness for LV, LP and low-frequency applications. The process, voltage, and temperature variation effects on low-frequency voltage gain, UGF, and phase margin of the proposed OTA has also been investigated with process corner simulations. The proposed OTA is designed and simulated in UMC 180 nm standard n-tub bulk CMOS process technology utilizing Tanner EDA tools.

Computer‐aided design methodology for linearity enhancement of multiwatt GaN HEMT amplifiers using multiple parallel devices

This article presents a design methodology for linearizing GaN HEMT amplifiers based on splitting a large FET into multiple parallel FETs with same total gate periphery and by biasing them individually. By varying the biases, the magnitude and the phase of the IMD3 components at the output of FET changes. A detailed simulation methodology using commercial microwave CAD software is presented. Simulation results show that by biasing one device in Class AB and other(s) in deep Class AB mode, IMD3 components of parallel FETs can be made out of phase to each other leading to cancellation and improvement in linearity. Three prototype circuits were simulated using (a) a single 5 mm FET (1 × 5 mm), (b) two parallel 2.5 mm FETs (2 × 2.5 mm), and (c) four parallel 1.25 mm FETs (4 × 1.25 mm), for a total gate periphery of 5 mm, over the frequency range of 0.8 to 1.0 GHz. IMD3 improvement up to 20 dBc was achieved with the 4 × 1.25 mm circuit when the FET biases were optimized. Measurement results show improvement in linearity up to 20 dBc for 4 × 1.25 mm circuit. The proposed method improves linearity without a substantial penalty on the power consumption and is straightforward to implement.

First demonstration of RF N-polar GaN MIS-HEMTs grown on bulk GaN using PAMBE

Nitrogen polar (N-Polar) GaN high-electron mobility transistors (HEMT) targeting high efficiency in millimeter wave power amplification applications were fabricated on epitaxial layers grown by plasma assisted molecular beam epitaxy (PAMBE) on on-axis semi-insulating bulk GaN substrates. On-state current density of ∼1 A mm−1 was observed on transistors with LG = 0.75 μm, LGS = 0.5 μm and LGD = 3.75 μm. In a deep class AB mode of operation, devices fabricated on epitaxial structures with these substrates demonstrated 60% higher electron channel mobility compared to devices fabricated with a similar epitaxial structure grown on sapphire substrates using metal-organic chemical vapor deposition. As the first demonstration of N-polar GaN-on-GaN MISHEMT for power amplifier applications, the devices discussed in this letter bridge a path towards achieving higher power gain and efficiency for millimeter-wave N-polar GaN HEMTs.

A Dual-Band GaN MMIC Power Amplifier With Hybrid Operating Modes for 5G Application

This letter implements a 3.5-/5.8-GHz dual-band power amplifier (PA) with hybrid operating modes for 5G mobile communication and vehicle network using a 0.25- $\mu \text{m}$ gallium nitride (GaN)-HEMT process. For the 3.5-GHz band, the PA operates in the Doherty mode, and the performance is optimized for a high back-off efficiency and a large bandwidth. For the 5.8-GHz band, the PA operates in class-AB mode, and optimal saturation efficiency is used as the design goal. According to the measurement results, a saturated power of 41.8–42.6 dBm, a saturated drain efficiency (DE) of 56%–64%, and a 6-dB back-off DE of 42%–51% are achieved from 3.3 to 3.8 GHz, while the saturated power and DE at 5.8 GHz are 41 dBm and 55%, respectively. To our best knowledge, this is the first dual-band GaN monolithic microwave integrated circuit PA designed for hybrid operating modes.

Analytical Design Space of Power Amplifiers Including the Class-A/B/J Continuum for Dynamic Load Modulation

In this paper, an analytical design space of power amplifiers (PAs) including the Class-A/B/J continuum for dynamic load modulation (DLM) at the current generator plane (CGP) is proposed based on the theory of load modulated (LM) continuous Class-B/J PAs. By introducing a biasing operation factor ρ, the theory of DLM PAs provides an analytical design space for all the operation modes from Class-B/J mode to Class-A mode. The analytical design space of DLM PAs shows that high efficiency is maintained at a large dynamic range of output power back-off (OPBO) with a purely resistive load modulation at the CGP when Class-B/J mode is performed. For deep Class-AB mode, the analytical design space of the DLM PAs shows that a combination of resistive and reactive load modulation at the CGP is used to maintain the high efficiency at the OPBO. The effectiveness of the proposed analytical design space is validated by load-pull measurements of a bare-chip gallium nitride (GaN) device.

A <inline-formula> <tex-math notation="LaTeX">$\Pi$ </tex-math> </inline-formula>-Shaped Gate Design for Reducing Hot-Electron Generation in GaN HEMTs

The use of a π -shaped gate structure is proposed for GaN HEMTs, which effectively reduces the hot-electron generation under all regimes of operation, while preserving device performance well into the lower millimeter-wave frequency range. Simulations under dc and large-signal RF conditions of the proposed π-gate device, along with the corresponding electron energy distribution functions, were obtained with a full-band cellular Monte Carlo device simulator self-consistently coupled to a harmonic-balance circuit solver and compared with the simulations of a typical Tgate HEMT whose dc curves were calibrated to experimental data. Our results show that the peak hot-carrier generation obtained with an asymmetric-π-gate is up to 41%, 44%, and 75% lower at dc and in Class AB mode at 10 GHz and 40 GHz, respectively, as compared with that observed with the comparable Tgate devices. This new gate structure suggests that significantly higher reliability against hot-electron-induced device damage can be achieved with modest impacts on performance.

Ultra-low-power bulk-driven fully differential subthreshold OTAs with partial positive feedback for Gm-C filters

This paper presents an ultra-low-power, bulk-driven, source-degenerated fully differential transconductor (FD-OTA), operating in subthreshold region. The source-degeneration (SD) and bulk-drive ensure linearity and rail-to-rail input swing. The flipped voltage follower and SD resistor perform V–I conversion in input core with power efficient class AB mode of operation. The reduction in open loop gain and gain bandwidth (GBW) of bulk-drive is compensated by applying partial positive feedback at diode connected MOSFET pair. The current gain from input core to output load side is set (1:1) in OTA1 and (1:4) in OTA2. The OTA2 offers increased transconductance and GBW whereas self-cascode load increases the output impedance and overall gain of the FD-OTAs. Both the input core and common source self-cascode load operate in class AB mode so these FD-OTAs provide enhanced slew rates. These OTAs have been employed to implement Biquadratic low-frequency Gm-C filter suitable for bio-signal applications. The proposed OTA2 has used dual supply voltage of ± 0.3 V and dissipates around 70 nW power and provides 62 dB FD-open loop gain with GBW of 7.73 kHz while driving the FD-load of 2 × 15 pF. The Cadence VIRTUOSO environment using UMC 0.18 µm CMOS process technology has been used to simulate the proposed circuit. The Simulation results verified fully differential total harmonic distortion of − 72 dB, for 1.2 Vp–p signal at 200 Hz frequency in unity gain configuration with resistive degeneration of 1 MΩ for OTA1.

Two stage class AB-AB amplifier using FGMOS for low voltage operation and SSF for frequency compensation

The paper presented here offers a two stage amplifier where both stages are in class AB mode. The input stage makes use of a floating gate metal oxide semiconductor (FGMOS) transistor which enables this circuit to operate at lower voltage and also increases overall linearity. The frequency compensation is done using voltage buffer scheme. A super source follower (SSF) acts as voltage buffer and exploited here with a series capacitor. The function of SSF is to enhance phase margin (PM) and gain bandwidth product (GBW) of the amplifier. The small signal equivalent and mathematical analysis of circuit is also given. The performance of the proposed circuit has been verified by using Mentor Graphics Eldo simulation tool with TSMC CMOS 0.18μm process parameters. The ac simulation results of amplifier show that GBW is 9MHz and power consumption is 0.5mW.

A 60-GHz Power Amplifier With AM–PM Distortion Cancellation in 40-nm CMOS

This paper presents a complementary push-pull 60-GHz power amplifier (PA) in 40-nm CMOS. The proposed technique is used to mitigate the amplitude to phase modulation (AM-PM) distortion caused by the nonlinear input capacitance of an MOS transistor. By operating in deep class-AB mode, the back-off efficiency of the PA is improved without compromising gain. The proposed interstage transformer with two secondary windings enables right impedance transformation concurrently for the two separate transistors with independent biasing ability. The two-stage PA achieves a gain of 22.4 dB, power added efficiency (PAE) PAEMAX of 23%, and saturated output power ( $P_{\text {SAT}}$ ) of 16.4 dBm with 8% PAE at 6 dB back-off. With 35 dB of adjacent channel power ratio. Also a comparison with a common-source PA is presented, which shows its limitation in dealing with AM-PM distortion.

Design of a Linear High-Drive Class-AB Differential Amplifier in 90 nm CMOS Technology

In this paper, a CMOS differential input, differential output amplifier is presented. This amplifier operates in class AB mode and exhibits high current drive capability. The circuit is designed and implemented in a UMC 1P-9M standard 90-nm CMOS technology. It provides fast settling response of 235 ns while powered with 2 V. The proposed amplifier operates on a wide input differential range with high linearity exhibiting a P-1 dB of 10 dB. The circuit exhibits a differential current-drive capability of 2.9 mA. The presented amplifier has high gain-bandwidth product of 94 MHz. This differential amplifier provides a CMRR of 89 dB.

Optimal Design of Low Power CMOS Power Amplifier Using Particle Swarm Optimization Technique

A low voltage 2.4 GHz CMOS power amplifier for wireless personal area network (WPAN) applications is presented in TSMC 0.13 $$\upmu $$μm CMOS process. It consists of driver and power amplifier stages which are connected in current reuse structure. The driver amplifier has push pull inverter configuration. The power amplifier is the common source amplifier. These two stages are biased in class AB mode. For optimizing out-of-band emissions, the proposed power amplifier is linearized by RF predistortion technique. For efficient power amplifier, the design parameters are needed to be optimized using particle swarm optimization technique. The optimized power amplifier achieves 0 dBm output power, 34.06 % PAE, 18 dB power gain at 2.4 GHz frequency. It consumes 2.95 mW power at a supply voltage of 1.2 V.

Designing Linear PAs at Millimeter-Wave Frequencies Using Volterra Series Analysis

Power amplifiers (PAs) at millimeter-wave (mm-wave) frequencies are required for delivering high output linear power while being efficient; however, their performance is severely affected by the scaled semiconductor technology and the operating frequency. To improve the linearity of mm-wave PAs, it is recommended that an external linearization technique such as predistortion be used. The PA presented in this paper uses adaptive predistortion (APD). The APD linearization technique was developed using the Volterra series analysis on the silicon–germanium (SiGe) heterojunction bipolar transistor. The Volterra series analysis was used to identify and characterize the third-order intermodulation distortion components. The PA uses a single-ended common-emitter topology. It consists of three stages biased in the Class AB mode. The PA and APD were designed using the 130-nm SiGe bipolar and complementary metal–oxide–semiconductor process. The PA and APD achieve an optimum third-order intermodulation reduction of 10 dB and an improved linear output power of 2.5 dBm.

Model-Based Nonlinear Embedding for Power-Amplifier Design

A fully model-based nonlinear embedding device model including low- and high-frequency dispersion effects is implemented for the Angelov device model and successfully demonstrated for load modulation power-amplifier (PA) applications. Using this nonlinear embedding device model, any desired PA mode of operation at the current source plane can be projected to the external reference planes to synthesize the required multi-harmonic source and load terminations. A 2-D identification of the intrinsic PA operation modes is performed first at the current source reference planes. For intrinsic modes defined without lossy parasitics, most of the required source impedance terminations will exhibit a substantial negative resistance after projection to the external reference planes. These terminations can then be implemented by active harmonic injection at the input. It is verified experimentally for a 15-W GaN HEMT class-AB mode that, using the second harmonic injection synthesized by the embedding device model at the input, yields an improved drain efficiency of up to 5% in agreement with the simulation. A figure-of-merit is also introduced to evaluate the efficacy of the nonlinear embedding PA design methodology in achieving the targeted intrinsic mode operation given the model accuracy.

Realization of a 30-W highly efficient and linear reconfigurable dual-band power amplifier using the continuous mode approach

This paper presents the design methodology and the realization of a highly linear and power-efficient reconfigurable dual-band amplifier based on the continuous/Class-ABJ approach. The Class-ABJ theory allows presenting different reactive solutions on both fundamental and second harmonic terminations compared with the standard Class-AB mode. Despite the various terminations, a constant optimum output performance in terms of power, gain, and efficiency can still be achieved. The output impedances are then translated into frequency thus allowing the realization of broadbandpower amplifiers(PAs) at high-power level of 30 W. In this work, the Class-ABJ broadband approach will be used for the realization of a reconfigurable dual-band power amplifier operating in the two frequency bands 2.1–2.2 and 2.5–2.6 GHz. Continuous wave (CW) measurements on the realized PA show power and efficiency greater than 17 W and 55% in the two frequency bands with peak values up to 30 W and 63.7%. Indeed, it is shown that such novel modes can be predistorted and therefore the linearity requirement can also be met.

An Optimized 2.4GHz RF Power Amplifier Performance for WLAN System

Recently, the design of RF power amplifiers (PAs) for modern wireless systems are faced with a difficult tradeoff for example, cellphone; battery lifetime is largely determined by the power efficiency of the PA and high spectral efficiency which have ability to transmit data at the highest possible rate for a given channel bandwidth. This paper presents the design a multi stage class AB power Amplifier with high power added efficiency (PAE) and acceptable linearity for the WLAN applications. The open-circuited third harmonic control circuit enhances the efficiency of the PA without deteriorating the linearity of class-AB mode of the PA. The voltage and current waveforms are simulated to evaluate the appropriate operation for the modes. The effectiveness of the proposed controller has been verified by comparing proposed method with another methods using simulation study under a variety of conditions. The proposed circuit operation for a WLAN signals delivers a power-added efficiency (PAE) of 37.6% is measured at 31.6-dBm output power while dissipating 34.61 mA from a 1.8V supply. Finally, the proposed PA is show a good and acceptable result for the WLAN system.