Circuit Reliability Research Articles

The Application of Secondary Effects in Optimizing Analog Circuits

Abstract. This study delves into the application of secondary effects, specifically body effect, channel length modulation effect, and subthreshold conduction effect, in the optimization of analog integrated circuits. The research highlights the critical role these effects play in modern circuit design, especially as device dimensions continue to shrink. Through a systematic analysis, the study presents key strategies for mitigating these effects to enhance circuit performance, reliability, and power efficiency. Notably, the implementation of a transient BD scheme in partially analog-assisted D-LDOs (Digital Low Dropout Regulators) has shown a performance improvement of over 10% compared to schemes without this enhancement, while also significantly reducing total coupling. Techniques such as DIBL effect compensation have proven effective in reducing load sensitivity and power consumption. This study provide valuable insights and practical approaches for the design and optimization of high-performance, energy-efficient electronic systems, making a significant contribution to the field of integrated circuit design.

Application of Fractional Modified Taylor Wavelets in the Dynamical Analysis of Fractional Electrical Circuits under Generalized Caputo Fractional Derivative

Abstract This study examines the application of fractional calculus in the analysis and modeling of electrical circuits of fractional order, highlighting its potential to explain the behaviour of complex electrical circuits accurately. In the domain of electrical circuits, fractional differential equations are employed in the analysis and simulation of systems that consist of resistors, capacitors and inductors. In the present paper, a novel approach utilizing fractional order modified Taylor wavelets is implemented to solve the fractional model of RL, LC, RC and RLC electrical circuits under generalized Caputo fractional derivative which offers precise and flexible modeling of non-locality and hereditary characteristics in complex systems. Furthermore, an additional parameter $\sigma$ (time scale parameter) is incorporated in fractional circuit dynamics to maintain the physical dimensionality. The considered wavelets with the collocation technique offer an efficient solution by converting the fractional model of electrical circuits into a set of algebraic equations which are further solved by using the Newton iteration method. Moreover, this study discusses the significance of Ulam-Hyers stability, emphasizing its role in ensuring stable and reliable circuit performance. The impact of fractional order on the dynamics of the electric circuit model is presented by tables and graphs. The approximate solutions obtained by the proposed method are well comparable with exact solutions and some other existing wavelet-based techniques. The residual errors are also evaluated under various model parameters for fractional orders. Furthermore, the graphs illustrate that the error progressively decreases as the number of wavelets basis increases.

Control of spin–orbit torque-driven domain nucleation through geometry in chirally coupled magnetic tracks

The interfacial Dzyaloshinskii–Moriya interaction (DMI) can be exploited in magnetic thin films to realize lateral chirally coupled systems, providing a way to couple different sections of a magnetic racetrack and realize interconnected networks of magnetic logic gates. Here, we systematically investigate the interplay between spin–orbit torques, chiral coupling, and the device design in domain wall racetracks. We show that the current-induced domain nucleation process can be tuned between single-domain nucleation and repeated nucleation of alternate domains by changing the orientation of an in-plane patterned magnetic region within an out-of-plane magnetic racetrack. Furthermore, by combining experiments and micromagnetic simulations, we show that the combination of damping-like and field-like spin–orbit torques with DMI results in selective domain wall injection in one of two arms of a Y-shaped device depending on the current density. Such an element constitutes the basis of domain wall based demultiplexer, which is essential for distributing a single input to any one of the multiple outputs in logic circuits. Our results provide input for the design of reliable and multifunctional domain wall circuits based on chirally coupled interfaces.

Rational Design of High-Efficiency Synthetic Small Regulatory RNAs and Their Application in Robust Genetic Circuit Performance Through Tight Control of Leaky Gene Expression.

Synthetic sRNAs show promise as tools for targeted and programmable gene expression manipulation. However, the design of high-efficiency synthetic sRNAs is a challenging task that necessitates careful consideration of multiple factors. Therefore, this study aims to investigate rational design strategies that significantly and robustly enhance the efficiency of synthetic sRNAs. This is achieved by optimizing the following parameters: the sRNA scaffold, mRNA binding affinity, Hfq protein expression level, and mRNA secondary structure. By utilizing optimized synthetic sRNAs within a positive feedback circuit, we effectively addressed the issue of gene expression leakage─an enduring challenge in synthetic biology that undermines the reliability of genetic circuits in bacteria. Our designed synthetic sRNAs successfully prevented gene expression leakage, thus averting unintended circuit activation caused by initial expression noise, even in the absence of signal molecules. This result shows that high-efficiency synthetic sRNAs not only enable precise gene knockdown for metabolic engineering but also ensure the robust performance of synthetic circuits. The strategies developed here hold significant promise for broad applications across diverse biotechnological fields, establishing synthetic sRNAs as pivotal tools in advancing synthetic biology and gene regulation.

Multi-View Graph Learning for Path-Level Aging-Aware Timing Prediction

As CMOS technology continues to scale down, the aging effect—known as negative bias temperature instability (NBTI)—has become increasingly prominent, gradually emerging as a key factor affecting device reliability. Accurate aging-aware static timing analysis (STA) at the early design phase is critical for establishing appropriate timing margins to ensure circuit reliability throughout the chip lifecycle. However, traditional aging-aware timing analysis methods, typically based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations or aging-aware timing libraries, struggle to balance prediction accuracy with computational cost. In this paper, we propose a multi-view graph learning framework for path-level aging-aware timing prediction, which combines the strengths of the spatial–temporal Transformer network (STTN) and graph attention network (GAT) models to extract the aging timing features of paths from both timing-sensitive and workload-sensitive perspectives. Experimental results demonstrate that our proposed framework achieves an average MAPE score of 3.96% and reduces the average MAPE by 5.8 times compared to FFNN and 2.2 times compared to PNA, while maintaining acceptable increases in processing time.

Enhancing voltage regulation in high-speed digital circuits: A simulation-based analysis of the modified Ohm's law

Voltage droop is a significant challenge in high-speed digital circuits, impacting the reliability and performance of electronic systems. This paper introduces a novel approach based on a Modified Ohm's Law to address this issue. By incorporating nonlinear resistance effects, the Modified Ohm's Law provides a more accurate representation of circuit behavior, particularly under dynamic conditions. Through a rigorous simulation framework, the behavior of power supply models under varying load conditions is analyzed. The paper systematically examines circuit responses, load variations, and power supply dynamics, integrating both Standard and Modified Ohm's Law to compare their effectiveness in voltage regulation. The simulation results indicate that the Modified Ohm's Law provides a more accurate prediction of voltage behavior, particularly under rapid load changes, leading to significant improvements in voltage stability. The applied parameter sweep analyses reveal that adjusting the time constant of the power supply within the Modified Ohm's Law framework yields superior voltage regulation compared to traditional methods. Additionally, the analysis of frequency and amplitude variations demonstrates the robustness of the Modified Ohm's Law in maintaining voltage stability across different operational scenarios. This approach effectively addresses the nonlinearities in resistance, reducing voltage droop and enhancing the reliability of high-speed digital circuits. The findings demonstrate the potential of the Modified Ohm's Law in practical applications, suggesting further research and real-world experimentation to fully explore its benefits and implementation strategies. This work contributes to the advancement of voltage regulation techniques, offering a robust solution to the persistent problem of voltage droop in modern electronic systems.

A novel cryogenic acoustic microscope to evaluate electronic components

Abstract Electronics to operate at cryogenic temperatures is key to many areas of science, including space exploration and in particle physics. Ensuring circuit functional reliability is mission critical. One system that will use tens of thousands of custom designed application specific integrated circuits (ASIC) is the Deep Underground Neutrino Experiment (DUNE), which will have sensor circuits operating in liquid argon (87 K) for decades. Both functional and nondestructive testing are being used to ensure circuit quality and reliability. Part of this work involves design, testing and data analysis using a cryogenic acoustic microscope operating at frequencies up to 50 MHz. Image analysis and correlations are used to compare differences seen before and after cryogenic cycling. Data are reported that were collected at room temperature (300 K) and when cooled using liquid nitrogen (77 K).

Impact of Layout Parameter Mismatches on Short Circuit Reliability of Parallel-Connected Planar, Trench, and Double-Trench SiC MOSFETs

Impact of Layout Parameter Mismatches on Short Circuit Reliability of Parallel-Connected Planar, Trench, and Double-Trench SiC MOSFETs

Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization

Transistor aging leads to the deterioration of analog circuit performance over time. The worst aging degradation is used to evaluate the circuit reliability. It is extremely expensive to obtain it since several circuit stimuli need to be simulated. The worst degradation collection cost reduction brings an inaccurate training dataset when a machine learning (ML) model is used to fast perform the estimation. Motivated by the fact that there are many similar subcircuits in large-scale analog circuits, in this article we propose Wages to train an ML model on an inaccurate dataset for the worst aging degradation estimation via a domain generalization technique. A sampling-based method on the feature space of the transistor and its neighborhood subcircuit is developed to replace inaccurate labels. A consistent estimation for the worst degradation is enforced to update model parameters. Label updating and model updating are performed alternately to train an ML model on the inaccurate dataset. Experimental results on the very advanced 5 nm technology node show that our Wages can significantly reduce the label collection cost with a negligible estimation error for the worst aging degradations compared to the traditional methods.

Aggravated NBTI reliability due to hard-to-detect open defects

FinFET technology has become an attractive candidate for high-performance and power-efficient applications. In the other hand, the behavior of FinFET devices is influenced by self-heating effect (SHE) due to its 3D structure, low thermal coupling and quantum confinement effect, among others. SHE degrades the device’s performance and could worsen reliability mechanisms like NBTI. In addition, some hard-to-detect open defects in FinFET based-circuits using logic gates designed with multi-fin and multi-finger techniques may escape the test and present abnormal static currents, which may increase the impact of self-heating effect and make the NBTI degradation more severe. Hence, it is crucial to accurately determine the temperature profiles of those chips passing the test and presenting abnormal static currents. This paper investigates the reliability of chips passing the test with abnormal static currents using Sentaurus Technology Computer-Aided Design (TCAD). FinFET transistors are calibrated with Intel 14-nm FinFET technology. Our TCAD simulation framework determines accurately the temperature and NBTI degradation. Using the TCAD information, the device degradation over time can be predicted. Moreover, the delay penalization of a critical logic path of an ISCAS benchmark circuit is investigated. The delay penalization of logic paths, attributed to the defect and NBTI, is analyzed with varying logic depths, emphasizing the importance of addressing critical paths with different logic depths. Our study leads to new considerations for improving the prediction of circuit reliability and taking countermeasures.

Reduce energy consumption - causes of CMOS inverter switching delay and its influencing factors

This paper offers a comprehensive examination of the Complementary Metal-Oxide-Semiconductor (CMOS) inverter, a quintessential component in contemporary digital integrated circuits, renowned for its minimal power consumption, robust noise resistance, and adaptability. The focus of this investigation is the switching delay of the CMOS inverter, a pivotal attribute that exerts substantial influence on the overall functionality of the circuitry. This discourse undertakes a detailed exploration of the factors contributing to the CMOS inverter switching delay, dissecting the influence of both intrinsic and extrinsic elements. Initially, the analysis delineates the origins of the switching delay in CMOS inverters, categorizing them into internal and external determinants. Subsequently, the study meticulously examines methodologies to modulate these factors, thereby achieving effective control over the delay. By implementing strategic optimizations, this research aims to diminish latency and enhance operational efficiency. Through a theoretical lens, this paper elucidates the complex interplay between these inherent and external factors, culminating in the optimization of the CMOS inverter switching delay. The insights garnered from this analysis are poised to offer a substantive theoretical foundation for the design of more efficient and reliable digital circuits in the current technological milieu.

Centralized Finite State Machine Control to Increase the Production Rate in a Crusher Circuit

Crushing is a critical operation in mineral processing, and its efficient performance is vital for minimizing energy consumption, maximizing productivity, and maintaining product quality. However, due to variations in feed material characteristics and safety constraints, achieving the intended circuit performance can be challenging. In this study, a centralized control strategy based on a finite state machine (FSM) is developed to improve the operations of an iron ore crushing circuit. The aim is to increase productivity by manipulating the closed-side-setting (CSS) of cone crushers and the speed of an apron feeder while considering intermediate storage silo levels and cone crusher power limits, as well as product quality. A dynamic simulation was conducted to compare the proposed control strategy with the usual practice of setting CSS to a constant value. Four scenarios were analyzed based on variations in bond work index (BWI) and particle size distribution. The simulation results demonstrate that the proposed control strategy increased average productivity by 6.88% and 48.77% when compared to the operation with a constant CSS of 38 mm and 41 mm, respectively. The proposed strategy resulted in smoother oscillation without interlocking, and it maintained constant flow rates. This ultimately improved circuit reliability and predictability, leading to reduced maintenance costs.

Synthesis of Optimal Correction Functions in the Class of Disjunctive Normal Forms

The paper proposes to consider individual heuristics as unreliably operating parts of the information processing system. In a separate case, several different heuristics are adopted to solve the same problem, and the results obtained are adjusted in a certain way. In this case, problems arise that are close in methodology to the problems of synthesizing reliable circuits from unreliable elements or making a collective expert decision. The work solves the problem of constructing an optimal correction function based on control material; classes of functions of k-valued logic under monotonicity restrictions are studied. A theorem on the completeness of the class of monotonic functions of k-valued logic for arbitrary k is proved, and a basis in the given class is proved and constructed. The problem of constructing an optimal corrector in the class of disjunctive normal forms of k-valued functions is solved.

An aging simulation method based on the change of input vector inside the critical path

Abstract With the large-scale expansion and process shrinking of modern integrated circuits, aging has become one of the main factors threatening circuit reliability. To evaluate the impact of aging on circuit life, it is important to investigate aging simulation methods. Aiming at the problem of slow speed and insufficient accuracy of large-scale digital circuit aging simulation methods, a circuit aging simulation method based on the change of input vector inside the critical path (CICP) is proposed in this paper. First, the critical path (CP) with the tightest timing is extracted by static timing analysis (STA), and SPICE simulation is carried out to accurately predict the aging of the CP of the circuit. Second, the aging simulation is carried out considering the change of the internal input vector of the CP. The simulation results show that after changing the internal input signal, the aging path delay increases up to 3.5%.

Design and High Performance Evaluation of a Low Power Bit-Line SRAM PMOS Biased Sense Amplifier

Sense amplifiers developed into very big circuits due to their significant role in Memory design. The sense amplifier plays a significant role in terms of its recital, Functionality and reliability of the memory circuits. Fast access time and low power Dissipation are achieved with newly developed circuits of sense amplifiers for low voltage supply. Static RAM is the sense amplifiers at the ends of the two Complementary bit lines that amplify the small voltages to a normal logic level. Static RAM (SRAM) is a type of random access memory that retains data bits in its Memory as long as power is supplied. The proposed circuit is a P-type metal oxide Semiconductor (PMOS) biased sense amplifier, which provides very high, output Impedance, has reduced sense delay, and has reduced power dissipation. It performs the same operations as conventional circuits. The proposed circuit has a smaller number of transistors, so sensing delay and power consumption are also reduced. These circuits are simulated and examined using the Tanner EDA tool employing 180 nm technology library parameters. Key Words: Low power consumption, Power Consumption, Sense amplifiers, sense delay, static RAM.

Evaluating the Electroencephalographic Signal Quality of an In-Ear Wearable Device.

Wearable in-ear electroencephalographic (EEG) devices hold significant promise for advancing brain monitoring technologies into everyday applications. However, despite the current availability of several in-ear EEG devices in the market, there remains a critical need for robust validation against established clinical-grade systems. In this study, we carried out a detailed examination of the signal performance of a mobile in-ear EEG device from Naox Technologies. Our investigation had two main goals: firstly, evaluating the hardware circuit's reliability through simulated EEG signal experiments and, secondly, conducting a thorough comparison between the in-ear EEG device and gold-standard EEG monitoring equipment. This comparison assesses correlation coefficients with recognized physiological patterns during wakefulness and sleep, including alpha rhythms, eye artifacts, slow waves, spindles, and sleep stages. Our findings support the feasibility of using this in-ear EEG device for brain activity monitoring, particularly in scenarios requiring enhanced comfort and user-friendliness in various clinical and research settings.

Ultrafast Terahertz Superconductor Van der Waals Metamaterial Photonic Switch

The high‐temperature layered superconductor (HTS) BSCCO is one of the key quantum material platforms in THz science and technology. Compact, stable, and reliable BSCCO THz photonic integrated circuit components can be developed to effectively and efficiently control and manipulate THz wave radiation, especially for future communication systems and network applications. Herein, the design, simulation, and modeling of ultrafast THz metamaterial photonic integrated circuits are reported on a few nanometer‐thick HTS BSCCO van der Waals (vdWs), capable of the active modulation of phase with constant transmission coefficient over a narrow‐frequency range. Meanwhile, the metamaterial circuit works as an amplitude modulator without significantly changing the phase in a different frequency band. Under the application of ultrashort optical pulses, the transient modulation dynamics of the THz metamaterial offer a fast‐switching timescale of 50 ps. The dynamics of picosecond light–matter interaction, Cooper pairs breaking, photoinduced quasiparticles generation and recombination, phonon bottleneck effect, and emission and relaxation of bosons in BSCCO vdW metamaterial arrays are discussed for the potential application of multifunctional superconducting photonic integrated circuits in communication and quantum technologies.

Design and Analysis of High Performance FinFET-Based Linear Feedback Shift Register for Cryptography Applications

Nowadays, all the elements of our surrounding is occupied by electronics. Electronics occupies major role on our day today life. Electronics device integration on a single chip enhances performance in terms of speed, low-power circuits, and area. Integration of VLSI provides better scalability and reliability. This research paper focused on the implementation of Linear feedback shift registers (LFSR) using FinFET techniques at the layout level for various applications, including cryptography. FinFETs are highlighted as a replacement for CMOS technology, offering advantages such as improved performance in terms of speed, low-power circuits, and area. Linear feedback shift registers are commonly used in digital systems and cryptography for generating pseudo-random sequences. The use of FinFET technology in the layout level suggests an interest in exploring advanced semiconductor technologies to enhance the performance of these circuits. The paper appears to cover different design methods of LFSRs, which could include aspects like circuit optimization, power efficiency, and reliability. The integration of electronics on a single chip, particularly with FinFET technology, is noted for its potential to provide better scalability and reliability. The first architecture is created using bulk CMOS techniques; whereas the second is constructed using two fin FinFET LFSRs. Using the Microwind designing tool, the third technique is developed with a 3-fin FinFET LFSR. It provides a solution for a novel FinFET architecture that implements LFSR. When comparing CMOS and FinFET circuit designs for LFSR, the latter achieves superior performance in terms of area and power efficiency. An analysis is conducted on the design techniques and performance of CMOS LFSR, 2 fin FinFET based LFSR, and 3 fin FinFET. According to the experimental findings, the CMOS-based LFSR uses 1.243 mW of power; the FinFET-based LFSR uses 90.47 μW, and the two fin FinFET LFRS uses 0.254 mW.

P‐73: Gate Driver Circuit to generating Multi‐Frequency Pulses using LTPO Technology

This paper proposes a gate driver circuit for the implementation of multi‐region and multi‐refresh rates. A distinctive feature of this proposed circuit is the integration of a separate control block into the existing gate driver circuit. Another is the utilization of CMOS (a combination of n‐type IGZO and p‐type LTPS) to enhance circuit reliability and reduce power consumption. This gate driver circuit can be applied to an LTPO based pixel circuit which can be using with a variable refresh rate and implemented multi‐zone and multi‐refresh rates. Through circuit simulations, the paper verifies the successful operation of multi‐refresh rates based on control signals and establishes a reduction in clock power consumption. Consequently, the proposed gate driver circuit stands as a solution for achieving high resolution and low power consumption in displays.

QCA-based fault-tolerant XOR Gate for reliable computing with high thermal stability

The XOR gate is an essential element in the design of digital circuits due to its versatility and usefulness. The design of XOR gate in this paper is based on Quantum-dot Cellular Automata (QCA) 2D planner technology with no line-to-line intersections. The output amplitude is improved by redundant cell-based design, which also helped reliability and fault tolerance outperform. The proposed XOR gate achieves fault tolerance to single-cell addition and missing-cell defects from 68.48% to 95.33%. In addition, the proposed XOR gate is also fault-tolerant against multiple-cell missing defects, as verified from the simulations. Furthermore, high thermal stability makes the circuit reliable for QCA-based digital design applications. The digital design applications such as 4-bit B2G code converter and a 4-bit parity checker are designed from this XOR gate, utilizing 438 and 414 cells, respectively. This demonstrates its effectiveness in designing fault resilient and reliable circuit designs for various applications.