Circuitry Configuration Research Articles

Performance Prediction of Plate-Finned Tube Heat Exchangers for Refrigeration: A Review on Modeling and Optimization Methods

Finned tube heat exchangers are used in many technological applications in both civil and industrial sectors. Their large-scale use requires a design aimed at reaching high thermal efficiency as well as avoiding unnecessary waste of resources in terms of time and costs. Therefore, in the last decades, research in this area has developed considerably and numerous studies have been conducted on modeling in order to predict heat exchangers (HXs) performance and to optimize design parameters. In this paper, the main studies carried out on plate-finned tube HXs have been collected, analyzed, and summarized, classifying existing models by their scale approach (small, large, or multi-scale). In addition, the main methods of design optimization with a focus on circuitry configurations have been illustrated. Finally, future developments and research areas that need more in-depth analysis have been identified and discussed.

Tailoring a Minimal Self-Replicate DNA Circuit for Highly Efficient Intracellular Imaging of microRNA.

Trace analyte detection in complex intracellular environment requires the development of simple yet robust self-sufficient molecular circuits with high signal-gain and anti-interference features. Herein, a minimal non-enzymatic self-replicate DNA circuitry (SDC) system is proposed with high-signal-gain for highly efficient biosensing in living cells. It is facilely engineered through the self-stacking of only one elementary cascade hybridization reaction (CHR), thus is encoding with more economic yet effective amplification pathways and reactants. Trigger (T) stimulates the activation of CHR for producing numerous T replica that reversely motivate new CHR reaction cycles, thus achieving the successive self-replication of CHR system with an exponentially magnified readout signal. The intrinsic self-replicate circuity design and the self-accelerated reaction format of SDC system is experimentally demonstrated and theoretically simulated. With simple circuitry configuration and low reactant complexity, the SDC amplifier enables the high-contrast and accurate visualization of microRNA (miRNA), ascribing to its robust molecular recognition and self-sufficient signal amplification, thus offering a promising strategy for monitoring these clinically significant analytes.

Design of a Numerical Simulator for Finned-Tube Heat Exchangers with Arbitrary Circuitry

A numerical simulator that can handle a finned-tube heat exchanger with a complex refrigerant circuitry is presented. The model is based on a tube-by-tube approach in which each tube is considered as the control volume in the analysis of the mass, energy, and momentum conservation. A mathematical representation of the refrigerant circuitry is also developed using the concepts in graph theory. The tube–tube adjacency matrix provides a unique representation of the tube connectivity and can also be utilized for constraints handling. With the implementation of the constraints, nonphysical and infeasible circuitries are removed from the solution space, which is advantageous for an evolutionary search for an optimum solution. The numerical simulator is verified against two sets of experimental data, and the calculated heat duty and pressure drop are within ±6% and ±20%, respectively. Sample simulations of the performance of different refrigerants in three circuitry configurations, and circuitry optimization are conducted to investigate the reliability and effectiveness of the tube-tube adjacency matrix and simulation model in the search for an optimal solution.

Multi-objective optimization of low-GWP mixture composition and heat exchanger circuitry configuration for improved system performance and reduced refrigerant flammability

The recently introduced hydrofluoroolefin (HFO) refrigerants, including R1234yf and R1234ze(E), have significantly lower global warming potentials (GWPs) than traditional hydrofluorocarbon (HFC) refrigerants like R410A. However, prior tests show that direct drop-in of pure R1234yf or R1234ze(E) into equipment designed for R410A results in a decrease in heat exchanger capacity and the system coefficient of performance. The primary reason is the lower in-tube heat transfer performance of R1234yf and R1234ze(E) compared with that of R410A. To address this issue, previous studies have mixed the mildly flammable HFC R32 with HFOs to improve system performance, with HFC R125 also added to suppress flammability. Previous studies selected compositions based on simple cycle analyses and did not consider modifications of the heat exchanger circuitry configuration to adapt to the new refrigerants. This study presents a novel multi-objective optimization approach to design a refrigerant composition that maximizes energy efficiency within flammability and GWP limits. The approach in this work simultaneously optimizes mixture composition and heat exchanger circuitry configuration. A case study on a rooftop unit indicates that, compared with mixture-only optimization, simultaneous optimization of mixture and heat exchanger circuitry yields a 5.9% improvement in cycle efficiency and a 48.6% reduction in refrigerant flammability with a GWP of 268. Circuitry optimization using refrigerants with different temperature glides shows that the larger the temperature glide is, the larger EER improvement is obtained. The results show that zeotropic blends with a large temperature glide are more sensitive to the refrigerant circuitry than pure refrigerants and may suffer significant performance degradation with subpar heat exchanger circuitry design. The proposed optimization approach is generally applicable to mixtures with any number of components. Using this approach to design a HVAC system can yield higher system efficiency within flammability and GWP constraints.

A T-Type Modular Multilevel Converter

This article proposes a novel modular multilevel converter (MMC) named “T-type MMC” (T-MMC) for reliable, controllable, and efficient performance in energy conversion applications. Circuitry configurations and control structures are presented with respect to fundamental and additional functions. The T-MMC topology consists of two solid-state power stages (Stage-I and Stage-II), which are coordinated for ac and dc fault tolerance and increased ac-side voltage synthesis. Energy storage elements can be integrated into the submodules. As a result, the T-MMC based energy storage system can not only increase system inertia but also maintain continuous power transmission during faults. A thyristor forced-commutation technique facilitates actively controlled utilization of symmetrical thyristors in the conduction path; thus, T-MMC normal-mode operation losses can be equivalent to those of the conventional half-bridge MMC. Simulation and experimentation demonstrate the performance of the T-MMC.

A Method for the Development of Indicators of a Transient Period Based on Short-Pulse Shapers in Asynchronous Adders

The interest prevalent in the self-timed (ST) circuitry is related to the use of super-large integrated circuits. Circuits that enable increasing the degree of integration and power efficiency in combination with comparable performance are topical. A circuit of an asynchronous adder with a spacer two-rail code and an indicator of the transient process period based on CMOS transistors is proposed. A method of the circuitry configuration of the transient period indicator based on forming short pulses that correspond to the presence of a transient process is presented. A comparative analysis of the indicator’s performance demonstrates that the proposed method ensures a significant reduction in the number of components and power consumption. The efficiency of the proposed circuits is validated by simulation using the OrCAD PSpice circuit simulation software tool.

Optimization of circuitry arrangements for heat exchangers using derivative-free optimization

Optimization of the refrigerant circuitry can improve a heat exchanger's performance. Design engineers currently choose the refrigerant circuitry according to their experience and heat exchanger simulations. However, the design of an optimized refrigerant circuitry is difficult. The number of refrigerant circuitry candidates is enormous. Therefore, exhaustive search algorithms cannot be used and intelligent techniques must be developed to explore the solution space efficiently. In this paper, we formulate refrigerant circuitry design as a binary constrained optimization problem. We use CoilDesigner, a simulation and design tool of air to refrigerant heat exchangers, in order to simulate the performance of different refrigerant circuitry designs. We treat CoilDesigner as a black-box system since the exact relationship of the objective function with the decision variables is not explicit. Derivative-free optimization (DFO) algorithms are suitable for solving this black-box model since they do not require explicit functional representations of the objective function and the constraints. The aim of this paper is twofold. First, we compare four mixed-integer constrained DFO solvers and one box-bounded DFO solver and evaluate their ability to solve a difficult industrially relevant problem. Second, we demonstrate that the proposed formulation is suitable for optimizing the circuitry configuration of heat exchangers. We apply the DFO solvers to 17 heat exchanger design problems. Results show that TOMLAB/glcDirect and TOMLAB/glcSolve can find optimal or near-optimal refrigerant circuitry designs after a relatively small number of circuit simulations.

Single‐switch single‐inductor multi‐output pulse width modulation converters based on optimised switched‐capacitor

To combine advantages of switched-mode and switched-capacitor (SC) power converters, a series of non-isolated multi-output pulse width modulation converters are developed in this study. This type of converters employs only one inductor and one active switch, which contributes to a simple structure and easy control features. An optimised SC technique is developed for peak current limitation and equivalent resistance reduction for SC units. Circuitry configuration, operation principle, equivalent model and an optimised design are presented in detail. Experimental results of a three-output (±24 V, 48 V) converter prototype verifies the feasibility of voltage regulation and power efficiency.

Piezoresistive in-situ strain sensing of composite laminate structures

Various methods have been developed to monitor the health and strain state of carbon fiber reinforced polymers, each with a unique set of pros and cons. This research assesses the use of piezoresistive sensors for in situ strain measurement of carbon fiber and other composite structures in multidirectional laminates. The piezoresistive sensor material and the embedded circuitry are both evaluated. For the piezoresistive sensor, a conductive nickel nanocomposite sensor is compared with the piezoresistivity of the carbon fiber itself. For the circuit, the use of carbon fibers already present in the structure is compared with the use of nickel coated carbon fiber. Successful localized strain sensing is demonstrated for several sensor and circuitry configurations. Numerous engineering applications are possible in the ever-growing field of carbon-composites.

Programmable Implementation of Diamond-Shaped Type-2 Membership Function in CMOS Technology

In this paper, circuit implementation of diamond-shaped type-2 membership function in CMOS technology is presented. Designing of mixed analog/digital circuits provides a flexible configuration as well as the highly accurate performance, where analog circuits are employed to realize required functions, while the programmable units implemented using digital circuits. The current-mode approach is employed owing to the simple circuitry and intuitive configuration to design the circuits. The programmability of the circuit in terms of slopes, upper, and lower modal points enables the expert of the system to create other shapes of type-2 membership functions including rectangular, rhombus, triangular, and trapezoidal. For a particular set of programming parameters of diamond-shaped type-2 membership function, post layout simulation results of the proposed circuit using HSPICE and level 49 parameters (BSIM3v3) in 0.18 $$\mu $$ μ m technology, demonstrate an average power consumption of 0.688 mW, maximum propagation delay of 8.7 ns and a relative error as low as $$\pm $$ ± 1 %. Furthermore, Monte Carlo analysis is carried out to ensure the robustness of the circuit performance against the process variation.

Evaluation of a timing integrated circuit architecture for continuous crystal and SiPM based PET systems

Improving timing resolution in positron emission tomography (PET), thus having fine time information of the detected pulses, is important to increase the reconstructed images signal to noise ratio (SNR) [1]. In the present work, an integrated circuit topology for time extraction of the incoming pulses is evaluated. An accurate simulation including the detector physics and the electronics with different configurations has been developed. The selected architecture is intended for a PET system based on a continuous scintillation crystal attached to a SiPM array. The integrated circuit extracts the time stamp from the first few photons generated when the gamma-ray interacts with the scintillator, thus obtaining the best time resolution. To get the time stamp from the detected pulses, a time to digital converter (TDC) array based architecture has been proposed as in [2] or [3]. The TDC input stage uses a current comparator to transform the analog signal into a digital signal. Individually configurable trigger levels allow us to avoid false triggers due to signal noise. Using a TDC per SiPM configuration results in a very area consuming integrated circuit. One solution to this problem is to join several SiPM outputs to one TDC. This reduces the number of TDCs but, on the other hand, the first photons will be more difficult to be detected. For this reason, it is important to simulate how the time resolution is degraded when the number of TDCs is reduced. Following this criteria, the best configuration will be selected considering the trade-off between achievable time resolution and the cost per chip. A simulation is presented that uses Geant4 for simulation of the physics process and, for the electronic blocks, spice and Matlab. The Geant4 stage simulates the gamma-ray interaction with the scintillator, the photon shower generation and the first stages of the SiPM. The electronics simulation includes an electrical model of the SiPM array and all the integrated circuitry that generates the time stamps. Time resolution results are analyzed using Matlab. The goal is to analyze the best resolution achievable with the SiPM and its degradation due to different circuitry configurations.

Modelling, Evaluation and Optimization of Vehicle-to-Grid Operation

This paper describes a simulation model of PHEV integration with the grid. This model provides primary PHEV charging and discharging scenarios based on the general PHEV owner behaviors and the typical PHEV charging circuitry configuration. Initially, the uncontrolled PHEV charging scenarios are performed to evaluate the impact of the PHEV loading on the distribution grid operation. The night charging scenario is chosen for detailed analysis and the load flow is used to calculate the power distribution and loss on the 33-bus test power network. The results indicate the inadequacy of current power capacity to meet the growing electricity demand from PHEVs. A simple control method of off-peak charging is performed to show the improvement in voltage levelling and line loading. Therefore, the appropriate control scheme should be derived for regulating the PHEV charging and discharging. An optimal algorithm is proposed for utilizing the PHEV charging and discharging power in a distribution system to minimize the total real power loss. During charging period, the power rate of individual battery charging is coordinated according to the optimal objective and constraints of charger, battery and power grid. Compared to the uncontrolled PHEV charging results, the optimal algorithm can achieve the maximum loss reduction for each charging scenario. Moreover, voltage drop at each node is limited in a tolerable range while the tightened branch current restrictions are satisfied.

Novel Circuitry Configuration with Paired-Cell Erase Operation for High-Density 90-nm Embedded Resistive Random Access Memory

We propose a novel circuitry configuration for high-density 90-nm embedded resistive random access memory (ReRAM). The memory cells are operated at 2 V, and a small memory cell size of 6F2 consisting of a 1.2-V standard transistor and a resistive junction (1T–1R) is designed, where F is the feature size. The unique circuitry configuration is that each pair of source-lines connects to each source-line selective gate. Therefore, erasing is done by a pair of cells in turn in the whole sector, while the reading or programming is done by a random accessing operation. We simulated the ReRAM circuit for read and write operations with SPICE. As a result, we found that 5-ns high-speed read access was obtained in the 256-word lines (WLs) × 256-bit lines (BLs) and that the SET/RESET operation was stable.

HDL modeling of convective accelerometers for system design and optimization

This study concerns the integration of convective accelerometers on CMOS. The design approach is based on an HDL modeling of the sensing cell. The development of a monolithic system is then undertaken, using multi-domain simulations, within the microelectronics design environment. For illustration, the sensor equivalent input noise (i.e. the resolution) is computed for various readout circuitry configurations: a simple instrumentation amplifier, a customized low-noise amplifier and a chopper-stabilized amplifier with a track-and-hold signal demodulator. Finally, a noise equivalent acceleration below 1 mg/√Hz has been reached, which is interesting for applications in consumer electronics.

On‐board non‐linear circuitry for Ku‐band active arrays

AbstractActive phased arrays will play an important role in future satellite communications, because of the system flexibility and potential reconfigurability that they may provide.Therefore, an investigation of the relationship existing between payload characteristics and the synthesis parameters of this kind of antenna may constitute a helpful tool.To this end, a parametric analysis of the on‐board non‐linear circuitry of the transmitting system (power and up‐converter sections) has been carried out, establishing the dependence of the mass and DC power demand on the number of beams and feeds of the transmitting phased array.The parametric investigation has been, in particular, applied to an active imaging phased array and an active direct radiating phased array whose suitability to provide a multibeam coverage of Western Europe at Ku band has been demonstrated within an ESA/ESTEC contract.This paper describes the parametric approach followed in the investigation of the on‐board non‐linear subsystems of the active transmitting phased arrays.The assumed circuitry configurations are widely commented, and the parametric curves for the case of imaging and direct radiating phased arrays are reported.

Uranium detector available to public

This study concerns the integration of convective accelerometers on CMOS. The design approach is based on an HDL modeling of the sensing cell. The development of a monolithic system is then undertaken, using multi-domain simulations, within the microelectronics design environment. For illustration, the sensor equivalent input noise (i.e. the resolution) is computed for various readout circuitry configurations: a simple instrumentation amplifier, a customized low-noise amplifier and a chopper-stabilized amplifier with a track-and-hold signal demodulator. Finally, a noise equivalent acceleration below 1 mg/√Hz has been reached, which is interesting for applications in consumer electronics.