Circuit Topology Research Articles

From Finite Element Simulations to Equivalent Circuit Models of Extracellular Neuronal Recording Systems Based on Planar and Mushroom Electrodes.

define a new methodology to build multi-compartment lumped-elements equivalent circuit models for neuron/electrode systems. the equivalent circuit topology is derived by careful scrutiny of accurate and validated multiphysics finite-elements method (FEM) simulations that couple ion transport in the intra- and extracellular fluids, activation of the neuron membrane ion channels, and signal acquisition by the electronic readout. robust and accurate circuit models are systematically derived, suited to represent the dynamics of the sensed extracellular signals over a wide range of geometrical/physical parameters (neuron and electrode sizes, electrolytic cleft thicknesses, readout input impedance, non-uniform ion channel distributions). FEM simulations point out phenomena that escape an accurate description by equivalent circuits; notably: steric effects in the thin electrolytic cleft and the impact of extracellular ion transport on the reversal potentials of the Hodgkin-Huxley neuron model. our multi-compartment equivalent circuits match accurately the FEM simulations. They unveil the existence of an optimum number of compartments for accurate circuit simulation. FEM simulations suggest that while steric effects are in most instances negligible, the extracellular ion transport affects the reversal potentials and consequently the recorded signal if the electrolytic cleft becomes thinner than approximately 100 nm. the proposed methodology and circuit models improve upon the existing area and point contact models. The coupling between the extracellular concentrations and reversal potential highlighted by FEM simulations emerges as a challenge for future developments in lumped-element modeling of the neuron/sensor interface.

Calibration of multiple shunted piezoelectric transducers with correction for residual modes and shunt interactions

Piezoelectric shunt damping can be used for efficient vibration mitigation of a single or multiple vibration modes of a structure. Several analytical tuning expressions have been derived for numerous circuit topologies for a single shunt. However, when multiple shunted piezoelectric transducers are attached to a flexible structure, their individual interactions alongside the spill-over from residual modes affect the calibration accuracy. In this paper, explicit correction terms that represent these effects are presented for multiple shunted piezoelectric transducers targeting a single vibration mode. The correction terms are obtained from the evaluation of effective electromechanical coupling factors, while proper balancing between shunts follows from an assumed proportionality between shunt forces. The proposed correction method is applicable to general shunt architectures, for which tuning is available when targeting a single-degree-of-freedom structure. Its ability to regain nearby optimal damping properties is illustrated numerically for the classic series RL shunt.

Observation of Multiple Topological edge States in Square-Root electric circuits

Square-root topological states are new topological phases, whose intriguing topological properties are inherited from the parent lattice Hamiltonian. Because of the square-root procedure, the bulk gap of the parent Hamiltonian is doubled. In this letter, we report the observation of the square-root topological insulators (SRTIs) in topological LC circuits, whose squared Hamiltonian includes a Su-Schrieffer-Heeger (SSH) model, a well-known example of topological insulators (TI). The multiple localized edge states falling in different bandgaps are observed with characteristic phase structures, in sharp contrast to the discrete diffraction in a topologically trivial structure. These edge states with zero energy are manifested by a prominent impedance peak at the midgap frequency and directly observed by impedance measurements. Our work opens up an alternative gateway towards actively controllable topological systems and may bring about new possibilities in topology-driven electronic devices.

Improving the specific impulse of Hall thrusters using a wide channel design

This paper proposes increasing the width of the discharge channel to improve the specific impulse of Hall thrusters. In our study, we significantly increased the achievable channel width by optimizing the magnetic circuit topology, and the design freedom of the Hall thruster was improved. A prototype of a wide-channel high-specific-impulse Hall thruster was designed and experimentally verified. The effects of channel width on the discharge process and the characteristics of an aft-loaded magnetic field Hall thruster were investigated. The high-intensity luminous region did not diffuse radially with an increase in the channel width, and the plasma was always concentrated near the channel centerline. A wider channel is more conducive for improving the propellant utilization efficiency, thereby effectively improving the specific impulse of the Hall thruster. By optimizing the discharge channel width, the upper limit of the discharge voltage was increased, and the maximum specific impulse was increased from 3170 to 3794 s, a relative improvement of 20%. The effect of the specific impulse improvement at the same discharge voltage was analyzed and discussed. The results of this study are significant for the design of high-specific-impulse Hall thrusters.

PSO Training Neural Network MPPT with CUK Converter Topology for Stand-Alone PV Systems Under Varying Load and Climatic Conditions

Temperature and irradiance levels are two examples of environmental variables that affect the power value produced by photovoltaic panels. Therefore, in order to transfer the maximum power value from the PV panel to the load under varying climatic conditions, maximum power point tracking (MPPT) algorithms and DC-DC converter topologies are used. In this study, the performances of boost converter and CUK converter circuit topologies are investigated under variable irradiance and variable load conditions by using a neural network-based MPPT algorithm learning particle swarm optimization (PSO). As the first scenario, it is analyzed assuming that the temperature and irradiance values coming to the panel are constant. As the second scenario, the performance evaluation of the converter topologies according to the current, voltage and power parameters is made for the variable load situation. As the last scenario, the difference in the irradiance value coming to the panel depending on the sun's condition during the day has been examined. Canadian Solar CS6P-250P PV panel is used in the study. 50 kHz is selected as the switching frequency. According to the results obtained, it has been observed that the CUK converter circuit topology reaches the maximum power point faster than the boost converter circuit topology both in dynamic environmental conditions and load change, and the oscillation at this point is less. It is aimed to increase the performance of this method, which uses boost converter topology and MPPT in the literature, by applying CUK converter topology.

Повышение формализации задач верификации топологии и электрической схемы для систем автоматизированного проектирования

The article discusses the study of methods for checking the conformity of the topology and electrical circuit in electronic devices. The authors present a new approach to the analysis and verification of topological structure taking into account electrical characteristics, which leads to increased formalization of problems and provides better optimization of interaction between a person and a computer CAD system. The study includes an analysis of modern methods and tools used in the electronic device design process, and also proposes innovative approaches to ensure consistency between topology and electrical functionality. LVS verification of the project using Caliber, xRC extraction of the project, physical verification of the project using CAD software Cadence Physical Verification System (PVS), LVS verification of the project using PVS are performed. Presents a detailed analysis of the integrated circuit verification process performed using modern CAD tools. The work examines the key stages of verification, including LVS verification of the project using the Caliber tool, xRC extraction of the project, as well as physical verification of the project using the Cadence Physical Verification System (PVS). Particular attention is paid to LVS checks, which are an important design step to ensure compliance with the topology and electrical design. The features of using Caliber to perform LVS checks are discussed, as well as the xRC extraction process to extract parameters of resistors and capacitors. For physical verification of the project, the capabilities of Cadence PVS were used, which provides analysis of compliance of the physical implementation of the circuit with the specified rules. The results obtained and the experience presented in the article can be useful for engineers and researchers involved in the design of integrated circuits, as well as for those interested in the application of modern CAD tools in the field of verification and validation of electronic devices.

Joint Learning Neuronal Skeleton and Brain Circuit Topology with Permutation Invariant Encoders for Neuron Classification

Determining the types of neurons within a nervous system plays a significant role in the analysis of brain connectomics and the investigation of neurological diseases. However, the efficiency of utilizing anatomical, physiological, or molecular characteristics of neurons is relatively low and costly. With the advancements in electron microscopy imaging and analysis techniques for brain tissue, we are able to obtain whole-brain connectome consisting neuronal high-resolution morphology and connectivity information. However, few models are built based on such data for automated neuron classification. In this paper, we propose NeuNet, a framework that combines morphological information of neurons obtained from skeleton and topological information between neurons obtained from neural circuit. Specifically, NeuNet consists of three components, namely Skeleton Encoder, Connectome Encoder, and Readout Layer. Skeleton Encoder integrates the local information of neurons in a bottom-up manner, with a one-dimensional convolution in neural skeleton's point data; Connectome Encoder uses a graph neural network to capture the topological information of neural circuit; finally, Readout Layer fuses the above two information and outputs classification results. We reprocess and release two new datasets for neuron classification task from volume electron microscopy(VEM) images of human brain cortex and Drosophila brain. Experiments on these two datasets demonstrated the effectiveness of our model with accuracies of 0.9169 and 0.9363, respectively. Code and data are available at: https://github.com/WHUminghui/NeuNet.

A simple passive floating memristor emulator circuit

In this research article, we propose a passive two-terminal floating memristor emulator circuit (MEC). The proposed MEC consists of two NMOS transistors, one PMOS transistor and one capacitor. The MEC has a simple circuit topology structure and is more advantageous for integration, which has a chip area of only 218.04 μm2. The circuit can operate without additional bias and performs well in the high frequency environment at 50 MHz. Some of the memristor’s characteristics, such as pinched hysteresis loop and non-volatility, are verified using the Cadence Virtuoso environment with 0.18 μm SMIC technology. The MEC has also been successfully proven to be effective and reliable through the temperature variation, process corner variation and Monte Carlo analysis. In addition, we built a circuit for experimental testing by using the CD4007s to verify the theoretical and simulated results. Finally, the proposed memristor emulator circuit is applied to logic circuits.

Riemannian quantum circuit optimization for Hamiltonian simulation

Hamiltonian simulation, i.e. simulating the real time evolution of a target quantum system, is a natural application of quantum computing. Trotter-Suzuki splitting methods can generate corresponding quantum circuits; however, a faithful approximation can lead to relatively deep circuits. Here we start from the insight that for translation invariant systems, the gates in such circuit topologies can be further optimized on classical computers to decrease the circuit depth and/or increase the accuracy. We employ tensor network techniques and devise a method based on the Riemannian trust-region algorithm on the unitary matrix manifold for this purpose. For the Ising and Heisenberg models on a one-dimensional lattice, we achieve orders of magnitude accuracy improvements compared to fourth-order splitting methods. The optimized circuits could also be of practical use for the time-evolving block decimation algorithm.

Emergent energy dissipation in quantum limit

Energy dissipation is of fundamental interest and crucial importance in quantum systems. However, whether energy dissipation can emerge without backscattering inside topological systems remains a question. As a hallmark, we propose a microscopic picture that illustrates energy dissipation in the quantum Hall (QH) plateau regime of graphene. Despite the quantization of Hall, longitudinal, and two-probe resistances (dubbed as the quantum limit), we find that the energy dissipation emerges in the form of Joule heat. It is demonstrated that the non-equilibrium energy distribution of carriers plays much more essential roles than the resistance on energy dissipation. Eventually, we suggest probing the phenomenon by measuring local temperature increases in experiments and reconsidering the dissipation typically ignored in realistic topological circuits.

Positive‐to‐negative tunable delay circuit designed with NGD RC network

SummaryDespite the performed progressive research work, the interpretation of the negative group delay (NGD) function remains not familiar to non‐specialist design and fabrication circuit engineers. The functionality misunderstanding limits the NGD circuit applications compared to other classical electronic functions. The present paper deals with the design of a tunable circuit by operating with positive and negative delay behaviors. The topology of the tunable circuit by using a low‐pass (LP) type NGD circuit is described. The design formulas for calculating the circuit resistor and capacitor parameters from the desired delay are expressed. The design feasibility of the tunable circuit composed of LP‐NGD cell and RC‐circuit is validated with a proof‐of‐concept (PoC) implemented on a test board. Two different signals with pulse and arbitrary waveforms having tens‐milliseconds duration were considered during the validation tests. As expected by tuning a varistor from 0.4 kΩ to 1 kΩ, the negative delay behavior varying from about −0.4 ms was verified thanks to the time‐advanced effect due to the LP‐NGD property. Then, the output signal delay was observed to become positive when the varistor was tuned from 1 kΩ to 3 kΩ.

The Design of Low Power Op-amp for Biomedical Application

This work presents a low-power operational amplifier (op-amp) circuit design which optimized and tailored specifically for biomedical circuit application in low power environment. The proposed op-amp design incorporates the folded cascode differential amplifier technique with a low voltage supply 1.2 V, utilizing current biasing, current mirrors, and adopted low-power circuit topologies. AC and DC analysis are carried out to analyse the performance of the proposed design. Extensive simulations executed using industrial standard EDA tool have validated the circuit design, and demonstrated a gain of 70.94 dB, UGBW of 4.90 MHz, GM of 52.70 dB, PM of 82.02 degrees, PSRR of 82.77 dB, CMRR of 100.78 dB, and total power dissipation of only 28.07 mW. Low power consumption is essential for biomedical circuit applications, and the result shows a significant power reduction without compromising other performance parameters. The proposed op-amp circuit design is suitable to be implemented in low-power and high-performance biomedical devices.

Design and Implementation of Improved Gate Driver Circuit for Sensorless Permanent Magnet Synchronous Motor Control

Reliable motor control is important for electric vehicle applications. The control process requires accurate measurements of the current and rotor position information to establish correct motor control design, particularly in sensorless permanent magnet synchronous motor control systems. Practical issues regarding the motor control circuit, such as the effects of parasitic element behavior on the switching components in the insulated gate bipolar transistor-driven inverter, were discussed in this study. It analyzed the effects of parasitic elements that can cause the ringing of switching losses and affect the spike of the signal in the motor current, which must be avoided in the implementation of motor control. The gate driver circuit topology was improved to reduce this effect in motor control devices. The proposed gate driver circuit design with the ringing suppression circuit configuration achieved good performance by keeping the signal spike at less than 10% in the motor current. Furthermore, a signal spike or noise was not observed in the estimation results of rotor position when using current information as the parameter control process. Both conditions were verified by experiments on the designed motor control devices. Under these conditions, signal precision can be achieved in motor control.

Design of oscillatory neural networks by machine learning.

We demonstrate the utility of machine learning algorithms for the design of oscillatory neural networks (ONNs). After constructing a circuit model of the oscillators in a machine-learning-enabled simulator and performing Backpropagation through time (BPTT) for determining the coupling resistances between the ring oscillators, we demonstrate the design of associative memories and multi-layered ONN classifiers. The machine-learning-designed ONNs show superior performance compared to other design methods (such as Hebbian learning), and they also enable significant simplifications in the circuit topology. We also demonstrate the design of multi-layered ONNs that show superior performance compared to single-layer ones. We argue that machine learning can be a valuable tool to unlock the true computing potential of ONNs hardware.

Bisection Neural Network Toward Reconfigurable Hardware Implementation.

A hardware-friendly bisection neural network (BNN) topology is proposed in this work for approximately implementing massive pieces of complex functions in arbitrary on-chip configurations. Instead of the conventional reconfigurable fully connected neural network (FC-NN) circuit topology, the proposed hardware-friendly topology performs NN behaviors in a bisection structure, in which each neuron includes two constant synapse connections for both inputs and outputs. Compared with the FC-NN one, the reconfiguration of the BNN circuit topology eliminates the remarkable amount of dummy synapse connections in hardware. As the main target application, this work aims at building a general-purpose BNN circuit topology that offers a great amount of NN regressions. To achieve this target, we prove that the NN behaviors of the FC-NN circuit topologies can be migrated to the BNN circuit topologies equivalently. We introduce two approaches including the refining training algorithm and the inverted-pyramidal strategy to further reduce the number of neurons and synapses. Finally, we conduct the inaccuracy tolerance analysis to suggest the guideline for ultra-efficient hardware implementations. Compared with the state-of-the-art FC-NN circuit topology-based TrueNorth baseline, the proposed design can achieve 17.8- 22.2× hardware reduction and less than 1% inaccuracy.

Protection adaptability analysis method for photovoltaic grid-connected generating system

Inverter power sources such as photovoltaic inverters and SVG have unique fault characteristics compared to traditional synchronous motors due to their unique power generation methods, circuit topology, and low-voltage traversal control strategies. The power grid faces various adverse effects due to the ongoing expansion of photovoltaic power station (PV power station) capacity. How to comprehensively analyze the impact of photovoltaic power stations above 1000 MW on power grid relay protection has become a problem. Therefore, a protection adaptability analysis method for photovoltaic grid-connected generating systems is proposed, which is suitable for engineering analysis before the connection of large-capacity PV power stations to ensure the safety of the power system. And it is found that current differential protection exhibits better adaptability than distance protection.

Incoherent feedforward loop dominates the robustness and tunability of necroptosis biphasic, emergent, and coexistent dynamics

Biphasic dynamics, the variable-dependent ability to enhance or restrain biological function, is prevalent in natural systems. Accompanied by biphasic dynamics, necroptosis signaling also appears emergent and coexistent dynamics. However, it remains elusive how the properties of these dynamics are characterized by specific circuit structures and components. Starting with necroptosis circuit modeling, we systematically analyzed the network topology for achieving RIP1-dependent biphasic, emergent, and coexistent (BEC) dynamics. RIP1-RIP3-Caspase-8 (C8) incoherent feedforward loop embedded with positive feedback of RIP3 to RIP1 is identified as the core topology. The peak value of RIP3 phosphorylation is determined to present a scale-invariant feature, dictating BEC dynamics and the bell-shaped regulation of necroptosis biphasic dynamics. To quantitatively determine the uncertainty of necroptosis coexistent dynamics, potential landscape and Shannon entropy that measure entropy production during cell death are introduced for the first time. Further random necroptosis circuit analysis identifies the bell-shaped regulation of necroptosis biphasic dynamics by RIP3 auto-phosphorylation, which acts as a complementary process for robustly attaining BEC dynamics. Finally, we searched all possible two- and three-node circuit topologies to screen those that could perform BEC dynamics. A complete atlas of three-node circuit BEC dynamics is generated and only three minimal circuits emerge as robust solutions, confirming incoherent feedforward loop is the core topology. Analysis of the association between the minimal circuit structure and robustness proves that the identified optimal functional achievement structure is highly consistent with the experimental observed RIP1-RIP3-C8 topology. Overall, through highlighting a finite set of circuits, this study yields guiding principles that enable the mapping, modulation, and design of circuits for BEC dynamics in diverse synthetic biology applications.

A Critical Review of Compensation Converters for Capacitive Power Transfer in Wireless Electric Vehicle Charging Circuit Topologies

A Critical Review of Compensation Converters for Capacitive Power Transfer in Wireless Electric Vehicle Charging Circuit Topologies

Examination and experimental comparison of dc/dc buck converter topologies used in wireless electric vehicle charging applications

The studies on Wireless Power Transfer (WPT) technology and peripherals in Electric Vehicle (EV) applications are intensifying. While the energy received from the WPT system is transferred to the EV battery, the direct current (dc)/dc converter circuits are used. The dc/dc buck converter topologies are one of them. The converter circuits must be highly efficient, lightweight, and compact to have a high range in EV vehicles. There are asynchronous buck, synchronous buck, and interleaved synchronous buck converter circuit topologies from the literature. In this study, the efficiency results of these circuit topologies were analyzed using MATLAB/Simulink and experimental studies. This study contributes to the literature by conducting circuit-level efficiency analysis and component-level power loss analysis. It has been observed that the interleaved synchronous buck converter circuit operates at 99% efficiency at 1066 W. In addition, it has been shared with the oscilloscope results that the current ripples of this circuit topology are lower than other circuit converters. Specifically, there has been a significant reduction of 56% in power losses, particularly in the interleaved synchronous buck converter (ISBC). This study analyzes the dynamic behavior of the dc/dc buck converter topologies, and results about their performance are given.

An efficient algorithm for estimating gate-level power consumption in large-scale integrated circuits

Estimating power dissipation in Very Large Scale Integrated (VLSI) circuits, particularly large-scale sequential circuits, is a significant challenge in Electronic Design Automation (EDA). Benchmarked against PrimeTime PX, the proposed algorithm proficiently analyzes large-scale combinational and sequential circuits. This research begins with a power analysis algorithm for combinational circuits, focusing on signal probability (SP) and transition count (TC). It then extends to sequential circuits, introducing methodologies for loopback issues and a validity-checking mechanism for spatial dependency topology. Developed on the OpenTimer open-source framework using the SMIC 40-nm process library, the algorithm was validated on academic and industrial datasets. Experimental evaluations show that our algorithm outperforms in terms of speed and accuracy. For power analysis with vector annotations, it achieves an average error within 0.16% in power testing of large-scale timing circuits. It also performs gate-level vectorless power analysis on complex topology and large-scale integrated circuits, demonstrating computational robustness.