Circuit Speed Research Articles

Mathematical Approaches to Circuit Optimization in VLSI Design

Exceptionally Huge Scale Integration (VLSI) plan is continuously trying to find ways to improve circuit speed, lower control utilize, and make the finest utilize of space. A big portion of coming to these objectives is utilizing numerical strategies, which allow organized ways to form circuits work way better. This paper looks at a number of distinctive numerical methods and how they can be utilized in VLSI plan. It centers on how well these strategies can progress the value and productivity of circuits. Optimization calculations, like mimicked toughening, hereditary calculations, and molecule swarm optimization, are a prevalent way to see at math issues. Iteratively investigating plan regions is how these strategies discover combinations that grant superior execution measures, such as speed, control, and zone. Case considers appear that they are great at moving forward complicated circuits, appearing enormous picks up in plan parameters compared to old-fashioned heuristic strategies. Scientific modeling is additionally exceptionally imperative for accurately appearing how a circuit will work and anticipating execution measurements some time recently the genuine application. Direct programming and numbers programming are two strategies that offer assistance software engineers set limits and objectives, which leads to superior circuit structure and asset allotment. These models offer assistance individuals make choices by giving them numbers that appear the trade-offs between diverse plan objectives, like speed vs. power consumption or range minimization. Utilizing huge information sets and prescient analytics, machine learning procedures have moreover changed optimization strategies since they were included to VLSI plan.

Enhanced CPU Design for SDN Controller.

Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compared to other transistor technologies regarding energy efficiency and circuit speed. To the best of our knowledge, this is the first time that a ternary design has been applied inside the CPU of an SDN controller. Earlier studies focused on Ternary Content-Addressable Memory (TCAM) in SDN. This paper proposes a new 1-trit Ternary Full Adder (TFA) to decrease the propagation delay and the Power-Delay Product (PDP). The proposed design is compared to the latest 17 designs, including 15 designs that are 1-trit TFA CNTFET-based, 2-bit binary FA FinFET-based, and 2-bit binary FA CMOS-based, using the HSPICE simulator, to optimize the CPU utilization in SDN environments, thereby enhancing programmability. The results show the success of the proposed design in reducing the propagation delays by over 99% compared to the 2-bit binary FA CMOS-based design, over 78% compared to the 2-bit binary FA FinFET-based design, over 91% compared to the worst-case TFA, and over 49% compared to the best-case TFAs.

Analyzing performance: Error-efficient, low-power recursive inexact multipliers for CNN applications

In present scenario, significant data manipulations can be espied in image processing and Convolutional Neural Networks (CNNs) applications. The quality performance of these applications relies ponderously on arithmetic operations. In this context, Approximate Computing frequently finds its application, where a certain margin of error is deemed acceptable, on prioritizing circuit speed over absolute precision and the common focus lies on optimizing the binary multiplier which is a crucial yet power-intensive component, so as to streamline the complexity of above mentioned applications. Furthermore, Inexact Multipliers (IMs) are developed by using recursive method, thereby purveying enhanced design and error metrics. This paper introduces higher order Recursive-Based Inexact Multipliers (RBIMs), which integrates the suggested 4-bit IMs, and exact multipliers along with the recursive method, aiming to provide a delicate balance between design performance metrics and error tolerance. For evaluating the proposed approach, most of the existing and recently suggested IMs operating at 8-bit and 16-bit, are designed in Verilog, coded in Python, synthesized and simulated using Cadence Register Transfer Language (RTL) Compiler, Google Colabs. Eventually, the simulation results bespeak a notable improvement in power consumption, with the 8-bit and 16-bit RBIMs by outperforming the previous designs up to 36.9 %, and 35.5 % respectively. Further, the efficacies of the RBIMs are validated through its usage in image processing and CNN applications.

Specific Investigations Concerning the Improveable Multiplier Architecture of High-Speed and Area-Efficient Adders

Over the past few decades, the growth of portable devices such as laptops, mobile phone and personal digital assistant has resulted in increasing demand for complex functionality with effective computation. The present day technology is known for digital systems with very high computing capabilities. The demand for high speed, low power integrated circuits for portable devices has become crucial. The never ending growing complexities of integrated circuit for future devices pose a challenging task for integrated circuit designer. Cost effective integrated circuits requires the design meeting out the challenging task to optimize power, area with high performance. Hence this research focuses on the optimization of area, power and speed of Arithmetic circuits, Very Large Scale Integrated circuits (VLSI) are widely used in Arithmetic circuits, Digital Signal Processing (DSP), Image and Video Processing applications

TREAFET: Temperature-Aware Real-Time Task Scheduling for FinFET based Multicores

The recent shift in the VLSI industry from conventional MOSFET to FinFET for designing contemporary chip-multiprocessor (CMP) has noticeably improved hardware platforms’ computing capabilities, but at the cost of several thermal issues. Unlike the conventional MOSFET, FinFET devices experience a significant increase in circuit speed at a higher temperature, called temperature effect inversion (TEI), but higher temperature can also curtail the circuit lifetime due to self-heating effects (SHEs). These fundamental thermal properties of FinFET introduced a new challenge for scheduling time-critical tasks on FinFET-based multicores that how to exploit TEI towards improving performance while combating SHEs. In this work, TREAFET , a temperature-aware real-time scheduler, attempts to exploit the TEI feature of FinFET-based multicores in a time-critical computing paradigm. At first, the overall progress of individual tasks is monitored, tasks are allocated to the cores, and finally, a schedule is prepared. By considering the thermal profiles of the individual tasks and the current thermal status of the cores, hot tasks are assigned to the cold cores and vice-versa. Finally, the performance and temperature are balanced on-the-fly by incorporating a prudential voltage scaling towards exploiting TEI while guaranteeing the deadline and thermal safety. Moreover, TREAFET stimulates the average runtime frequency by employing an opportunistic energy-adaptive voltage spiking mechanism, in which energy saving during memory stalls at the cores is traded off during the time slice having the spiked voltage. Simulation results claim TREAFET maintains a safe and stable thermal status (peak temperature below 80 °C) and improves frequency up to 17% over the assigned value, which ensures legitimate time-critical performance for a variety of workloads while surpassing a state-of-the-art technique. The stimulated frequency in TREAFET also finishes the tasks early, thus providing opportunities to save energy by power gating the cores, and achieves a 24% energy delay product (EDP) gain on average.

Synergistic polarization engineering of dielectric towards low-voltage high-mobility solution-processed ultraflexible organic transistors

The emerging wearable skin-like electronics require the ultra-flexible organic transistor to operate at low voltage for electrical safety and energy efficiency and simultaneously enable high field-effect mobility to ensure the carrier migration ability and the switching speed of circuits. However, the currently reported low-voltage organic transistors generally present low mobility, originating from the trade-off between molecular polarity and surface polarity of the dielectrics. In this work, the orientation polarization of the dielectric is enhanced by introducing a flexible quaternary ammonium side chain, and the surface polarity is weakened by the shielding effect of the nonpolar methyl groups on the polar nitrogen atom. The resulting antisolvent QPSU dielectric enables the high-dielectric constant up to 18.8 and the low surface polarity with the polar component of surface energy only at 2.09 mJ/m2. Such a synergistic polarization engineering between orientation polarization and surface polarity makes the solution-processed ultraflexible transistors present the ultralow operational voltage down to −3 V, the ultrahigh charge-carrier mobility up to 8.28 cm2 V−1 s−1 at 1 Hz, excellent cyclic operational stability and long-term air stability. These results combined with the ultrathin thickness of transistor as low as 135 nm, the ultralight mass of 0.5 g/m2, the conformal adherence capability on human skin and 1-μm blade edge, and the strong mechanical robustness with stable electrical properties for 30,000 bending cycles, open up an available strategy to successfully realize low-voltage high-mobility solution-processed organic transistor, and presents the potential application of QPSU dielectric for the next-generation wearable imperceptible skin-like electronics.

Manipulation of high-frequency spin waves in ferromagnetic thin films via magnetic torques induced by ultrafast demagnetization

Spin-based technologies demand the effective excitation and control of high-frequency spin waves in order to increase the operational speed of magnonic logic circuits. An available option for the high-frequency spin wave is the perpendicular standing spin waves (PSSWs) in ferromagnetic thin films. However, the practical utilization of a PSSW is still challenging due to a few unsolved critical issues such as its relatively low amplitude and simultaneous excitation of other PSSW modes. Here, efficient excitation and control of a first-order PSSW mode are demonstrated in Ni80Fe20 thin films using a double-laser-pulse scheme. Based upon our experimental and theoretical investigations, it is found that the precession amplitudes of the Kittel and PSSW modes show strong dependence on equivalent torques (i.e., the averaged torques during fast relaxation process after the second pulse excitation) applied to these two modes. Thus, selective excitation and amplification of the first-order PSSW mode can be realized by manipulating the equivalent torque, i.e., introducing a second laser pulse with an appropriate arrival time and laser fluence. Moreover, the spectral tuning of this single PSSW mode can be achieved by proportionately adjusting the laser fluence of two pump pulses. These findings may pave the way for the realization and construction of future high-performance spintronic devices.

Latent Toehold-Mediated DNA Circuits Based on a Bulge-Loop Structure for Leakage Reduction and Its Application to Signal-Amplifying DNA Logic Gates.

DNA circuits based on successive toehold-mediated DNA displacement reactions, particularly entropy-driven DNA circuit (EDC) systems, have attracted considerable attention as powerful enzyme-free tools for dynamic DNA nanotechnology. However, background leakage (noise signal) often occurs when the circuit is executed nonspecifically, even in the absence of the appropriate catalyst DNA (input). This study designed and developed a new latent toehold-mediated DNA circuit (LDC) system that relies on a bulge-loop structure as a latent toehold toward leakage reduction. Furthermore, the number (size) of nucleotides (nt) in the bulge-loop is found to play a significant role in the performance (i.e., leakage, signal, and kinetics) of LDC systems. In fact, the signal rate for the LDC systems increased as the number of nt in the bulge-loop increased from 4 to 8, whereas the leakage rate of the LDC systems with bulge-loops of 7 nt or less was low, but the leakage rate of the LDC system with a bulge-loop of 8 nt increased significantly. Note that the LDC system with the optimal bulge-loop (7 nt) was capable of not only reducing the leakage but also accelerating the circuit speed without any signal loss, unlike methods of reducing the leakage by reducing the signal reported previously for the conventional EDC systems. These facts indicate that the 7 nt bulge-loop acts as a "latent" toehold for the DNA circuit system. By using the amplification function of output signals with an accelerated circuit and reduced leakage, our LDC system with a 7 nt bulge-loop could be applied directly and successfully to signal-amplifying DNA logic gates such as OR and AND gates, and thus, sufficient output signals could be obtained even with a small amount of input. These findings reveal that our LDC systems with a bulge-loop structure can replace the conventional EDC system and have enormous potential in the field of DNA nanotechnology.

CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications

In modern Digital System design, adders are widely used in many applications including Microprocessors, Digital Signal Processors, Arithmetic Logic Units and digital signal processing. Power efficiency is an important key factor for any integrated circuits. By considering the importance of Full Adder (FA) cells, their power consumption may play significant role in overall power consumption. So designing a low-power full adder is important to achieve the high-performance computing. Swing restored technique is commonly used method to reduce the signal swing at the internal nodes and it helps to reduce the power consumption and improves the circuit's speed. This paper presents a novel hybrid full adder cell design using the modified swing restored technique and complementary pass transistor logic. The Full Adder circuit was implemented using Cadence Virtuoso tool on gptk 180nm CMOS process technology. The proposed full adder was compared with earlier reported circuits based on Delay, Power and PDP. The comparison shows that proposed circuit consumes less power with high performance. Also various process corners and noise immunity were analyzed to find the sensitivity of the circuit. Further an 8-bit Ripple Carry Adder was designed using the proposed full adder to verify the functionality in higher order bits. Simulations were performed and analysed using the Cadence Spectre.

A Novel Mixture-Devices-Based Submodule for MMC by Using Low on-State Voltage IGCT and High di/dt Ability IGBT

At present, insulated-gate bipolar transistor (IGBT) is widely used as the converter component in the submodule of modular multilevel converter (MMC) for its excellent performance in driving circuit and switching speed, but the further application is restricted by its high conduction loss and cost rate. Integrated gate-commutated thyristor (IGCT) is another converter device used in MMC with low conduction loss and cost. However, the d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</i> /d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> capability of IGCT is limited so that a snubber circuit is required in the submodule for protection, which generates unwanted power loss for MMC. For better performance and reliability, this paper proposes a mixture-devices-based submodule (MS) for MMC based on the cooperation of parallel IGCT and IGBT devices. Double-pulse switching experiments for the MS are conducted to verify its effectiveness, and to get the data for the follow-up switching power loss calculation. The power loss of MMC based on IGBT, IGCT and mixture devices are calculated based on the model established in this paper. Furthermore, the comprehensive comparison for power loss among IGBT-based, IGCT-based and mixture-device-based MMCs are performed, proving the effectiveness of the mixture topology in terms of power loss reduction. Meanwhile, the proposed MS is cost-competitive.

A New Design Technique for a High-Speed and High dV/dt Immunity Floating-Voltage Level Shifter

This paper presents a high-speed level shifter with about 500 V/ns power supply slew immunity. In this designed structure, a narrow pulse-controlled current source is adapted to accelerate the voltage conversion and reduce the power consumption. A Fast-Slewing Circuit speeds up the operation of the level shifter based on the current comparison principle. Edge detection technology is used to filter the generated voltage noise and achieve high dV/dt immunity. The proposed level shifter simulated with the 0.18 μm BCD (bipolar-CMOS-DMOS) process shows fast responses with a typical delay of 1.49 ns and 500 V/ns dV/dt immunity in the 200 V high-voltage application, which only occupies a 0.022 mm2 active area with the 0.18 μm BCD process.

Modeling, Prediction, and Results Correction of PDSH Circuits for Nanosecond Pulse Peak Detection

The peak detect and sample hold (PDSH) circuit is an important component of the light detection and ranging (LiDAR) system, because the PDSH circuit can correct the walk error of the time discriminator, and distinguish different objects at the same location. However, due to the requirement for high-precision measurement of nanosecond-scale pulse signals, the design of the PDSH circuit presents significant challenges. This paper accomplishes the modeling of the PDSH circuit, including the modeling of the PDSH measurement speed and the voltage step, quantifies various factors that affect the PDSH circuit measurement results, and makes predictions based on the model. Through the derivation and simplification of the rise process in the PDSH circuit, this study establishes a mathematical model to predict the performance of the PDSH circuit. Furthermore, this study also investigates the effect of circuit delay time on the measurement speed of the PDSH circuit. Meanwhile, this study analyzes the voltage step process, and an equivalent circuit model is derived through theoretical analysis. By utilizing a fitting method, the equivalent capacitance value of the diode is obtained. The simulation and experiment results show that the errors between the measurement speed model of the PDSH circuit and the actual circuit are no more than 1.98 ns and 2.03 ns, respectively. Thus, the measurement speed model can accurately predict whether the PDSH circuit meets the requirements. Moreover, the maximum absolute error of the equivalent circuit model is 19.87 mV, which can significantly reduce the error caused by the voltage step.

Development of a DC Motor Speed Control System Based on PID

In the field of motion control systems, motor speed control plays a pivotal role. Various control algorithms and methods have been developed for this purpose, and one of the earliest strategies to emerge was analog control. Over time, it has evolved into a typical control structure with convenient parameter tuning capable of meeting general control requirements. This design is based on digital control algorithms, with the ST89C52 microcontroller as the control core. It generates pulse-width modulation (PWM) pulses controlled by a digital algorithm to regulate the speed of direct circuit (DC) motors. Additionally, it utilizes a photoelectric sensor to convert motor speed into pulse frequency, which is fed back to the microcontroller, thereby achieving closed-loop speed control and eliminating static speed errors.

SEU Hardened D Flip-Flop Design with Low Area Overhead.

D flip-flop (DFF) is the basic unit of sequential logic in digital circuits. However, because of an internal cross-coupled inverter pair, it can easily appear as a single event upset (SEU) when hit by high-energy particles, resulting in the error in the value stored in the flip-flop. On this basis, a new structure D flip-flop is proposed in this paper. This flip-flop uses an asymmetric scheme in which the master-slave latch adopts different hardening structures. By sacrificing circuit speed in exchange for stronger SEU fortification capability, the SEU threshold of this structure is improved by 10 times compared to traditional D flip-flops. It has also been compared with Dual Interlocked Storage Elements (DICEs), and it saves the area cost of six transistors compared to the DICE structure. Under the same operating conditions, the average power consumption and peak power consumption are, respectively, 9.8% and 18.8% lower than those of the DICE circuit, making it suitable for soft radiation environments where high circuit speed is not a critical requirement.

Effect of tilted magnetic field on the binding energy of a hydrogenic donor in a near triangular quantum well

ABSTRACT Low-dimensional semiconductor systems have attracted considerable attention of the researchers because of their applications such as speed circuits, optical devices etc. The application of external perturbations like magnetic field can change the properties of these systems. Study on tilted magnetic fields is of interest theoretically as it illustrates special confinement effects. In the present study, we calculate the binding energy of a hydrogenic donor in a quantum well with a potential profile proportional to |z|2/3, called Near Triangular Quantum Well (NTQW), in the presence of a magnetic field tilted by an angle θ with the growth axis, using variational method. Calculations of hydrogenic donor binding energies are made by varying the well width (L), Aluminium composition (x), strength of the magnetic field (γ) and the tilt angle (θ). Integrated probability density (P) of finding a hydrogenic donor in NTQW is also analysed as a function of well width (L).

Accurate Sneak-Path-Controlled Readout for a Cross-Point Resistive Sensor Array

A readout method of measuring resistances from a sensor array is proposed. As opposed to the conventional method of feedback readout, in which the crosstalk is suppressed by an op-amp, the sneak paths are controlled by switches, and a matrix equation of the circuit is derived from measured voltage. Thus, the scanning speed and power consumption of an interface circuit are not inherently deteriorated by the op-amp. The main factors affecting readout accuracy are parasitic resistance of the analog switch and quantized error of the analog-to-digital converters (ADCs). Therefore, calibration of switch resistance is also proposed to maintain readout accuracy by additional ADCs. To evaluate the proposed readout system, “sneak-path-controlled readout” (SPCR) and “accurate sneak-path-controlled readout” (ASPCR) are implemented. To verify the accuracy of the proposed readout method, the interface circuit and the calibration of switch resistance were simulated by MATLAB. The target array size was 32×32, and the sensor resistances were distributed in the same manner as real sensors. Since readout performance is also affected by the pattern of resistances, several patterns of resistance were prepared, and their results were compared. The results of the simulations show that SPCR using a 16-bit ADC can read normally distributed sensors with readout error of 0.05%. Moreover, ASPCR can handle a wider resistance distribution, and its readout error was less than 0.3% with a resistance pattern in which resistance ranges from 1.71 kΩ to 217 kΩ.

Research on multilayer fast equalization strategy of Li-ion battery based on adaptive neural fuzzy inference system

In this paper, an adaptive neuro fuzzy inference system (ANFIS) based multilayer fast equalization strategy for Li-ion batteries is developed to solve the problem of wrong fuzzy rule settings affecting the equalization speed in traditional fuzzy logic methods. Firstly, a multilayer equalization circuit is designed to perform both intra-group and inter-group equalization, and a Graph theory analysis shows that this circuit topology can perform fast equalization while ensuring better equalization efficiency. Then an adaptive neuro fuzzy inference system is designed based on the multilayer equalization circuit designed in this paper to achieve more accurate adaptive adjustment of the equalization current and reduce time consumption, and finally a comparative study of the equalization circuit and equalization method under static and charging/discharging conditions is conducted using the Matlab/Similink platform. The experimental study shows that the speed of the multilayer equalization circuit designed in this study is increased by about 62 % and 37.55 % compared with the traditional single-inductor equalization circuit and adjacent-inductor circuit, respectively. Compared with the conventional fuzzy logic control (FLC) equalization strategy, the speed of the proposed equalization strategy is improved by about 10.98 %. It effectively speeds up the equalization process of Li-ion batteries.

Approximate Unitary t-Designs by Short Random Quantum Circuits Using Nearest-Neighbor and Long-Range Gates

We prove that {{,textrm{poly},}}(t) cdot n^{1/D}-depth local random quantum circuits with two qudit nearest-neighbor gates on a D-dimensional lattice with n qudits are approximate t-designs in various measures. These include the “monomial” measure, meaning that the monomials of a random circuit from this family have expectation close to the value that would result from the Haar measure. Previously, the best bound was {{,textrm{poly},}}(t)cdot n due to Brandão–Harrow–Horodecki (Commun Math Phys 346(2):397–434, 2016) for D=1. We also improve the “scrambling” and “decoupling” bounds for spatially local random circuits due to Brown and Fawzi (Scrambling speed of random quantum circuits, 2012). One consequence of our result is that assuming the polynomial hierarchy ({{,mathrm{textsf{PH}},}}) is infinite and that certain counting problems are #{textsf{P}}-hard “on average”, sampling within total variation distance from these circuits is hard for classical computers. Previously, exact sampling from the outputs of even constant-depth quantum circuits was known to be hard for classical computers under these assumptions. However the standard strategy for extending this hardness result to approximate sampling requires the quantum circuits to have a property called “anti-concentration”, meaning roughly that the output has near-maximal entropy. Unitary 2-designs have the desired anti-concentration property. Our result improves the required depth for this level of anti-concentration from linear depth to a sub-linear value, depending on the geometry of the interactions. This is relevant to a recent experiment by the Google Quantum AI group to perform such a sampling task with 53 qubits on a two-dimensional lattice (Arute in Nature 574(7779):505–510, 2019; Boixo et al. in Nate Phys 14(6):595–600, 2018) (and related experiments by USTC), and confirms their conjecture that O(sqrt{n}) depth suffices for anti-concentration. The proof is based on a previous construction of t-designs by Brandão et al. (2016), an analysis of how approximate designs behave under composition, and an extension of the quasi-orthogonality of permutation operators developed by Brandão et al. (2016). Different versions of the approximate design condition correspond to different norms, and part of our contribution is to introduce the norm corresponding to anti-concentration and to establish equivalence between these various norms for low-depth circuits. For random circuits with long-range gates, we use different methods to show that anti-concentration happens at circuit size O(nln ^2 n) corresponding to depth O(ln ^3 n). We also show a lower bound of Omega (n ln n) for the size of such circuit in this case. We also prove that anti-concentration is possible in depth O(ln n ln ln n) (size O(n ln n ln ln n)) using a different model.

Design of FIR Filter Using Low-Power and High-Speed Carry Select Adder for Low-Power DSP Applications

Adders are one of the basic arithmetic circuits of any processor, microcomputer, multiplication circuits, etc. Presently, the most substantial areas in the research of VLSI design are area, power, and efficient high-speed circuits. In this paper two new architectures Carry Select Adder (CSLA) using D-latch and CSLA using multiplexers are proposed to reduce the power, delay, and its efficiency is compared with conventional carry select adder (CSLA) and existing literature. Architectural level power reduction is the most important area where it plays a vital role in improving the speed and power of the overall circuit. The existing and proposed CSLAs are synthesized with the Synopsys EDA tool using 32 nm technology node is used for the design and implementation. The values obtained across technology in nm underline the dominance of the proposed adder architectures in terms of delay and energy and area efficiency. For the proposed architectures, the evaluation results show that 60%–75% improvement in delay and 22%–56%in power when compared to other architectures. Proposed architectures shows increment in area but overall are delay product reduces compares to existing designs The proposed CSLA-DLATCH-FIR obtained significant reduction for 16-bits for power (46.4 (µW)), delay (0.66), ADP (359.8 × 10–15), and PDP (30.63 × 10–15). While the proposed CSLA-MUX-FIR has attained substantial performance for power (52.44 (µW)), delay (0.82 ns), ADP (457.392 × 10–15), and PDP (42.9 × 10–15). With the use of this proposed CSLA, a FIR filter was able to significantly reduce its power and delay.

Efficient architecture for arithmetic designs using perpendicular NanoMagnetic Logic

As the process of scaling down continues at a rapid pace, there is a growing need for an alternative semiconductor device to replace CMOS. One of the alternatives that attracted a lot of attention is called nanomagnetic logic (NML). This is because NML delivers a high device density in addition to a non-volatility of stored information, beyond-CMOS technologies, and device work at room temperature. It is necessary to lower the circuit density and increase the speed of circuits like adders. Using emerging NML logic, we created a full-adder, and ripple carry adder (RCA) with a minimum area. As a result, the invented multilayer-based decimal design makes use of RCA, and full-adder, for innovative 3D topology. We used an NML framework built with perpendicular nanomagnetic (pNML) layers to simulate the characteristics of these devices. With the adder designs that have been offered the latency values are relatively low while performing exhaustive testing. Using pNML technology, a decimal adder has been constructed for the first time in the literature. In addition, simulations are carried out with the help of the Modelsim simulator. During the process of nanomagnetic designing consideration is given to both of these aspects as latency and area. To create an NML circuit, the tool MagCAD is employed. Results are better using the pNML environment-based full adder, RCA and decimal adder.