Circuit Specifications Research Articles

Identification System for Short-Circuit Fault Points in Concentrated Stator Windings of Motors

Motors serve as the primary power sources in a wide range of industrial fields. In recent years, their application has been expanded to electric and hybrid electric vehicles. As the performance of the motors installed in electric vehicles directly affects human life, it is critical to diagnose the condition of the windings. The objective of this article is to establish a method to identify the short-circuit fault points in concentrated stator windings based on the magnetic flux density distribution near the stator windings. Unlike with distributed windings, the coils are wound around the teeth in concentrated windings. Thus, it is expected that the accurate position specification of the short circuit can be realized if a detailed magnetic flux density distribution over the teeth is obtained with an appropriate magnetic field sensor. The problem of sensor positioning is solved with two stepper motors moving the search coil in the rotational and longitudinal directions independently at specified intervals. The excellent capability of the proposed system is verified through experiments using the stator winding employed in hybrid electric vehicles. The accuracy and sensitivity of the proposed identification system for short-circuit fault points may enable its practical application in industries, for example, shipping and periodic inspections as well as the production management of motors with concentrated stator windings.

NAPA-p1: monolithic nanosecond timing pixel for large area sensors, designed for future e + e - colliders

NAPA-p1 is a prototype Monolithic Active Pixel Sensor 'MAPS' developed as a first iteration towards meeting the detectors general requirements for future e + e - colliders. Long-term objective is to develop a wafer-scale sensor in MAPS with an area ∼ 10 cm × 10 cm. This article presents the motivations for the design choices of NAPA-p1, translating the physics requirement into circuit specifications. Simulations show a pixel jitter of < 400 ps-rms and an equivalent noise charge of 13 e -rms with an average power consumption of 1.15 mW/cm2 assuming a 1% duty cycle, meeting the target specifications. The prototype is designed in 65 nm CMOS imaging technology, with dimensions of 1.5 mm × 1.5 mm and a pixel pitch of 25 μm. The prototype chip has been fabricated and characterization results will be available soon.

On-Chip Tunable Active Inductor Circuit for Radio Frequency Ics

The work presents a design of a gyrator-based on-chip tunable active inductor (AI) which can become an integral part of high-frequency integrated circuits. The proposed AI uses the Floating gate technology-based PMOS (FGPMOS) simulation model, where the on-chip, non-volatile programming ability of FGPMOS is used as a tunable active feedback resistor. The circuit specifications are first derived for the application at 800MHz to 2GHz. The design is simulated at 350nm CMOS technology and shows a temperature sensitivity of 0.13mV/oC as well as a noise sensitivity of about 10.97nV/Hz. The precise programming range of inductance value from 3nH to 9nH can be achieved. The circuit has a power dissipation of 5.02mV and a moderately high-quality factor of about 120. The layout of the proposed circuit has been designed on Cadence Virtuoso and fabricated at ON-Semiconductor, C5 CMOS process foundry of MOSIS fabrication service, USA. The complete design has a chip area of 18x30µm2. The fabricated results illustrate the on-chip tuning ability of the proposed AI from 3nH to 7nH with the help of externally applied Tunnelling and Injection voltages, respectively. The proposed design also simulates a tunable bandpass filter and a tunable Low Noise Amplifier.

Comparative analysis of meta heuristics algorithm for differential amplifier design

The design of analog circuits is very essential for the development of system design based on electronics as the world is analog in nature. Furthermore, performance of emerging products depends on analog circuits for reduction of power dissipation and improvement of speed. Though in the system on chip (SoC) analog circuit consumes less, it is more complex to design it due to the analog circuit nature complexity. The job of the evolutionary algorithm (EA) in the process of optimization of an analog circuit based on complementary metal oxide semiconductor (CMOS) is to get the appropriate values that can be used for the design parameters of the given circuit in such a way such that all the targeted specification of the given circuit can be obtained. The chaotic serial particle swarm optimization (CSPSO) and cuckoo search (CS) algorithms are lower than to those found through the particle swarm optimization (PSO) and differential evolution (DE) algorithms. The CS algorithm obtained all the desired specifications with less power dissipation and the least total transistor area compared to those attained by the DE and PSO algorithms.

Active Compensation-Based Harmonic Reduction Technique to Mitigate Power Quality Impacts of EV Charging Systems

This article presents a novel active compensation-based harmonic reduction (ACHR) technique in order to mitigate the existing third harmonic component in the input current of the power factor corrector (PFC) circuit in electric vehicle (EV) charging systems. Traditional PFC control scheme includes an outer voltage loop to control the output dc voltage and an inner current loop to ensure that the grid current is sinusoidal. The work shows how third and other high-order harmonic components are created, while the signal is transmitting through the voltage control loop, and then, an analytical model is developed to calculate the dominant third harmonic magnitude according to the circuit specifications and control parameters. The ACHR approach takes advantage of multilevel filter design to prevent the presence of high-order odd harmonics in addition to mitigating the existing third harmonic component created by the voltage control loop before it is passed through the current control loop. ACHR is designed optimally, and its performance is analyzed in detail to have a robust and stable closed-loop system while keeping the characteristics of fundamental harmonic. A totem-pole boost PFC proof-of-concept is built to verify the proposed ACHR technique. The results show that the third harmonic magnitude is reduced from 244 mA in conventional control scheme to 130 mA in the proposed ACHR technique. Moreover, total harmonic distortion (THD) in input current is decreased from 4.88% to 4.03%.

Developmental pruning of sensory neurites by mechanical tearing in Drosophila.

Mechanical forces actively shape cells during development, but little is known about their roles during neuronal morphogenesis. Developmental neurite pruning, a critical circuit specification mechanism, often involves neurite abscission at predetermined sites by unknown mechanisms. Pruning of Drosophila sensory neuron dendrites during metamorphosis is triggered by the hormone ecdysone, which induces local disassembly of the dendritic cytoskeleton. Subsequently, dendrites are severed at positions close to the soma by an unknown mechanism. We found that ecdysone signaling causes the dendrites to become mechanically fragile. Severing occurs during periods of increased pupal morphogenetic tissue movements, which exert mechanical forces on the destabilized dendrites. Tissue movements and dendrite severing peak during pupal ecdysis, a period of strong abdominal contractions, and abolishing ecdysis causes non-cell autonomous dendrite pruning defects. Thus, our data establish mechanical tearing as a novel mechanism during neurite pruning.

Behavioral Analysis of Noise and Bandwidth Specifications of Heartbeat Detection Circuits for Ultra Low Power Devices

This paper presents the behavioral modeling of three circuit architectures, which are suitable for heartbeat detection in wireless healthcare applications. The developed front-end models implement an analog system that detects the heartbeats for lower power consumption and higher detection accuracy without digital signal processing. Therefore, the circuit blocks and their critical specifications specifically regarding the noise and bandwidth are evaluated. The architectures are implemented in Verilog-A and their behavior simulations use real electrocardiogram (ECG) signals with different characteristics and conditions. All architectures have amplification, band-pass and notch response blocks as their first three stages. Then, the first circuit architecture detects the heartbeat using an adaptive threshold based on a pulse width approach. The second heartbeat detection scheme finds the maximum and minimum values of each beat using a sample-and-hold-based peak detector. The third model uses a similar peak detection scheme, but delays the analog signal for better precision. The simulation results show that all models can detect heartbeats when the input noise is less than 20 μ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> , the third having the highest noise tolerance of around 50 μ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> . For the ECG signal to maintain its characteristics with respect to its positive and negative peak, the bandpass response should present a low cutoff frequency below 10 Hz.

Bayesian Optimization Approach for RF Circuit Synthesis via Multitask Neural Network Enhanced Gaussian Process

An RF integrated circuit design heavily relies upon experienced experts to iteratively tune the circuit parameters. A Bayesian optimization (BO) method is explored in existing works for automated analog and RF circuit synthesis. The overall performance can be further improved by constructing a model to exploit the correlation among different circuit specifications. In this article, we propose a BO approach for RF circuit synthesis via a multitask neural network enhanced Gaussian process (MTNN-GP). We present a novel multioutput GP model, in which the kernel functions of multiple outputs are constructed from a multitask neural network with shared hidden layers and task-specific layers. Therefore, the correlation between the outputs can be captured by the shared hidden layers. Our proposed MTNN-GP-based BO method is compared with several state-of-the-art BO methods on three real word RF circuits and achieves best performance. The experimental results demonstrate the effectiveness and efficiency of our proposed method.

Computational Methods for the Design of Recombinase Logic Circuits with Adaptable Circuit Specifications.

Synthetic biology aims at engineering new biological systems and functions that can be used to provide new technological solutions to worldwide challenges. Detection and processing of multiple signals are crucial for many synthetic biology applications. A variety of logic circuits operating in living cells have been implemented. One particular class of logic circuits uses site-specific recombinases mediating specific DNA inversion or excision. Recombinase logic offers many interesting features, including single-layer architectures, memory, low metabolic footprint, and portability in many species. Here, we present two automated design strategies for both Boolean and history-dependent recombinase-based logic circuits. One approach is based on the distribution of computation within multicellular consortia, and the other is a single-cell design. Both are complementary and adapted for non-expert users via a web design interface, called CALIN and RECOMBINATOR, for multicellular and single-cell design strategies, respectively. In this book chapter, we are guiding the reader step by step through recombinase logic circuit design, from selecting the design strategy fitting to their final system of interest to obtaining the final design using one of our design web interfaces.

Automated circuit sizing with multi-objective optimization based on differential evolution and Bayesian inference

Manual sizing of analog circuit specifications has become challenging owing to their ever-increasing complexity. Especially for innovative, large-scale circuit designs with numerous design variables, operating conditions, and conflicting objectives to optimize, analog designers must run time-consuming simulations for several weeks to find the optimum configuration. Recently, machine learning and optimization techniques have been applied in the field of analog circuit design, wherein evolutionary algorithms and Bayesian models have shown good results for circuit sizing tasks. In this context, we introduce multi-objective optimization based on differential evolution and Bayesian inference (MODEBI)—a design optimization method based on generalized differential evolution 3 (GDE3) and Gaussian processes (GPs). The proposed method can perform sizing for complex circuits that require optimization of many design variables and conflicting objectives. Although state-of-the-art methods reduce multi-objective problems to single-objective optimization and potentially induce a priori bias, the proposed method searches directly over the multi-objective space using Pareto dominance and ensures that designers are provided with diverse solutions to choose from. To reduce optimization time, we propose using GPs to model the circuit and employing this surrogate model to preselect candidates. However, this results in a more complex offspring selection process, and the diversity in population survival must be specifically addressed. This paper proposes several solutions to these problems, resulting in multiple MODEBI variations. To the best of our knowledge, this is the first method that specifically addresses solution diversity and simultaneously focuses on minimizing the number of simulations required to obtain feasible configurations. The evaluation performed on two voltage regulators with different complexity levels showed that the proposed offspring selection method and survival policy can obtain highly diverse feasible solutions considerably faster than GDE3 or Bayesian optimization-based algorithms.

Optimum Transistor Sizing of CMOS Differential Amplifier Using Tunicate Swarm Algorithm

In this paper, optimum transistor sizing of CMOS differential amplifier using tunicate swarm algorithm (TSA) is proposed. The designing of CMOS differential amplifier is activated to determine the best feasible design parameter values. This work proposes the optimized values of various parameters of a CMOS differential amplifier for better performance. TSA is chosen to optimize the circuit area. TSA has the ability to solve complex functions, like MOS transistor size and bias current. TSA is employed to optimize the parameters of circuit design, like area, power dissipation MOS transistor size, and also used to enhance other circuit specifications, while fulfilling circuit design criteria. The design objectives of CMOS differential amplifier are considered the fitness function of TSA algorithm. Then, weight parameters of CMOS differential amplifier design are optimized using TSA. By CMOS differential amplifier using TSA algorithm, we can optimize circuit design parameters with higher probability of yielding optimal results regarding circuit area lessening, lesser power dissipation and MOS transistor sizes. The proposed method is implemented in the MATLAB platform. The proposed CMOS-DA-TSA method attains 52.01%, 50.29% and 44.30% minimum slew rate, 64.61%, 75.30% and 55.92% minimum power dissipation compared to the existing methods like CMOS-ACD-SOA, CMOS-PAI-FOPSO and CMOS-PSO-MOL, respectively.

A superconducting nanowire-based architecture for neuromorphic computing

Neuromorphic computing would benefit from the utilization of improved customized hardware. However, the translation of neuromorphic algorithms to hardware is not easily accomplished. In particular, building superconducting neuromorphic systems requires expertise in both superconducting physics and theoretical neuroscience, which makes such design particularly challenging. In this work, we aim to bridge this gap by presenting a tool and methodology to translate algorithmic parameters into circuit specifications. We first show the correspondence between theoretical neuroscience models and the dynamics of our circuit topologies. We then apply this tool to solve a linear system and implement Boolean logic gates by creating spiking neural networks with our superconducting nanowire-based hardware.

Approximate Computing: Evolutionary Methods for Functional Approximation of Digital Circuits

Approximate computing deviates from long-held paradigm and attracted towards intrinsic application resilience to enhance the efficiency by relaxing the parameter of full accuracy. The specifications of digital circuits are violated while explicitly designing. The benefits are in terms of area, performance, power consumption, and speed. For approximating circuit, synthesis tools depend on available technique to check whether the synthesized circuit meets the set parameters and provides the quality. Mostly used approach is circuit simulator for analyzing responses received from all input variables but it is an exhaustive approach and can be used only for a small number of inputs. So this paper focuses on techniques, methods used to approximate circuits and to use formal methods for solving challenges faced by traditional methods. The use of evolutionary methods for circuits has led to the promising results. Major challenges in these methods are the ability to automatically synthesize approximation circuits without relying on the skill of designers. Strategies for generating approximate circuits, methodologies for evaluating the error with benchmarks used are tabulated in paper. The exact circuit, error and their approximate threshold are required for simplification which leads to selecting synthesis techniques for circuit transformations. The criteria of selection of approximate logic synthesis method are based on error analysis, number input and desired output, use of types of application and digital circuits like adder, multiplier, FIR, FFT etc. Introduction, principle, methods of approximate computing with major sub-areas of research work conducted in field of functional approximation which are apropos for designing and testing of circuits are main concern of paper.

High-Dimensional Many-Objective Bayesian Optimization for LDE-Aware Analog IC Sizing

With the advancement of complementary metal–oxide–semiconductor (CMOS) technologies, layout-dependent effects (LDEs) become increasingly influential to MOSFET characteristics and in turn analog integrated circuit performance. Early awareness of LDEs before the layout stage gets critical in order to help subsequent layout synthesis meet performance requirements and thus reduce design iteration. In this article, we propose a high-dimensional many-objective Bayesian optimization (HMBO)-based LDE-aware sizing methodology to address such challenges. It can effectively tackle the huge configuration space that is incurred by the increased number of optimization variables for considering the LDEs in addition to the conventional sizing variables. Moreover, our proposed method is able to aim for simultaneously satisfying multiple circuit specifications to identify an optimum design point within the enlarged configuration space. In addition, we propose a performance-driven pattern learning scheme called Gibbs-upper confidence bound (UCB) for better managing the dimension splitting. Our method is compared with several prevalent evolutionary algorithms as well as state-of-the-art Bayesian optimization works designed for analog circuit sizing problems. The experimental results demonstrate the high efficacy of our proposed sizing methodology.

Single event transient mitigation techniques for a cross‐coupled LC oscillator, including a single‐event transient hardened CMOS LC‐VCO circuit

Single-event transients (SETs) due to heavy-ion (HI) strikes adversely affect the electronic circuits in the sub-100 nm regime in the radiation environment. This study proposes techniques to mitigate SETs in CMOS voltage-controlled oscillators (VCOs) without affecting the circuit specifications. A circuit asymmetry technique is used for faster recovery of the oscillator in the event of a single event transient (SET) caused by an ion hit. Also, a new SET tolerant inductor capacitor-voltage controlled oscillator (LC-VCO) topology is proposed for a radiation environment that shows reduced phase displacement, amplitude displacement, and recovery time. A comparison has been made with various LC-VCOs that have an inherent rad-hard capability which proves a significant improvement in SET sensitivity.

A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis

Analog and mixed-signal (AMS) computer-aided design tools are of increasing interest owing to demand for the wide range of AMS circuit specifications in the modern system on a chip and faster time to market requirement. Traditionally, to accelerate the design process, the AMS system is decomposed into smaller components (called modules ) such that the complexity and evaluation of each module are more manageable. However, this decomposition poses an interface problem, where the module’s input-output states deviate from when combined to construct the AMS system, and thus degrades the system expected performance. In this article, we develop a tool module-linking-graph assisted hybrid parameter search engine with neural networks (MOHSENN) to overcome these obstacles. We propose a module-linking-graph that enforces equality of the modules’ interfaces during the parameter search process and apply surrogate modeling of the AMS circuit via neural networks. Further, we propose a hybrid search consisting of a global optimization with fast neural network models and a local optimization with accurate SPICE models to expedite the parameter search process while maintaining the accuracy. To validate the effectiveness of the proposed approach, we apply MOHSENN to design a successive approximation register analog-to-digital converter in 65-nm CMOS technology. This demonstrated that the search time improves by a factor of 5 and 700 compared to conventional hierarchical and flat design approaches, respectively, with improved performance.

High-level fault injection to assess FMEA on critical systems

Embedded systems in critical applications are constrained by very strict standards, but safety analysis (e.g., Failure Mode and Effects Analysis, or FMEA) of these systems is often empirical and mainly relies on the experience of engineers. Performing empirical analyses on complex designs is a major challenge that leads engineers to make very pessimistic assumptions and consequently to over-design multiple countermeasures. Many fault injection techniques have been developed to evaluate the robustness of Register Transfer Level (RTL) hardware designs. With these techniques, robustness is evaluated by comparing the faulty circuit outputs with the circuit specifications or golden RTL fault-free simulations. However, these techniques are too circuit centered, and therefore do not account for the overall system specifications. In addition, with complex hardware designs, fault simulations become very time-consuming. In this paper, we present a new high-level fault injection approach taking into account the overall critical system specifications to extract acceptable circuit parameter ranges while speeding up the evaluation process. We describe a case study of a real airborne system. The critical parameter ranges are determined for the circuit. Then, these ranges are used to rapidly evaluate the robustness of each RTL block in the circuit.

Efficient Formal Verification of Galois-Field Arithmetic Circuits Using ZDD Representation of Boolean Polynomials

In this study, we present a new formal method for verifying the functionality of Galois-field (GF) arithmetic circuits. Assuming that the input–output relation (i.e., the specification of a GF arithmetic circuit) can be represented as polynomials over 2, the proposed method formally checks the equivalence between GF polynomials derived from a netlist and the specification. To efficiently verify the equivalence, we employ a zero-suppressed binary decision diagram (ZDD) to represent polynomials over 2. Even though polynomial reduction is the most time-consuming process of verification (i.e., equivalence checking), our new algorithm can efficiently reduce the GF polynomials in the form of a zero-suppressed binary decision diagram derived from the target netlist. The proposed algorithm derives the polynomials representing all intermediate nodes (i.e., the outputs of all gates) in the order from primary inputs to those primary outputs that are in accordance with the reverse topological traversal order. We demonstrated the efficiency and effectiveness of the proposed method via a set of experimental verifications. In particular, we confirmed that the proposed method can verify practical GF multipliers (including those used in standardized elliptic curve cryptography) approximately 30 times faster on average and at most 170 times faster than the best conventional method.

Concurrent design of Schottky diode limiter and LNA

In this paper concurrent design of Schottky diode based limiter and low noise amplifier (LNA), based on noise matching, is investigated to achieve minimum noise figure (NF) of the receiver chain. In design procedure of the LNA, the noise figure is minimum, gain at central frequency is 14.5 dB, and limiter structure tolerates up to 5 W continuous wave input power. In the proposed concurrent design, a pass-band filter is applied at the LNA output to attenuate undesired out-of-band signals. In the proposed design, the limiter-LNA is implemented with a 0.25 µm gate length AlGaAs/InGaAs pHEMT process. Measured noise figure of chain is 2.7 dB and average gain over 8.5–9.5 GHz frequency range and the gain at 9 GHz center frequency are 10 dB and 14.5 dB respectively. The performance results of proposed matching network are compared with traditional 50 Ω matching networks in limiter-LNA with identical circuit specifications.

Design and Build IoT-Based Lavender Plant Smart Pots

This research started from plant observation, preparation, design of component and circuit specifications, assembly, work steps, and evaluation. The results of the study will prove the tool works or not, if the soil moisture sensor detects the soil moisture is reduced by 50%, then the sensor will respond and send a signal to the microcontroller to activate the relay so that the pump will turn on automatically. The monitoring system on the device can be accessed via a smartphone, the signal is sent by the smartphone and then captured by the microcontroller, then processed and the output can be an image of the monitored plant. This tool is also equipped with a water reservoir that can also be monitored from a smartphone. If the water in the reservoir reaches 30% of the capacity of the reservoir, the Water Level sensor will send a signal to the microcontroller and warn that the water level is very low, then send an order to the owner to immediately fill the reservoir. At night this tool is also equipped with an LDR sensor if the light intensity is less then the LED will light up.