Circuit Primitives Research Articles

Modular Modeling of Analog Organic Neuromorphic Circuits: Toward Prototyping of Hardware-Level Spiking Neural Networks

This work proposes a novel modeling approach for analog organic circuits using very simple to customize circuit topology and parameters of individual p- and n-type organic field effect transistors (OFETs). Aided with the combination of primitive elements (OFETs, capacitors, resistors), the convoluted behavior of analog organic neuromorphic circuits (ONCs) and even other general analog organic circuits, can be predicted. The organic log-domain integrator (oLDI) synaptic circuit, the organic differential-pair integrator (oDPI) synaptic circuit, and the organic Axon-Hillock (oAH) somatic circuit are designed and serve as the modular circuit primitives of more complicated ONCs. We first validate our modeling approach by comparing the simulated oDPI and oAH circuit responses to their experimental measurements. Thereafter, the summation effects of the excitatory and inhibitory oDPI circuits in prototyped ONCs are investigated. We also predict the dynamic power dissipation of modular ONCs and show an average power consumption of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.1 \mu \text {J}$ </tex-math></inline-formula> per spike for the oAH soma at a ~1 Hz spiking frequency. Furthermore, we compare our modeling approach with other two representative organic circuit models and prove that our approach outperforms the other two in terms of accuracy and convergence speed.

Physical Limitations on Fundamental Efficiency of SET-Based Brownian Circuits

Brownian circuits are based on a novel computing approach that exploits quantum fluctuations to increase the efficiency of information processing in nanoelectronic paradigms. This emerging architecture is based on Brownian cellular automata, where signals propagate randomly, driven by local transition rules, and can be made to be computationally universal. The design aims to efficiently and reliably perform primitive logic operations in the presence of noise and fluctuations; therefore, a Single Electron Transistor (SET) device is proposed to be the most appropriate technology-base to realize these circuits, as it supports the representation of signals that are token-based and subject to fluctuations due to the underlying tunneling mechanism of electric charge. In this paper, we study the physical limitations on the energy efficiency of the Single-Electron Transistor (SET)-based Brownian circuit elements proposed by Peper et al. using SIMON 2.0 simulations. We also present a novel two-bit sort circuit designed using Brownian circuit primitives, and illustrate how circuit parameters and temperature affect the fundamental energy-efficiency limitations of SET-based realizations. The fundamental lower bounds are obtained using a physical-information-theoretic approach under idealized conditions and are compared against SIMON 2.0 simulations. Our results illustrate the advantages of Brownian circuits and the physical limitations imposed on their SET-realizations.

Efficient Parallel Binary Operations on Homomorphic Encrypted Real Numbers

A number of homomorphic encryption application areas could be better enabled if there existed a general solution for combining sufficiently expressive logical and numerical circuit primitives. This paper examines accelerating binary operations on real numbers suitable for somewhat homomorphic encryption. A parallel solution based on Single Instruction Multiple Data (SIMD) can be used to efficiently perform combined addition, subtraction and comparison-based operations on packed binary operands in a single step. The result maximises computational efficiency, memory space usage and minimises multiplicative circuit depth. General application and performance of these accelerated binary primitives are demonstrated in a number of case studies, including min-max and sorting operations.

(Invited) In-Memory Computing with Memristor Circuit Primitives

The dramatic rise of data-intensive workloads has revived special-purpose hardware and architectures for continuing improvements in computational speed and energy efficiency. While traditional CMOS ASICs deliver some performance gains, typically by limiting data movement or implementing “in-memory computation”, such approaches still suffer from low power efficiency. Therefore, new proposals leveraging non-volatile memristive devices for in-memory computation are highly attractive in a variety of application domains. While originally developed for as digital (binary) high density non-volatile memories, memristive devices have demonstrated a wide range of behaviors and properties – such as a wide range of tunable analog resistance and non-linear dynamics – which motivate their use in novel functions and new computational models. Many recent in-memory compute studies have focused on crossbar circuit architectures, demonstrating their application for neural networks, scientific computing and signal processing. However, other circuit primitives – such as content addressable memories (CAMs) and combined systems such as crossbar arrays and non-linear elements– have shown further promise for mapping a diverse range of complimentary computational models such as finite state machines, pattern matching, hashing algorithms and Hopfield networks for tackling optimization problems. In this talk, I will review the different exciting opportunities for in-memory computational primitives levering non-volatile memristive devices and their circuits and architectures for enabling low power, high-throughput computation in a variety of application domains. I will also highlight the different materials and device requirements which steer material stack design and fabrication for these diverse circuits and application domains. Finally, I will show recent lab demonstrations of various applications mapped to these in-memory computational circuit primitives based on memristor devices, and give an outlook on performance.

Majority-Logic, its applications, and atomic-scale embodiments

Today's computing is increasingly data-intensive, heralding the age of big data. With greater data volumes, come the needs for faster processing, greater storage capacity, and expanded communication bandwidth, all of which imply the expenditure of more energy. Thus, energy efficiency, already a major design consideration, will assume broader significance in the coming years. As important as storage and communications are, our focus in this paper is on better technology to reduce the computation (logic manipulation) power. We review majority logic, a special case of threshold logic, show how a number of common arithmetic/logic operations can be performed using the majority-gate primitive, and review an impressive array of atomic-scale logic technologies that are particularly efficient in realizing the majority or minority function. We conclude that a combination of orders of magnitude energy reduction by virtue of the technology used and implementation strategies that lead to comparable complexity in terms of majority gates when contrasted with currently used circuit primitives (AND, OR, XOR, NOT, mux) leads to energy-efficient realization of arithmetic/logic functions suitable for use in the age of big data.

Experimental Demonstrations of Security Primitives With Nonvolatile Memories

This article provides a comprehensive review of experimental work on security primitives based on emerging and mature nonvolatile memories (NVMs). The focus is on physically unclonable functions (PUFs) that exploit process-induced variations to generate a die-specific random response. We identify two main types of the proposed designs and discuss their advantages and main challenges. Endurance and reliability are serious concerns in PUFs relying on large-signal stochastic switching properties of NVMs in the verification phase. Such designs do not seem to be appealing in terms of energy, throughput, and security. On the other hand, circuit primitives that exploit sneak-path current and device nonlinearity are genuinely more suitable for building strong PUFs, but they are susceptible to environmental variations. Achieving high reliability in such PUFs is the main challenge, and finding a practical holistic solution with integrated optimum security and performance characteristics is an important research direction. We further note that many PUF works have been performed on a single memory cell level. The proposed implementations and their performance projected based on experimental data show a low bit error rate, however, at the cost of poor resilience to modeling attacks. Without further justification, these approaches can be only classified for now as weak PUFs, and moreover, more work would be needed to verify their physical unclonability. This article is concluded by outlining the most urgent experimental and modeling future work and the exciting prospects for NVM-based PUFs.

Low Pass Filter PUF: Authentication of Printed Circuit Boards Based on Resistor and Capacitor Variations

Physical Unclonable Functions (PUFs) are probabilistic circuit primitives that extract randomness from the physical characteristics of a device. PUFs are easy and simple to implement and its random nature makes its behavior hard to predict and model. Most existing PUF designs are based on variation at the chip level and can not be implemented in a printed circuit board (PCB). Therefore, these PUFs can not be used to protect against counterfeit PCBs in a distributed supply chain. In this work, we propose a novel PUF design based on resistor and capacitor variations for low pass filters (LoPUF). We demonstrate the setup in a protoboard for different resistor-capacitor pairs (RC pairs) for reliable low pass filter PUF. Because of process variations, the voltage will be different at the same cut-off frequency for our proposed PUF. Finally, the output of the filter is connected to an inverter to measure the pulse width and best suitable pulses are used for ID generation based on our algorithm.

Optimized Search-and-Compute Circuits and Their Application to Query Evaluation on Encrypted Data

Private query processing on encrypted databases allows users to obtain data from encrypted databases in such a way that the users’ sensitive data will be protected from exposure. Given an encrypted database, users typically submit queries similar to the following examples: 1) How many employees in an organization make over U.S. $100000? 2) What is the average age of factory workers suffering from leukemia? Answering the questions requires one to search and then compute over the relevant encrypted data sets in sequence. In this paper, we are interested in efficiently processing queries that require both operations to be performed on fully encrypted databases. One immediate solution is to use several special-purpose encryption schemes simultaneously; however, this approach is associated with a high computational cost for maintaining multiple encryption contexts. Another solution is to use a privacy homomorphic scheme. However, no secure solutions have been developed that satisfy the efficiency requirements. In this paper, we construct a unified framework to efficiently and privately process queries with search and compute operations. For this purpose, the first part of our work involves devising several underlying circuits as primitives for queries on encrypted data. Second, we apply two optimization techniques to improve the efficiency of these circuit primitives. One technique involves exploiting single-instruction-multiple-data (SIMD) techniques to accelerate the basic circuit operations. Unlike general SIMD approaches, our SIMD implementation can be applied even to a single basic operation. The other technique is to use a large integer ring (e.g., $\mathbb {Z}_{2^{t}}$ ) as a message space rather than a binary field. Even for an integer of $k$ bits with $k>t$ , addition can be performed using degree 1 circuits with lazy carry operations. Finally, we present various experiments performed by varying the considered parameters, such as the query type and the number of tuples.

ASIC implementation of a hardware‐embedded physical unclonable function

Within-die variations in path delays are increasing with scaling. Although higher levels of within-die delay variations are undesirable from a design perspective, they represent a rich source of entropy for applications that make use of ‘secrets’, such as authentication, hardware metering and encryption. Physical unclonable functions or PUFs are a class of circuit primitives that leverage within-die variations as a means of generating random bitstrings for these types of applications. In this study, the authors present test chip results of a hardware-embedded delay PUF (HELP) that extracts entropy from the stability characteristics and within-die variations in path delays. HELP obtains accurate measurements of path delays within core logic macros using an embedded test structure called regional delay behaviour (REBEL). REBEL provides capabilities similar to an off-chip logic analyser, and allows very fast analysis of the temporal behaviour of signals emerging from paths in a core logic macro. Statistical characteristics related to the randomness, reproducibility and uniqueness of the bitstrings produced by HELP are evaluated across industrial-level temperature and supply voltage variations.

An open architecture for the massively parallel emulation of the Drosophila brain on multiple GPUs

The fruit fly Drosophila melanogaster is an exceedingly useful model organism for studying the causal links between neural circuits and behavior due to the numerical tractability of its brain and its powerful neurogenetic toolkit. Recent progress made in identifying the connectome of the fruit fly [1,2] and in characterizing the input and output functions of its sensory neural circuits [3] raise the possibility of creating and emulating a functional model of the entire fly brain using the increasingly powerful commodity parallel computing technology available to computational neuroscientists. To this end, we have developed an open software architecture for emulating neural circuit modules in the fly brain and their responses to recorded or simulated input stimuli on multiple Graphics Processing Units (GPUs). A key feature of this architecture is its support for integrating instances of different neural circuit models developed by independent researchers by requiring that the models’ implementations provide interoperable interfaces that adhere to the specification prescribed by the architecture. We refer to the architecture as a Neurokernel because it provides object classes essential to the emulation of the entire fruit fly brain that are analogous to those provided by an operating system kernel: (1) it serves as an extended machine that provides access to neural circuit primitives needed to construct and interconnect models of neural circuit modules in the fly brain; and (2) it serves as a resource allocator that scalably and transparently assigns GPU resources to emulated neural circuit models without manual specification by the researcher [5]. In order to provide these features, the Neurokernel architecture comprises several planes of abstraction that separate its application, control, and computing aspects (Fig. ​(Fig.1).1). Models of brain function implemented using the architecture use the application plane’s API to access neural circuit primitives without directly specifying which GPU resources to use. The architecture’s control plane automatically partitions and maps circuits to available GPU resources, and manages communication between multiple GPUs hosted locally or remotely. Storage methods used to efficiently represent large networks of neurons and synapses with feedback connections in GPU memory and numerical methods used to update neuron and synapse states are implemented in the computing plane. Figure 1 Neurokernel architecture We implemented key elements of the Neurokernel software using the Python programming language and the PyCUDA interface to NVIDIA’s CUDA GPU programming environment [4] to avail ourselves of the increasingly powerful ecosystem of scientific computing Python software and make the architecture accessible to other researchers in the neuroscience community.

A Translinear, Log-Domain FPAA on Standard CMOS Technology

A field-programmable analog array (FPAA) using a standard-CMOS wide-dynamic-range translinear element (TE) is introduced. The FPAA configurable analog blocks (CABs) are based on a reconfigurable translinear cell (RTC), capable of implementing the basic circuit elements required by translinear and log-domain circuit design. The interfacing is provided by an I/O programmable cell, which allows for easier connectivity between the signal-processing core and the external circuitry. As a proof-of-concept, a 5 × 5 RTC FPAA testchip was implemented in 0.35- μm CMOS technology. A set of various circuit primitives, such as one- and four-quadrant multipliers, an Euclidean distance operator and a fourth-order log-domain filter, were mapped on the chip in order to demonstrate the versatility of the approach. FPAA bandwidth reaches 20 MHz with a power consumption of 30 μW/TE and precision errors below 3%.

On the properties of the input pattern fault model

A review of traditional IC failure analysis techniques strongly indicates the need for fault models that directly analyze the function of circuit primitives. The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit module, independent of the design level. We describe the IP fault model and provide a method for analyzing IP faults using standard single stuck-line- (SSL-) based fault simulators and test generation tools. The method is used to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder. Improved IP fault coverage for the benchmarks and the adder is obtained by adding a small number of test patterns to tests that target only SSL faults. We also conducted fault simulation experiments that show IP test patterns are effective in detecting nontargeted faults such as bridging and transistor stuck-on faults. Finally, we discuss the notion of IP redundancy and show how large amounts of this redundancy exist in the benchmarks and in SSL-irredundant adder circuits.

Modeling a verification test system for mixed-signal circuits

In contrast to the large number of logic gates and storage circuits encountered in digital networks, purely analog networks usually have relatively few circuit primitives (operational amplifiers and so on). The complexity lies not in the number of building blocks but in the complexity of each block and the need to test a range of parameters-for example, gain, bandwidth, and signal-to-noise ratio. Degraded circuit performance as well as nonfunctional operation must be checked. Thus, circuit complexity rather than volume complexity is the dominant problem in analog test, and testing mixed-signal circuits entails more difficulties than testing purely digital circuits. In IC manufacturing, circuits traditionally move from design to test with little thought about how each department's activities affect those of the other. This lack of foresight almost always results in iteration cycles between design and test to realize a testable design that also satisfies the specification. We need a bridge between design and test phases to enable a smooth transition. An integrated approach whereby both teams understand each other's requirements is a big step in the right direction; interaction between design and test databases significantly increases the degree to which design and test development can operate as concurrent processes; some work has already been done in this area. Our goal was to build Spice models for the instruments incorporated in the IntegraTest system so that we could simulate the tests this system conducts during design. The models are based on manufacturer specifications, and control parameters used in the models are as close as possible to those in the instruments. To make changes in the models transparent to users, entering of parameters is isolated from the models' internal construction. After building the models, we compared the results of the simulated tests with results from actual tests performed with real instruments.

Distributed proximity effect correction on a network of workstations

Proximity effect caused by electron scattering imposes a severe limitation on the ultimate resolution attainable with E-beam lithography. In most of the correction schemes proposed so far, the correction time is dependent on the number of circuit primitives. Correction of realistic circuit patterns containing a large number of primitives is severely limited due to the time-consuming nature of proximity effect correction and the computer memory required on a workstation. This problem continues to pose more and more challenges as the circuit size and density continue to increase. It is proposed to perform proximity effect correction in a distributed manner using a network of workstations as an efficient solution.

Dose, shape, and hybrid modifications for PYRAMID in electron beam proximity effect correction

As the dimensions of circuit primitives are reduced, the proximity effect becomes an increasingly important limiting factor in the fabrication of high density integrated circuits using electron beam (e-beam) lithography. In the past, proximity effect correction schemes have in general utilized one of two different approaches: dose or shape modification. Previously, PYRAMID, a hierarchical, rule-based proximity effect correction scheme which has been demonstrated to be able to correct circuit patterns with a minimum feature size of 0.1 μm was successfully presented. Although PYRAMID has been implemented with a pattern shape modification technique, its correction algorithms are not limited to this approach. In this article, the two approaches are compared in details in terms of CD error (edge placement error) and edge contrast, using the two corresponding versions of PYRAMID. A hybrid approach, i.e., combination of dose and shape modifications, is also considered.

Reducing recursive effect for fast proximity correction

Previously, we proposed PYRAMID, an efficient tool for proximity effect correction in electron-beam lithography. Because PYRAMID corrects circuit primitives one at a time it may suffer from the recursive effect (i.e., correction on one element affects how a previously corrected element should have been corrected). In this paper, we present two different methods for reducing the recursive effect and compare their performance in terms of accuracy and speed.

Region-wise proximity effect correction for heterogeneous substrates in electron-beam lithography: Shape modification

P Y R A M I D, a hierarchical rule-based scheme for proximity effect correction in electron-beam lithography, has been demonstrated to enable rapid correction of circuit patterns exposed on homogeneous substrates with minimum feature size of 0.1 μm. The current version of PYRAMID modifies the shape of circuit primitives. So far, it has been limited to homogeneous substrates only. This article describes an extension of our pattern shape modification scheme for heterogeneous substrates. The space-varying nature of a heterogeneous substrate makes exposure estimation and proximity correction more involved than in case of a homogeneous substrate. As a result, the schemes developed for homogeneous substrates cannot be used directly used to deal with heterogeneous substrates. A simple but effective approach has been implemented in an effort to allow our shape modification scheme to correct patterns on heterogeneous substrates. The principal idea is to correct a circuit region-wise where each region is homogeneous. A transition zone is defined between two adjacent regions of a substrate and additional adjustment is done on primitives within transition zones to get smooth transition between regions. A fuzzy factor, adjustment factor, is introduced to make the convergence of correction faster. This article describes the region-wise proximity effect correction scheme proposed for heterogeneous substrates and presents preliminary simulation results indicating successful correction.

Block-Level Logic Extraction from CMOS VLSI Layouts

This paper describes a Prolog based Block Extraction System (ProBES) which converts a transistor level description of a CMOS circuit into a logic block level description. The operation of ProBES is conceptually similar to that of a circuit extractor. However, whereas a circuit extractor is used to identify circuit primitives such as transistors, resistors and capacitors from the geometrical information in a mask level layout description, ProBES can be used to identify predefined gates and logic blocks in a CMOS transistor network. ProBES operates according to the circuit hierarchy. Basic gates such as inverters, transmission-gates, nands, nors, etc. are identified first. Logic blocks composed of these gates are then identified. More complex blocks which contain blocks already identified are recognized next and so on. ProBES is meant to be used as an aid in the verification of logic design. It can provide a connectivity check for a circuit.

Using FPGAs to implement self-timed systems

Asynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in a variety of applications. In order to ease the complexity of this style of design, however, suitable self-timed circuit primitives must be available to the system designer. This article describes a technique for building self-timed circuits and systems using a library of circuit primitives implemented using Actel field programmable gate arrays (FPGAs). The library modules use a two-phase transition signaling protocol for control signals and a bundled protocol for data signals. A first-in first-out (FIFO) buffer and a simple routing chip are presented as examples of building self-timed circuits using FPGAs.

CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current. >