Circuit Optimization Research Articles

QPSK circuit optimization Based on Model-Based Design

In order to address the difficult problem of hardware implementation of complex communication algorithm, this paper takes digital phase modulation as an example, and uses model-based design approach to quickly complete the algorithm modeling, simulation and automatic generation of HDL code. Model-based design is a fast and effective design process for algorithm modeling, simulation, testing and automatic code generation. The simulation results show that the model-based design method cannot only quickly accomplish the modeling and testing of the algorithm, but also improve the design accuracy.

A New Multicommodity Network Flow Model and Branch and Cut for Optimal Quantum Boolean Circuit Synthesis

This study introduces a new optimization model and a branch-and-cut approach for synthesizing optimal quantum circuits for reversible Boolean functions, which are pivotal components in quantum algorithms. Although heuristic algorithms have been extensively explored for quantum circuit synthesis, research on exact counterparts remains relatively limited. However, the need to design quantum circuits with guaranteed optimality is increasing, especially for improving computational fidelity on noisy intermediate-scale quantum devices. This study presents mathematical optimization as a viable option for optimal synthesis, with the potential to accommodate practical considerations arising in fast-evolving quantum technologies. We set a demonstrative problem to implement reversible Boolean functions using high-level gates known as multiple control Toffoli gates while minimizing a technology-based proxy called quantum cost—the number of low-level gates used to realize each high-level gate. To address this problem, we propose a discrete optimization model based on a multicommodity network and discuss potential future variations at an abstract level to incorporate technical considerations. A customized branch and cut is then developed upon different aspects of our model, including polyhedron integrality, surrogate constraints, and variable prioritization. Our experiments demonstrate the robustness of the proposed approach in finding cost-optimal circuits for all benchmark instances within a two-hour time frame. Furthermore, we present interesting intuitions from these experiments and compare our computational results with relevant studies, highlighting newly discovered circuits with the lowest quantum costs reported in this paper. History: Accepted by Giacomo Nannicini, Area Editor for Quantum Computing. This paper has been accepted for the INFORMS Journal on Computing Special Issue on Quantum Computing. Funding: This research was supported by the Ministry of Science and Information and Communication Technology, South Korea [Grants 2017R1E1A1A0307098814 and 2020R1A4A307986411]. Supplemental Material: The software that supports the findings of this study is available within the paper and its Supplemental Information ( https://pubsonline.informs.org/doi/suppl/10.1287/ijoc.2024.0562 ) as well as from the IJOC GitHub software repository ( https://github.com/INFORMSJoC/2024.0562 ). The complete IJOC Software and Data Repository is available at https://informsjoc.github.io/ .

AI in Biomedical Imaging and Diagnostics

Advances in artificial intelligence (AI) and synthetic biology have profoundly influenced biomedical research, creating transformative opportunities in imaging, diagnostics, and therapeutic engineering. In biomedical imaging, AI-driven algorithms enhance precision and accuracy, enabling automated analysis of complex datasets, real-time imaging insights, and identification of disease biomarkers. Meanwhile, synthetic biology redefines cellular engineering, particularly in T-cell research, by enabling customized functionalities, such as precision-targeted antigen recognition and tunable immune responses. The integration of AI into T-cell engineering amplifies these capabilities, facilitating the design and optimization of synthetic circuits, predictive modeling of cellular behaviors, and dynamic monitoring of therapeutic outcomes. This interdisciplinary approach is revolutionizing diagnostics and immunotherapy by streamlining the identification of disease-specific markers, improving diagnostic accuracy, and enabling real-time modulation of T-cell functionality within the tumor microenvironment. By combining AI-powered insights with synthetic biology's ability to engineer living systems, this research aims to address critical challenges in disease treatment, including tumor heterogeneity and immune evasion. This work explores the synergistic application of AI and synthetic biology in biomedical imaging and T-cell engineering, highlighting state-of-the-art technologies, their therapeutic potential, and the future landscape of personalized medicine.

Design and optimisation of a two-stage amplifier based on a differential input stage and a common-source amplifier

Abstract. Since the emergence of integrated circuits, through the circuit structure, the production process of continuous iterative updating, so that its used in various types of electronic equipment more and more widely. Currently, operational amplifier circuits play an extremely important role in signal processing and communication systems. Amplifiers have different characteristics depending on the needs of different electronic devices. This thesis addresses the optimisation and design of the characteristics of the two-stages amplifier. Firstly, several classical amplifier structures are analysed. Select the appropriate structure and combine it into a two-stages amplifier. Simulation is carried out on cadence software and later the simulation results are analysed before parameter optimisation. On this basis, a two-stages amplifier based on a PMOS differential input stage with a common-source amplifier has been designed. It also improves the amplifier's gain, frequency range, gain bandwidth, and other performance metrics. Using PMOS self-bias circuit to improve power supply stability. Finally, based on the development hotspots of integrated circuits, the possibility of circuit optimization was analyzed. Discussions were conducted on negative feedback circuits, phase compensation methods, and other aspects.

Improved PID control of DC motor

Abstract. In this paper, the circuit optimization problem of precise control of DC motor through PID interface is studied. The main purpose of this research is to strategically coordinate resistance and capacitance elements in circuit design to explore and improve the speed of signal transmission and the accuracy of response. Additionally, by optimizing the interaction between these components, this paper attempts to achieve improved performance and efficiency in the motor control system, that is, changing different K_p and K_d to achieve the best fit parameters for the most system. The experimental approach employed in this study involves a collaboration between Tinkercad and Falstad software platforms to simulate and analyze the effects of various circuit configurations as well as coefficients. The effects of K_p and K_d on the system are obtained through systematic experiments and analysis. Meanwhile, it aim to verify the proposed optimization technique and evaluate its effectiveness in practical applications. The simulation results of Tinkercad and Falstad agree well with the expected theoretical results.

Shallower CNOT circuits on realistic quantum hardware

We focus on the depth optimization of CNOT circuits on hardwares with limited connectivity. We adapt the algorithm from Kutin et al. [17] that implements any n -qubit CNOT circuit in depth at most 5 n on a Linear Nearest Neighbour (LNN) architecture. Our proposal is a block version of Kutin et al. ’s algorithm that is scalable with the number of interactions available in the hardware: the more interactions we have the less the depth. We derive better theoretical upper bounds and we provide a simple implementation of the algorithm. Overall, we achieve better depth complexity for CNOT circuits on some realistic quantum hardware like a grid or a ladder. For instance the execution of a n -qubit CNOT circuit on a grid can be done in depth 4 n + 8.

Implementation of a non-standard system for simplifying Peirce-Webb functions

The object of research are models of optimal logic circuits based on universal Peirce-Webb functions. The problem solved is the efficiency of the technique for simplifying the Peirce-Webb functions. The extension of the non-standard system to the simplification of Peirce-Webb functions makes it possible to discover new rules of equivalent transformations of Boolean functions, and to complete the simplification procedure in one step. A feature of the simplification of functions in the Peirce-Webb basis by a non-standard system is fixing the digital project at the level of abstraction, followed by the application of the mechanism of logical synthesis to generate the corresponding equivalent at the level of gates of the logic circuit. The result of the transformation of the terms of the binary matrix in the end is some combinatorial system, metadata that can explain other data, for example, determine the minimum function for another logical basis. The interpretation of the result consists in the use of combinatorial properties of binary structures of functions in the Peirce-Webb basis and binary structures of functions in the basic basis. These properties do not depend on the selected logical basis, which makes it possible to carry out equivalent transformations on binary matrices of Peirce-Webb functions according to the rules of the algebra of the main basis. It has been experimentally confirmed that a non-standard system enables: – to reduce the algorithmic complexity of simplifying the Peirce-Webb functions; – to increase the performance of the simplification of Peirce-Webb functions by 200–300 %; – to demonstrate the visibility of the process of simplifying functions. In terms of application, the non-standard system of simplifying the Peirce-Webb functions could ensure the transfer of innovations to material production: from conducting fundamental research, expanding the capabilities of digital component design technology to organizing serial or mass production of novelties.

A Research of the Integrated Circuit Design and Optimization

With the scientific and technical revolution going on, integrated circuit has been playing a vital role in our daily life ever since. In IC (Integrated circuit) design and manufacturing, layout of the integrated circuit determines its success or failure. However, the constantly decreasing characteristic size and progressive process bring about some new issues. That is why in post-Moore’s Law period, the design and optimization of layouts deserves attention of the whole industry. A properly designed and optimized layout not only results in better performance while using, but also cut out the cost of manufacture. In this paper, the methodology of integrated circuit layout design and optimization are discussed. For design, the author presented the whole flow of how the layout is generated and principles in integrated circuit design. For optimization, two approaches are analyzed. One is shorting out the critical area. Based on critical area theory and methodology of image processing, layouts can be improved in configuration. The method discussed here makes a modification on the previous way to make the optimization more accurate and efficient. The other method is inserting auxiliary polysilicon, which can counteract the impact of channel length change of MOSFETs and focus error as a unavoidable result of the process improvement.

A Survey on Quantum Computing Architectures: Implications for Electrical Circuit Design and Optimization

Quantum computing, a paradigm shift with the potential to revolutionize fields ranging from cryptography to optimization, is rapidly evolving. This survey delves into the key quantum computing architectures—gate-based and quantum annealing—and their profound impact on circuit design and optimization. Gate-based systems, such as those utilizing superconducting qubits and trapped ions, offer versatile platforms capable of executing a broad array of quantum algorithms. However, they present unique challenges for circuit designers, including noise sensitivity, scalability, and the need for complex error correction circuits. Quantum annealing, exemplified by D-Wave systems, offers a more specialized approach to solving optimization problems, requiring distinct circuit design considerations focused on energy efficiency and coherence preservation.This paper reviews the foundational research on these architectures, compares their respective design challenges, and examines the optimization techniques that have emerged in response to these challenges. Gate count reduction, error correction, and hybrid quantum-classical methods are highlighted as key approaches for improving circuit efficiency and scalability in quantum systems. Furthermore, this survey emphasizes the importance of interdisciplinary collaboration between quantum physicists, electrical engineers, and computer scientists to address the complex challenges associated with quantum circuit design. By combining expertise from these fields, researchers can develop innovative solutions that bridge the gap between theoretical concepts and practical hardware implementations. Ultimately, this survey underscores the need for continued innovation at the intersection of quantum computing and electrical engineering, as researchers strive to overcome current limitations and develop practical, large-scale quantum systems that can harness the full potential of this revolutionary technology.

Optimal circuit breaker allocation strategy in DC transmission-connected systems

The purpose of this study is to provide data for the best possible circuit breaker allocation in power grids with HVDC transmission while taking circuit breaker failure into account. The lack of a suitable selection of HVDC circuit breakers is one of the primary obstacles to establishing an appropriate protection system for HVDC transmission. This research focuses on finding the optimal circuit breaker allocation strategy with respect to the transient response of the system, especially when the grid operator is using existing circuit breakers, rather than on the necessary steps to improve the technology of circuit breakers. Case studies are simulated using PSCAD/EMTDC in order to verify the transient response of the transmission system corresponding to the allocation of circuit breakers and the circumstance of circuit breaker failure. It is crucial to remember that there isn’t a strategy that is always the best. Consequently, a detailed analysis of the suggested approach is required, taking into account the benefits and drawbacks from the standpoints of fault clearing, power system planning, and operational factors. In the context of HVDC transmission, the authors hope that their research will spark and start conversations about circuit breaker allocation strategies.

Magnetic Railway Sleeper Detector

In an ever expanding railway network all around the world, the need for track maintenance grows steadily. Traditionally, one major part of track maintenance is ramming large vibrating steel picks into the gravel between and under railway sleepers to compress the gravel and generate a safe substructure. Even today, maintenance personnel still have to manually locate the sleepers if they cannot be detected by computer vision systems or visually by the operator. Here we developed a first of its kind magnetic sleeper detector, even able to find sleepers, buried in gravel, undetectable by vision based systems. Our approach of magnetic detection is based on a DC magnetic field excitation and a detector moving with respect to the rail system, including the sleepers and fasteners for mounting the rails. Due to railway application constraints a large air gap between the sensor and the sleeper structure is required, which significantly complicates the magnetic sensing task for robust sleeper detection. The design and optimization of the magnetic circuit was based on extensive 3D simulation studies to ensure highest possible variation in magnetic flux density at the sensor locations for absence and presence of a sleeper. Furthermore, a low noise and high sensitivity electronic circuit has been realized to cope with sensor signal offsets from unknown or changing sensor orientations with respect to the earth’s magnetic field, or magnetic interferences from other trains potentially passing by during active measurements. Since we only want to detect sleepers in close vicinity of the moving sensor system, digital signal processing of the acquired signals can easily compensate for disturbing slowly changing or static field components within real world application scenarios. We demonstrate that magnetic detection of even buried sleepers on railway tracks is possible for distances of up to 172 mm between the sensor and the sleeper. This enables an even higher level of railway maintenance automation previously impossible in certain scenarios.

Noise Analysis and Suppression Methods for the Front-End Readout Circuit of a Microelectromechanical Systems Gyroscope

Circuit noise is a critical factor that affects the performances of an MEMS gyroscope. Therefore, it is essential to analyze and suppress the noises in the key analog circuits, which are the main noise sources. This study presents an optimized front-end readout circuit and noise suppression methods. First, the noise analysis of the front-end readout circuit is carried out with theoretical derivation to clarify the main noise contributors. To suppress the output noise, an improved readout circuit based on the T-resistor networks is proposed, and the corresponding noise equation is derived in detail. In addition, the noise analysis of the critical circuits of the detection and control system, such as the inverting amplifiers, the first-order low-pass filters, and the first-order high-pass filters, is carried out, and the noise suppression strategy with the optimization of the resistances and is proposed. Taking the inverting amplifier as an example, the theoretical derivation is verified by measuring and comparing the output noises of different resistance schemes. In addition, the output noises of the gyroscope before and after circuit optimization are measured. Experimental results demonstrate that the output noise with the circuit optimization is reduced from 60 μV/Hz1/2 to 30 μV/Hz1/2 and the bias instability is reduced from 3.8 deg/h to 1.38 deg/h. In addition, the ARW is significantly improved from 0.035 deg/h1/2 to 0.018 deg/h1/2, which indicates that the proposed noise analysis and suppression methods are effective and feasible.

Miniaturized Multiband Substrate-Integrated Waveguide Bandpass Filters with Multi-Layer Configuration and High In-Band Isolation

This article presents a multiband bandpass filter structure with an in-line topology based on substrate-integrated waveguide (SIW) technology. A multi-layer configuration is employed to achieve circuit miniaturization. By constructing the coupling matrix, the coupling relationships among all resonators are quantitatively characterized, enabling the extraction of the theoretical frequency response and guiding circuit modeling and optimization. We designed and fabricated a third-order tri-band SIW filter and a third-order quad-band SIW filter, achieving a return loss of nearly 20 dB across all passbands. The close agreement between simulated and measured results validates the proposed design model. Additionally, the high in-band isolation of over 40 dB is demonstrated between all adjacent bands, highlighting the potential applicability of this technology in multiband scenarios.

Optimal Twirling Depth for Classical Shadows in the Presence of Noise.

The classical shadows protocol is an efficient strategy for estimating properties of an unknown state ρ using a small number of state copies and measurements. In its original form, it involves twirling the state with unitaries from some ensemble and measuring the twirled state in a fixed basis. It was recently shown that for computing local properties, optimal sample complexity (copies of the state required) is remarkably achieved for unitaries drawn from shallow depth circuits composed of local entangling gates, as opposed to purely local (zero depth) or global twirling (infinite depth) ensembles. Here, we consider the sample complexity as a function of the depth of the circuit, in the presence of noise. We find that this noise has important implications for determining the optimal twirling ensemble. Under fairly general conditions, we (i)show that any single-site noise can be accounted for using a depolarizing noise channel with an appropriate damping parameter f, (ii)compute thresholds f_{th} at which optimal twirling reduces to local twirling for Pauli operators, (iii)nth order Renyi entropies (n≥2), and (iv)provide a meaningful upper bound t_{max} on the optimal circuit depth for any finite noise strength f, which applies to observables and entanglement entropy measurements. These thresholds strongly constrain the search for optimal strategies to implement shadow tomography and are easily tailored to the experimental system at hand.

REVOLUTIONIZING SEMICONDUCTOR DESIGN AND MANUFACTURING WITH AI

The semiconductor industry plays a vital role in driving technological advancements, and the incorporation of AI (Artificial Intelligence) can greatly enhance its efficiency and productivity. Through optimizing material usage and reducing defects, AI can significantly reduce costs and enhance production efficiency and product quality. However, despite the increasing interest in AI applications in the semiconductor industry, comprehensive reviews are lacking to systematically analyze existing research and identify the challenges and opportunities in this field. This review aims to bridge this gap by providing a thorough overview of AI-driven techniques in optimizing semiconductor manufacturing and offering valuable insights for future research directions. The integration of Artificial Intelligence (AI) into chip design marks a transformative phase for the semiconductor industry. Traditional design methodologies, often labor-intensive and time-consuming, are increasingly constrained by human expertise and iterative processes. Generative AI, utilizing advanced machine learning models such as Generative Adversarial Networks (GANs) and Variational Autoencoders (VAEs), offers innovative approaches to automate and optimize various stages of chip design. This paper examines how generative AI can revolutionize chip design by automating complex tasks, including architecture exploration, circuit optimization, and layout generation. Through case studies, we demonstrate significant improvements in design efficiency, performance optimization, and reduced time-to-market. Additionally, we address challenges such as data availability, model interpretability, and the integration of AI-generated designs into existing verification workflows. The findings highlight the potential of generative AI to enhance design capabilities, reduce development costs, and accelerate innovation in semiconductor technology.

Unraveling the Complexity of Parkinson's Disease: Insights into Pathogenesis and Precision Interventions.

Parkinson's disease (PD) is a neurodegenerative disorder characterized by dopaminergic neuron loss, leading to motor and non-motor symptoms. Early detection before symptom onset is crucial but challenging. This study presents a framework integrating circuit modeling, non-equilibrium dynamics, and optimization to understand PD pathogenesis and enable precision interventions. Neuronal firing patterns, particularly oscillatory activity, play a critical role in PD pathology. The basal ganglia network, specifically the subthalamic nucleus-external globus pallidus (STN-GPe) circuitry, exhibits abnormal activity associated with motor dysfunction. The framework leverages the non-equilibrium landscape and flux theory to identify key connections generating pathological activity, providing insights into disease progression and potential intervention points. The intricate STN-GPe interplay is highlighted, shedding light on compensatory mechanisms within this circuitry may initially counteract changes but later contribute to pathological alterations as disease progresses. The framework addresses the need for comprehensive evaluation methods to assess intervention outcomes. Cross-correlations between state variables provide superior early warning signals compared to traditional indicators relying on critical slowing down. By elucidating compensatory mechanisms and circuit dynamics, the framework contributes to improved management, early detection, risk assessment, and potential prevention/delay of PD development. This pioneering research paves the way for precision medicine in neurodegenerativedisorders.

Riemannian optimization of photonic quantum circuits in phase and Fock space

We propose a framework to design and optimize generic photonic quantum circuits composed of Gaussian objects (pure and mixed Gaussian states, Gaussian unitaries, Gaussian channels, Gaussian measurements) as well as non-Gaussian effects such as photon-number-resolving measurements. In this framework, we parametrize a phase space representation of Gaussian objects using elements of the symplectic group (or the unitary or orthogonal group in special cases), and then we transform it into the Fock representation using a single linear recurrence relation that computes the Fock amplitudes of any Gaussian object recursively. We also compute the gradient of the Fock amplitudes with respect to phase space parameters by differentiating through the recurrence relation. We can then use Riemannian optimization on the symplectic group to optimize MM-mode Gaussian objects, avoiding the need to commit to particular realizations in terms of fundamental gates. This allows us to “mod out” all the different gate-level implementations of the same circuit, which now can be chosen after the optimization has completed. This can be especially useful when looking to answer general questions, such as bounding the value of a property over a class of states or transformations, or when one would like to worry about hardware constraints separately from the circuit optimization step. Finally, we make our framework extendable to non-Gaussian objects that can be written as linear combinations of Gaussian ones, by explicitly computing the change in global phase when states undergo Gaussian transformations. We implemented all of these methods in the freely available open-source library MrMustard, which we use in three examples to optimize the 216-mode interferometer in Borealis, and 2- and 3-modes circuits (with Fock measurements) to produce cat states and cubic phase states.

An exponential variation based PSO for analog circuit sizing in constrained environment

This work presents an Exponential Variation based Particle Swarm Optimization (EV-PSO) algorithm to improve the convergence rate and find an optimal solution to analog circuit optimization problems in a constrained-driven environment. Existing evolutionary algorithms have a lower convergence rate leading to higher design time. This work introduces two novel parameters, ζ1 and ζ2, into the velocity update equation. These parameters dynamically vary with the number of iterations. The algorithm was implemented on the Python platform. The results have shown that, in comparison to the considered existing methods, the exponential variation of the parameters ζ1 and ζ2 in the proposed algorithms have a larger rate of convergence. The proposed EV-PSO has a convergence rate of 27 iterations, which is 57.8%, 65.38%, and 59.1% better than the conventional PSO, differential evolution (DE) and genetic algorithm (GA) respectively. The typical design obtained from the optimal solution is verified through the simulation using 45-nm CMOS technology. The optimal solution presented in this work meets the desired input specifications within the specified constrained environment.

Mathematical Approaches to Circuit Optimization in VLSI Design

Exceptionally Huge Scale Integration (VLSI) plan is continuously trying to find ways to improve circuit speed, lower control utilize, and make the finest utilize of space. A big portion of coming to these objectives is utilizing numerical strategies, which allow organized ways to form circuits work way better. This paper looks at a number of distinctive numerical methods and how they can be utilized in VLSI plan. It centers on how well these strategies can progress the value and productivity of circuits. Optimization calculations, like mimicked toughening, hereditary calculations, and molecule swarm optimization, are a prevalent way to see at math issues. Iteratively investigating plan regions is how these strategies discover combinations that grant superior execution measures, such as speed, control, and zone. Case considers appear that they are great at moving forward complicated circuits, appearing enormous picks up in plan parameters compared to old-fashioned heuristic strategies. Scientific modeling is additionally exceptionally imperative for accurately appearing how a circuit will work and anticipating execution measurements some time recently the genuine application. Direct programming and numbers programming are two strategies that offer assistance software engineers set limits and objectives, which leads to superior circuit structure and asset allotment. These models offer assistance individuals make choices by giving them numbers that appear the trade-offs between diverse plan objectives, like speed vs. power consumption or range minimization. Utilizing huge information sets and prescient analytics, machine learning procedures have moreover changed optimization strategies since they were included to VLSI plan.

Towards High Performance QNNs via Distribution-Based CNOT Gate Reduction

Quantum Neural Networks (QNNs) are one of the most promising applications that can be implemented on NISQ-era quantum computers. In this study, we observe that QNNs often suffer from gate redundancy, which hugely declines the performance and accuracy of the network. Even state-of-the-art architecture search techniques like QuantumNAS do not completely alleviate this problem. Especially, We find that CNOT gates are major contributors to the execution delay and noise in quantum circuits, and there are many redundant CNOT gates in the QNN post-training. This motivates us to propose a novel distribution-based greedy-search circuit optimization technique, that can be employed after the completion of the training process. Our technique significantly reduces the number of CNOT gates in QNNs without affecting the accuracy of the network. With this technique, we have achieved an average of 3 × improvement in execution time while reaching a maximum of 12.4 × improvement.