Circuit Netlist Research Articles

Using Platform FPGAs for Fault Emulation and Test-set Generation to Detect Stuck-at Faults

This paper investigates the use of reconfigurable computing and readily available Field Programmable Gate Array (FPGA) platforms to expedite the generation of input-patterns for testing integrated circuits after manufacture. Unlike traditional fault simulation approaches, our approach emulates single stuck-at fault behavior in a circuit and finds the minimum test pattern set to detect it. In this paper, we present a method to insert faults into a circuit netlist by identifying circuit fault sites. We then present our parallel method of fault emulation and describe our method to organize and compress the input patterns needed to identify all faults. Using circuits from the ISCAS and MCNC benchmark suites, we show that our approach does better than a commercial tool in test-set reduction.

Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist

A synthesis tool consisting of coefficient synthesis of architecture, circuit specifications synthesis, and CMOS operational-amplifier (op-amp) synthesis for discrete-time sigma-delta modulators (SDMs) is presented. In circuit specifications synthesis, several major circuit non-idealities are discussed and modeled. A precise performance prediction with a new design flow of specification synthesis is proposed. A hybrid design methodology composed of equation-based and simulation-based approaches for synthesizing fully differential two-stage and folded-cascode op-amps in 0.35μm technology is also presented. Experimental results show that the peak signal-to-noise and distortion ratio (PSNDR) of the fourth-order feed-forward (FF) SDM with an oversampling ratio (OSR) of 64 and a bandwidth of 20KHz estimated by the proposed synthesis tool is 94.19dB, and the result of the circuit simulation with folded-cascode op-amp is 93.03dB. The estimated PSNDR of the third-order multiple-feedback (MF) SDM with an OSR of 32 and a bandwidth of 256KHz is 59.52dB, and the HSPICE simulation result is 55.39dB.

Automated Physical Modeling of Nonlinear Audio Circuits For Real-Time Audio Effects—Part I: Theoretical Development

This paper presents a procedural approach to derive nonlinear filters from schematics of audio circuits for the purpose of digitally emulating analog musical effects circuits in real time. This work, the first in a two-part series, extends a well-known efficient nonlinear continuous-time state-space formulation for physical modeling of musical acoustics to real-time modeling of nonlinear circuits. Rules for applying the formulation are given, as well as a procedure to derive simulation parameters automatically from circuit netlists. Furthermore, a related nonlinear discrete-time state-space algorithm is proposed to alleviate problems in solving particular circuit configurations. These methods were devised to solve non-convergence problems in the simulation of strongly saturated, nonparametric guitar distortion circuits such as the saturating diode clipper, which is presented as an example derivation. Experimental considerations and sonic performance on various other circuits will be presented in a subsequent paper.

Genetic Algorithm Based Approach To Circuit Partitioning

In this paper multiway circuit partitioning of circuits using Genetic Algorithms has been attempted. Due to the random search, inherent parallelism, and robustness of genetic algorithms, the solution of a circuit partitioning problem is global optimum. Results obtained show the versatility of the proposed method in solving NP hard problems like circuit partitioning. Results obtained show an improvement over the results of UCLA Branch and Bound partitioner (27). Information of the circuit has been given in accordance with circuit netlist files used in ISPD'98 circuit benchmark suite.

Generating realistic stimuli for accurate power grid analysis

Power analysis tools are an integral component of any current power sign-off methodology. The performance of a design's power grid affects the timing and functionality of a circuit, directly impacting the overall performance. Ensuring power grid robustness implies taking into account, among others, static and dynamic effects of voltage drop, ground bounce, and electromigration. This type of verification is usually done by simulation, targeting a worst-case scenario where devices, switching almost simultaneously, could impose stern current demands on the power grid. While determination of the exact worst-case switching conditions from the grid perspective is usually not practical, the choice of simulation stimuli has a critical effect on the results of the analysis. Targetting safe but unrealistic settings could lead to pessimistic results and costly overdesigns in terms of die area. In this article we describe a software tool that generates a reasonable, realistic, set of stimuli for simulation. The approach proposed accounts for timing and spatial restrictions that arise from the circuit's netlist and placement and generates an approximation to the worst-case condition. The resulting stimuli indicate that only a fraction of the gates change in any given timing window, leading to a more robust verification methodology, especially in the dynamic case. Generating such stimuli is akin to performing a standard static timing analysis, so the tool fits well within conventional design frameworks. Furthermore, the tool can be used for hotspot detection in early design stages.

Comprehensive Electromagnetic Modeling of On-Chip Switching Noise Generation and Coupling

A comprehensive modeling methodology is presented for the investigation of on-chip noise generation and coupling due to power switching. The backbone of the methodology is an electromagnetic model for the on-chip portion of the power grid. This allows for the impact of the displacement current density and, hence, electromagnetic retardation, to be taken into account in the accurate modeling of the power grid behavior at picosecond switching speeds. In this manner, and through the interfacing of this model with an electromagnetic model for the package portion of the power grid, which is described in terms of a multiport rational matrix transfer function, the impact of package-chip electrical interactions on switching noise can be modeled with electromagnetic accuracy. The electromagnetic model for the power grid is complemented by a resistance-capacitance model for the semiconductor substrate, which is capable of modeling local substrate induced noise coupling between neighboring circuits. Finally, distributed resistance, inductance, capacitance and conductance circuits for signal wires are extracted and used to provide for a transmission line-based modeling of crosstalk and power grid induced signal degradation. Transient simulations using the proposed comprehensive model are carried out using a hybrid time-domain integration scheme which combines a SPICE-like engine for the analysis of all circuit netlists and the nonlinear drivers incorporated in the model with a numerical integration algorithm suitable for the expedient update of the state variables in the discrete electromagnetic model for the power grid.

Direct Mapping of Low-Latency Asynchronous Controllers From STGs

A method for an automated synthesis of low-latency asynchronous controllers is presented. It is based on a direct mapping approach and starts from an initial specification in the form of a signal transition graph (STG). This STG is split into a device and an environment, which synchronize via a communication net that models wires. The device is represented as a tracker and a bouncer. The tracker follows the state of the environment and provides reference points to the device outputs. The bouncer communicates with the environment and generates output events in response to the input events according to the state of the tracker. This two-level architecture provides an efficient interface to the environment and is convenient for subsequent mapping into a circuit netlist. A set of optimization heuristics is developed to reduce the latency and size of the circuit. As a result of this paper, a software tool called OptiMist has been developed. Its low algorithmic complexity allows large specifications to be synthesized, which is not possible for the tools based on state-space exploration. OptiMist successfully interfaces conventional EDA design flow for simulation, timing analysis, and place-and-route

Using Eigenvectors to Partition Circuits

Many fields, ranging from bioinformatics to databases to large-scale integrated circuits, deal with the interrelation between elementary objects. Objects are represented as vertices and the relationships between them are represented as nets (edges that connect two or more vertices) in the form of a hypergraph. We seek a placement of vertices that groups like objects and separates unlike objects. This involves separating related objects into a few, possibly disjoint, blocks. These hypergraph-partitioning problems are NP-hard so cannot be solved exactly, except for very small instances. We develop and use a numerical technique based on eigenvector decomposition of the connectivity matrix associated with the circuit netlist to partition hypergraphs emanating from circuit netlists. The eigenvector components of the circuit connectivity matrix are then used to determine vertex coordinates in one dimension that are then rounded in some fashion to determine block assignments. The inherent difficulty with eigenvector techniques is that the eigenvector components tend to cluster, making it difficult to determine correct block assignments. Our technique uses weights on nets, vertices, and fixed vertices to obtain a more “discrete” placement of vertices, making it easier to determine correct block assignments.

Optimization Methodology of Layer Numbers with Circuit/Process Co-Design

The number of layers directly affects manufacturing cost, and it also has a trade-off with the circuit area in multilevel interconnection LSI. In this paper, we propose a co-design methodology for circuits and processes to optimize the number of interconnect layers. In the proposed methodology, the number of interconnect layers can be optimized in consideration of circuit area. Wire length distribution (WLD) is used to derive the optimized number of layers from a circuit netlist. Operating frequency and power consumption are estimated as functions of circuit area in the 180 nm process-technology node. From the analyzed results, it has been shown that circuit area has an optimum value to improve both operating frequency and power consumption.

FROSTY: A program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits

This paper presents FROSTY, a computer program for automatically extracting the high-level structural representation of a large-scale digital CMOS circuit from its transistor-level netlist and a library of subcircuit descriptions. To handle the complexity and diversity of industrial circuits, FROSTY combines traditional structural recognition and pattern matching methods into a two-step extraction process. First, logic structures based on channel-connected-components are recognized from a circuit netlist and from all library subcircuits, and are condensed into “macro devices” or called logic gates. This leads to hybrid netlists that contain the recognized logic gates and remaining transistors. Then annotated graphs representing the connectivity and properties of logic gates and remaining transistors are constructed. Compared to transistor-level netlists, these hybrid graphs are much smaller in size, more distinguishable in structure, and are thus more suitable for labeling-based pattern matching. An efficient pattern matching algorithm is then applied to extract the high-level structural representation from these condensed circuit graphs. FROSTY has demonstrated to be orders of magnitude faster than the pattern matching-based extraction program SubGemini, and can extract entire industrial designs with several hundreds of thousands of transistors in a few minutes on a modern Sun workstation. Furthermore, the FROSTY algorithm scales well with the size of a circuit.

Rewiring for watermarking digital circuit netlists

A resynthesis method to protect firm cores or circuit netlist representations is presented. The design is protected by embedding watermark by rewiring circuit with one or more redundancy addition/removal steps. This is the first known attempt to explore rewiring for watermarking. Area, performance, and testability requirements are preserved by the approach. We analyze several attack strategies and we experimentally demonstrate that the proof of authorship is guaranteed with very high probability for all ISCAS'85 benchmarks.

Linear Decision Diagram Based Mapping for Rapid Prototyping

The paper focuses on the methodology of generating a high-level circuit description, Linear Decision Diagrams (LDDs), from a popular Electronic Design Interchange Format (EDIF), and mapping this LDD-based description, onto a circuit netlist associated with rapid prototyping, Xilinx Netlist Format (XNF). A synthesis step that produces an XNF enables further technology mapping using Xilinx tools. The results of an experimental study on design of LDD models and transformation to/from EDIF and to XNF are reported here.

HDL Constructs in Linear Word-Level Decision Diagram Based Specification

Linear Decision Diagrams (LDDs) are used in the paper as an intermediate format that allows us to quickly generate the circuit netlist from HDL (hardware description language), such as Verilog, or transform it to HDL description for further ASIC or FPGA synthesis and verification. The results of an extensive experimental study (on memory requirements, run time to convert LDD intermediate format to/from HDL, and verification via simulation) are reported here.

Layout driven retiming using the coupled edge timing model

Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear whether the predicted performance improvement is still valid after placement has been performed. This paper presents a new retiming algorithm using a highly accurate timing model. It takes into account the effect of retiming on capacitive loads of single wires as well as fanout systems. Further, we propose the integration of retiming into a timing-driven standard cell placement environment. Retiming is used as an optimization technique throughout the whole placement process. The experimental results show the benefit of the proposed approach. In comparison with the conventional design flow based on the standard FEAS algorithm, our approach achieved an improvement in cycle time of up to 34% and 17% on the average.

INVAR – A Benchmark Generation Tool

This article introduces a new method for generating benchmark circuits. Common methods of testing physical design algorithms used today rely on standardised sets of widely accepted benchmark circuits, or on generating a random benchmark circuit based on its desired characteristics. Although these approaches are suitable in many situations, sometimes it is advantageous to know an exact function of a benchmark circuit. This article introduces a new method for generating benchmarks that is based on structural modifications of a user-specified design without altering its function. The method uses a set of pre-defined operations on a circuit netlist. The method is demonstrated on several commented examples.

Automatic generation of synthetic sequential benchmark circuits

The design of programmable logic architectures and supporting computer-aided design tools fundamentally requires both a good understanding of the combinatorial nature of netlist graphs and sufficient quantities of realistic examples to evaluate or benchmark the results. In this paper, the authors investigate these two issues. They introduce an abstract model for describing sequential circuits and a collection of statistical parameters for better understanding the nature of circuits. Based upon this model they introduce and formally define the signature of a circuit netlist and the signature equivalence of netlists. They give an algorithm (GEN) for generating sequential benchmark netlists, significantly expanding previous work (Hutton et al, 1998) which generated purely combinational circuits. By comparing synthetic circuits to existing benchmarks and random graphs they show that GEN circuits are significantly more realistic than random graphs. The authors further illustrate the viabilty of the methodology by applying GEN to a case study comparing two partitioning algorithms.

A Discussion on Test Pattern Generation for FPGA—Implemented Circuits

The objective of this paper is to generate a Application-Oriented Test Procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of ‘AC-non-redundant fault.’ Using a set of circuits implemented on a XILINX 4000E, it is shown that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required. It is then demonstrated that test pattern generation performed on the FPGA representation can be significantly accelerated by removing most of the AC-redundant faults. Finally, a technique is proposed to even more accelerate the test pattern generation process by using a reduced FPGA description.

Techniques for the creation of digital watermarks in sequential circuit designs

We present a methodology for the watermarking of synchronous sequential circuits that makes it possible to identify the authorship of designs by imposing a digital watermark on the state transition graph (STG) of the circuit. The methodology is applicable to sequential designs that are made available as firm intellectual property, the designation commonly used to characterize designs specified as structural hardware description languages or circuit netlists. The watermarking is obtained by manipulating the STG of the design in such a way as to make it exhibit a chosen property that is extremely rare in nonwatermarked circuits while, at the same time, not changing the functionality of the circuit. This manipulation is performed without ever actually computing this graph in either implicit or explicit form. Instead, the digital watermark is obtained by direct manipulation of the circuit description. We present evidence that no known algorithms for circuit manipulation can be used to efficiently remove or change the watermark and that the process is immune to a variety of other attacks. We present both theoretical and experimental results that show that the watermarking can be created and verified efficiently. We also test possible attack strategies and verify that they are inapplicable to realistic designs of medium to large complexity.

A fast hypergraph min-cut algorithm for circuit partitioning

Circuit partitioning is one of the central problems in VLSI system design. The primary objective of circuit partitioning is to minimize the number of interconnections between different components of the partitioned circuit. So the circuit partitioning problem is closely related to the minimum cut problem. Recently, two very fast algorithms for computing minimum cuts in graphs were reported (Nagamochi and Ibaraki; SIAM J. Discrete Math. 5 (1) (1992) 54; Stoer and Wagner, J. ACM 44 (4) (1997) 585). However, it is known that a circuit netlist cannot be accurately modeled by a graph, but only by a hypergraph. In this paper, we present the fastest algorithm known today for computing a minimum cut in a hypergraph which is a non-trivial extension of the result in Stoer and Wagner (J. ACM 44 (4) (1997) 586). Since the netlist of a circuit can be modeled naturally as a hypergraph, this opens the opportunity for finding very-high-quality solutions for the circuit partitioning problem. Unlike most minimum cut algorithms which rely on flow computations in a network, ours is a non-flow-based algorithm.

Probability-based approaches to VLSI circuit partitioning

Iterative-improvement two-way min-cut partitioning is an important phase in most circuit placement tools, and finds use in many other computer-aided design (CAD) applications. Most iterative improvement techniques for circuit netlists like the Fiduccia-Mattheyses (FM) method compute the gains of nodes using local netlist information that is only concerned with the immediate improvement in the cutset. This can lead to misleading gain information. Krishnamurthy suggested a lookahead (LA) gain calculation method to ameliorate this situation; however, as we show, it leaves room for improvement. We present here a probabilistic gain computation approach called probabilistic partitioner (PROP) that is capable of capturing the future implications of moving a node at the current time. We also propose an extended algorithm SHRINK-PROP that increases the probability of removing recently "perturbed" nets (nets whose nodes have been moved for the first time) from the cutset. Experimental results on medium- to large-size ACM/SIGDA benchmark circuits show that PROP and SHRINK-PROP outperform previous iterative-improvement methods like FM (by about 30% and 37%, respectively) and LA (by about 27% and 34%, respectively). Both PROP and SHRINK-PROP also obtain much better cutsizes than many recent state-of-the-art partitioners like EIG1, WINDOW, MELO, PARABOLI, GFM and GMetis (by 4.5% to 67%), Our empirical timing results reveal that PROP is appreciably faster than most recent techniques. We also obtain results on the more recent ISPD-98 benchmark suite that show similar substantial mincut improvements by PROP and SHRINK-PROP over FM (24% and 31%, respectively). It is also noteworthy that SHRINK-PROP'S results are within 2.5% of those obtained by hMetis, one of the best multilevel partitioners. However, the multilevel paradigm is orthogonal to SHRINK-PROP. Further, since it is a "flat" partitioner, it has advantages over hMetis in partition-driven placement applications.