Circuit Manufacturing Technology Research Articles

Flex-to-Rigid (F2R): A Generic Platform for the Fabrication and Assembly of Flexible Sensors for Minimally Invasive Instruments

The flex-to-rigid (F2R) platform allows for the fabrication of miniature and flexible sensor assemblies for minimally invasive medical instruments such as catheters and guidewires. Devices fabricated on silicon wafers are transferred onto polyimide and partially rendered flexible by means of a two-step backside silicon deep reactive ion etching. The flexibility allows for the devices to be folded into, or wrapped around the tip of the instruments. The fabrication of the whole assembly is based on standard integrated circuit manufacturing technologies so that it is possible to scale the devices down to the dimension of the smallest guidewires. Several demonstrations are presented to show the versatility of the F2R technology, and a polyimide-based flexible thermal flow sensor for application at the tip of a 360- μm diameter guidewire is introduced.

P3T – a new technology for the cost and resource efficient inline production of flexible printed circuits, RFID antennas and biosensors

PurposeThe purpose of this paper is to present details of the plasma printing and packaging technology (P3T), a new reel‐to‐reel technology under development for the cost and resource efficient manufacture of flexible printed circuits (FPC).Design/methodology/approachThe first two process steps of P3T include reel‐to‐reel patterned activation of polymer film at ambient pressure in the so‐called plasma‐printing process and subsequent selective electroless plating of the plasma‐activated areas of the polymer film. The concept underlying the P3T project includes processing of flexible films with widths up to 400 mm.FindingsCopper, palladium and nickel metal structures with widths down to less than 100 μm were produced on various polymers. Peel strengths according to the German DIN Standard 53494 of copper on polyimide film reached values in the region of 1 N/mm, sufficient for electronic applications. Sufficient wetting of the solder on copper metallisations and solderability were found.Research limitations/implicationsP3T covers the whole manufacturing chain for FPCs from surface patterning of the dielectric carrier to component assembly and soldering. This paper focuses, however, essentially on the first two process steps including plasma activation and electroless plating.Originality/valueA unique feature of the flexible circuit manufacturing technology presented here is the combination of the additive‐technique, the absence of vacuum processes, the continuous production mode and the ability to process polymer carrier films with widths of 400 mm.

Built-In Self-Repair Schemes for Flash Memories

The advancement of deep submicrometer Integrated circuit manufacturing technology has pushed the use of embedded memory, and the strong demand of embedded nonvolatile memory for system-on-chip and system in package applications has made flash memory increasingly important as well. Nevertheless, the yield loss of memory products caused by deep submicrometer defects and manufacturing uncertainties is still a critical issue. In order to solve the yield issue, built-in self-repair (BISR) has been considered as the most cost-effective solution. However, implementing BISR on flash memories is not trivial. In this paper, we propose BISR schemes for nor flash memory and NAND flash memory, respectively. The BISR schemes perform built-in self-test, built-in redundancy analysis, and on-chip repair. For the BISR scheme of nor flash memory, a typical redundancy architecture is assumed, based on which we analyze three existing algorithms and propose a redundancy analysis (RA) algorithm. On the other hand, for NAND flash memory, an RA algorithm based on an efficient 2-D redundancy architecture is proposed, and considering the widely used page-mode operation in NAND flash memory, a method to discover currently accessed address is also proposed. A simulation tool is also developed, supporting nor flash memory and NAND flash memory. The simulation results show that our approach can effectively repair defective memories.

Modelling the effectiveness of computer-aided development projects in the semiconductor industry

This paper presents a complete quantitative model to estimate the potential benefits of simulation-based projects over the conventional approach. In the semiconductor industry, technology computer-aided design has shown a great potential for rapid and cost-effective development of advanced integrated circuit manufacturing technologies. However, a complete quantitative model to estimate the efficiency and effectiveness of simulation-based projects has not yet been developed. This paper describes a simplified mathematical model to estimate the reduction in development cycle time and cost by computer applications in technology development to reduce the number of expensive and time-consuming experiments in the wafer fabrication facility. This model, clearly, demonstrates a reduction in technology development cycle time over 67% and multi-million dollar cost savings by computer-aided technology development in contrast to the conventional trial-and-error-experimentation. Thus, the proposed model offers project managers a valuable tool to quantitatively assess the time and cost advantage of computer-aided advanced technology development projects.

Development and application prospects of piezoelectric precision driving technology

With the rapid development of science and technology, microelectronics manufacturing, photonics technology, space technology, ultra-precision machining, micro-robotics, biomedical engineering and other fields urgently need the support of modern precision driving theory and technology. Modern precision driving technology can be generally divided into two parts: electromagnetic and non-electromagnetic driving technology. Electromagnetic driving technology is based on traditional technology, has a low thrust-weight ratio, and needs deceleration devices with a cumbrous system or a complex structure. Moreover, it is difficult to improve positioning accuracy with this technology type. Thus, electromagnetic driving technology is still unable to meet the requirements for the above applications. Non-electromagnetic driving technology is a new choice. As a category of non-electromagnetic driving technology, piezoelectric driving technology becomes an important branch of modern precision driving technology. High holding torque and acute response make it suitable as an accurate positioning actuator. This paper presents the development of piezoelectric precision driving technology at home and abroad and gives an in-depth analysis. Future perspectives on the technology’s applications in the following fields are described: 1) integrated circuit manufacturing technology; 2) fiber optic component manufacturing technology; 3) micro parts manipulation and assembly technology; 4) biomedical engineering; 5) aerospace technology; and 6) ultra-precision processing technology.

Low-cost Distributed Embedded Control Systems

This paper presents how a complex distributed control system can be inexpensively achieved using low-cost controllers. These controllers will be interconnected in a network with an open communication bus called CAN. The development of integrated circuit manufacturing technology has increased the power and performance of the microprocessors and microcontrollers as opposed to its price, and if they also have communication capabilities, they can be used to implement low-cost distributed control nodes.Nodes with different computer architectures (from 16 to 32 bits processors) could be combined as long as the complexity of a given application. This approach was tested in a simulated process, using a dsPICTM (Microchip, 2006) microcontroller control implementation, supervised by an XScale microcomputer with a GPL (General Public License) real-time operating system as RTLinux.

Horizontal buried channels in monocrystalline silicon

This paper reports horizontal buried channels in monocristalline silicon. Those channels are a few microns in width and height and several hundred microns long. The main applications for those buried channels are microfluidic networks for MEMS devices and cooling systems for integrated circuits. Their fabrication is based on integrated circuit standard processes such as selective monocristalline epitaxial growth and high temperature annealing. The major interest of the method is its compatibility with integrated circuit manufacturing technology.

Biographies

Gordon Earle Moore, a chemist with a PhD from the California Institute of Technology, was a key figure in the development of the semiconductor industry and silicon integrated circuit technology. Moore co-founded Fairchild Semiconductor, and, subsequently, the Intel Corporation. In 1965, Moore published an observation about the exponential pace of development in integrated circuit manufacturing technology that has come to be known as "Moore's law." Moore's contributions to semiconductor devices and the semiconductor industry have had a major impact on the development of Silicon Valley as a high-technology district.

Design of a tunable frequency CMOS fully differential fourth-order Chebyshev filter

A new fully differential amplifier and a fully differential R-MOSFET-C fourth-order Chebyshev active lowpass filter employing passive resistors and current-steering MOS transistors as variable resistors are proposed. The implementation relies on the tunability of current-steering MOS transistors operating in the triode region which counteract the deviation of resistors in integrated circuit manufacturing technology in order that the cutoff frequency of Chebyshev active filter can be realized accurately tunable. The amplifier is not only with voltage common-mode negative feedback (VCMFB), but also with current common-mode negative feedback (CCMFB), which will benefit for the stability of its DC operating point. A cutoff frequency of 138kHz fourth-order Chebyshev lowpass filter was designed and fabricated using 3.3V power supply and 0.35μm CMOS technology. Chip test results demonstrate better than −68dB THD with 70kHz, 2.0Vpp signal, frequency turning range of more than 14,000 from 3Hz to 420kHz, chip area of 0.36mm2 and power consumption of 16mW.

Simultaneous power supply planning and noise avoidance in floorplan design

With today's advanced integrated circuit manufacturing technology in deep submicron (DSM) environment, we can integrate entire electronic systems on a single system on a chip. However, without careful power supply planning in layout, the design of chips will suffer from local hot spots, insufficient power supply, and signal integrity problems. Postfloorplanning or postroute methodologies in solving power delivery and signal integrity problems have been applied but they will cause a long turnaround time, which adds costly delays to time-to-market. In this paper, we study the problem of simultaneous power supply planning and noise avoidance as early as in the floorplanning stage. We show that the problem of simultaneous power supply planning and noise avoidance can be formulated as a constrained maximum flow problem and present an efficient yet effective heuristic to handle the problem. Experimental results are encouraging. With a slight increase of total wirelength, we achieve almost no static IR (voltage)-drop requirement violation in meeting the current and power demand requirement imposed by the circuit blocks compared with a traditional floorplanner and 45.7% of improvement on a /spl Delta/I noise constraint violation compared with the approach that only considers power supply planning.

A Low Distortion Wide Tuning Range CMOS Fully-Differential Fourth-Order Bessel Filter

A fully differential R-MOSFET-C fourth-order Bessel active low-pass filter employing passive resistors and current-steering MOS transistors as a variable resistor is proposed. The implementation relies on the tunability of the current-steering MOS transistors operating in the triode region which counteract the deviation of resistors in integrated circuit manufacturing technology in order that the group delay of the Bessel active filter can be realized accurately. A 0.75 us group delay 520 kHz frequency fourth-order Bessel lowpass filter based on a passive doubly terminated RLC prototype was designed and fabricated using 3.3 V power supply and 0.35 um CMOS technology. Chip test results demonstrate better than −65 dB THD with @100 kHz, 1.65-Vpp signal, frequency tuning range of more than ten decades from 0.6 kHz to 550 kHz, chip area of 0.32 mm2 and power consumption of 13.3 mW.

Copper electroplating technology for microvia filling

This paper describes a copper electroplating enabling technology for filling microvias. Driven by the need for faster, smaller and higher performance communication and electronic devices, sequential build up (SBU) technology has been adopted as a viable multilayer printed circuit manufacturing technology. Increased wiring density, reduced line widths, smaller through‐holes and microvias are all attributes of these high density interconnect (HDI) packages. Filling the microvias with conductive material allows the use of stacked vias and via in pad designs. Other potential design attributes include thermal management enhancement and benefits for high frequency circuitry. Electrodeposited copper can be utilized for filling microvias and provides potential advantages over alternative via plugging techniques. The features, development, scale up and results of direct current (DC) and periodic pulse reverse (PPR) acid copper via filling processes, including chemistry and equipment, are described.

A high-performance glucose biosensor based on monomolecular layer of glucose oxidase covalently immobilised on indium–tin oxide surface

In this paper, a mediatorless amperometric glucose biosensor based on direct covalent immobilisation of monomolecular layer of glucose oxidase (GOx) on a semiconducting indium–tin oxide (ITO) is demonstrated. The abundance of surface hydroxyl functional group of ITO allows it to be used as a suitable platform for direct covalent immobilisation of the enzyme for sensor architecture. The anodic current corresponding to electrochemical oxidation of the enzymatic product, hydrogen peroxide, at a sputtered Pt electrode at 0.500 V (vs. SCE) was obtained as the sensor signal. It was found that the biosensor based on the direct immobilisation scheme shows a fast biosensor response, minimum interference from other common metabolic species and ease of biosensor miniaturisation. A linear range of 0–10 mM of glucose was demonstrated, which exhibits a high sensitivity as far as performance per immobilised GOx molecule is concerned. A detection limit as low as 0.05 mM and long-term stability were observed. Even more important, the biosensor design allows fabrication through a dry process. These characteristics make it possible to achieve mass production of biosensor compatible with the current electronic integrated circuit manufacturing technologies.

A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver

As integrated circuit (IC) manufacturing technology pushes toward the deep submicron (DSM) regime, the interconnect behavior begins to dominate the overall chip performance. Traditional interconnect characterization methods do not offer the required accuracy or the versatility to tackle challenges of DSM design. We present a system for interconnect parasitic capacitance extraction using an extremely fast three-dimensional (3-D) solver, capable of handling general geometry configurations and providing high accuracy. The contributions in this work make 3-D field solvers an attractive and, for the first time, computationally feasible approach to calculating interconnect parasitics. The system represents a significant performance leap in 3-D interconnect characterization, making it well suited for full-chip extraction and for high-accuracy characterization of critical nets, block IP, and standard and custom cell designs.

Fine line circuit manufacturing technology with electroless copper plating : HARUO AKAHOSHIE et al., IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part A, 18(1), 127 (March 1995)

Fine line circuit manufacturing technology with electroless copper plating : HARUO AKAHOSHIE et al., IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part A, 18(1), 127 (March 1995)

Integrating Bipolar Junction Transistors with Silicon-Based Light-Emitting Devices

AbstractSilicon-based optoelectronic devices enable the realization of optoelectronic systems that are compatible with integrated circuit manufacturing technology. This work reports on silicon-based visible light-emitting devices (LEDs) that have been successfully integrated into a standard bipolar fabrication sequence. The basic LED structure consists of a 0.5–1.0μm thick silicon-rich silicon oxide (SRSO) active light-emitting layer formed on a p-type silicon wafer by partial oxidation of porous silicon (PSi), with an n+ doped polysilicon cathode. The LEDs exhibit bright electroluminescence (EL) with a spectral peak between 1.75 and 1.90e. The LEDs are connected in a common-emitter configuration to integrated vertical pnp bipolar driver transistors. This is the first demonstration of an all-silicon visible light emitter / bipolar transistor optoelectronic integrated circuit. The LED device fabrication, process integration, and optoelectronic device characteristics are discussed.

Fine line circuit manufacturing technology with electroless copper plating

Fine line circuit manufacturing technology with electroless copper plating

The economics of flexible integrated circuit manufacturing technology

An economic frameword for evaluting flexible integrated circuit manufacturing technologies is developed as an alternative to the capacity races that appear to have played a major role in the decline of the U.S. IC industry. Economic advantages of flexible IC manufacturing technologies (such as cluster tools and multiprocessors) may include reductions in units costs at low output volumes, inexpensive increases in the diversity of IC products manufactured, and acceleration of the speed of new product introduction. The consequences of these developments for semiconductor equipment producers, IC manufacturers, and electronic system producers are examined.

100 nm wide copper lines made by selective electroless deposition

Copper lines with a minimum width of 100 nm were fabricated by selective electroless copper deposition (SED). The deposition reaction is based on the neutralization of positive copper ions in a basic solution by electrons which are the result of the reaction between formaldehyde and the hydroxyl ions. The reduction reaction requires a high pH typically in the range of 11.5-13 at the deposition temperature which is between 55 degrees C and 70 degrees C. The high pH required for the deposition reaction is achieved either by using alkaline bases, like sodium-hydroxide, or alkaline-free bases, like tetramethylammonium hydroxide (TMAH). Experimental data show similar results for both alkaline and alkaline-free deposition solutions. The copper nanolines were produced using electron beam lithography and polymethylmethacrylate (PMMA) e-beam resist due to its compatibility with the high pH of the deposition solution. The first approach, which is described here for making copper nanolines, produced 100 nm wide lines with vertical side walls and aspect ratio (height/width) as high as 4:1. The lines were uniform over both small and large areas and the deposition was only on the pre-designated regions (i.e. full selectivity). A second fabrication technique, which is also described, formed a fully-planar topography in which the copper is buried in an interlevel dielectric. 150 nm wide copper lines buried in 250 nm deep trenches in chemically-vapor-deposited (CVD) silicon-dioxide were made using that technique. Both techniques are described in detail and experimental results are presented in the form of SEM pictures. Selective copper deposition introduces some new problems in general and there are also some particular problems that are associated with the techniques described. Specific problems, such as step coverage and copper line shapes are discussed as well as more general problems like the compatibility with integrated circuit manufacturing technology.

GARDEN—An integrated and evolving environment for ULSI/VLSI CAD applications

The design and specification of efficient and powerful Ultra Large Scale Integration/ Very Large Scale Integration (ULSI/VLSI) computer-aided design (CAD) systems to deal with the current integrated circuit manufacturing technology is beyond the capabilities of the usual software development methodologies. This paper presents GARDEN, an integrated ULSI/VLSI design environment conceived to cope with problems in the evolution of the computing environment. It also highlights the utilization of the Vienna Development Methodology (VDM) for the specification, design, implementation, and maintenance—in short, all of the software life cycle—of this CAD system, under development at the IBM Brazil Rio Scientific Center.