Circuit Level Research Articles

Extendable Bidirectional DC–DC Converter With Improved Voltage Transfer Ratio and Reduced Switch Count

Bidirectional dc-dc converter (BDC) plays an important role in battery-based applications. This paper presents an extendable BDC using 8+5 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> components, including 3+ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> MOSFETs, where <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> is the number of stages. The detailed analysis of single-stage of the proposed converter is discussed. The voltage transfer ratio (VTR) of the converter during the step-up and step-down modes is derived. The effect of parasitic elements on the VTR and the efficiency is discussed. The state-space model is derived, and the open-loop transfer functions, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\widehat{\boldsymbol{v}}_{\boldsymbol H}/\widehat{\boldsymbol d}_{\boldsymbol H}$</tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\widehat{\boldsymbol{v}}_{\boldsymbol L}/\widehat{\boldsymbol d}_{\boldsymbol L}$</tex-math></inline-formula> for both the modes are obtained. These transfer functions are validated using circuit level simulation. The operating modes of the converter are validated using a 300 W, 650 V, and 50 kHz prototype, and the experimental results are presented. Using the derived transfer functions, the PI controllers are designed using Ziegler–Nichols method for step-up and step-down modes. Using the Xilinx system generator (XSG), the designed controllers are implemented, and the experimental closed-loop results are presented. The performance comparison shows that the VTR of the single-stage converter using four MOSFETs is significantly improved compared to the other converters which achieve the quadratic VTR. Each extended stage requires a single MOSFET along with 4 passive components.

Large-scale analysis of structural brain asymmetries in schizophrenia via the ENIGMA consortium

Left-right asymmetry is an important organizing feature of the healthy brain that may be altered in schizophrenia, but most studies have used relatively small samples and heterogeneous approaches, resulting in equivocal findings. We carried out the largest case-control study of structural brain asymmetries in schizophrenia, with MRI data from 5,080 affected individuals and 6,015 controls across 46 datasets, using a single image analysis protocol. Asymmetry indexes were calculated for global and regional cortical thickness, surface area, and subcortical volume measures. Differences of asymmetry were calculated between affected individuals and controls per dataset, and effect sizes were meta-analyzed across datasets. Small average case-control differences were observed for thickness asymmetries of the rostral anterior cingulate and the middle temporal gyrus, both driven by thinner left-hemispheric cortices in schizophrenia. Analyses of these asymmetries with respect to the use of antipsychotic medication and other clinical variables did not show any significant associations. Assessment of age- and sex-specific effects revealed a stronger average leftward asymmetry of pallidum volume between older cases and controls. Case-control differences in a multivariate context were assessed in a subset of the data (N = 2,029), which revealed that 7% of the variance across all structural asymmetries was explained by case-control status. Subtle case-control differences of brain macrostructural asymmetry may reflect differences at the molecular, cytoarchitectonic, or circuit levels that have functional relevance for the disorder. Reduced left middle temporal cortical thickness is consistent with altered left-hemisphere language network organization in schizophrenia.

Post algebras and ternary adders

Except for qubits for which the different possible values are unordered, the different values of m-valued circuits either with voltage levels, current levels or charge levels are totally ordered. Either at the Math level (Post algebras) or at the circuit level, it means that each multiple valued level must be decomposed into binary levels, processed with binary computation and finally converted into a multiple valued level. Using ternary adders as example, we show that the ternary-to-binary decoding and binary encoding should be applied to the whole adder or to restricted parts of the adder. The second approach using multiplexers leads to the most efficient ternary adders. However, a comparison with binary adders shows that the ternary-to-binary and binary-to-ternary conversions is the reason for which the binary adders are more efficient.

Dynamic grid stability in low carbon power systems with minimum inertia

The power system transition to large penetrations of renewable generation has become a core target of decarbonisation roadmaps in many countries. However, switching from synchronous to variable inverter-based resources has prompted technical concerns linked to the reduction in system inertia and short circuit levels. This may result in significant deviations in frequency and bus voltages during fault events. Hence, this paper provides a comprehensive review of power system stability challenges when integrating up to 100% inverter-based resources. The potential solutions from several enabling technologies (i.e., energy storage, controllable loads, wind, solar PV, etc.) are also assessed to mitigate anticipated issues. The review further details the role of grid codes and international standards in maintaining dynamic stability in power systems with extremely high up to 100% variable renewable generation. Finally, discussion and recommendation pathways are provided to inform industries and accelerate a secure power system transition to meet Net Zero targets.

Analysis of Performance Improvement of Passenger Car Synchronous Homopolar Generator with the Addition of Ferrite Magnets

Electric machines with hybrid excitation have increased torque density while maintaining a wide range of speed control. This article presents the results of the optimal design of a synchronous homopolar generator (SHG) with ferrite magnets on the rotor and excitation winding on the stator for passenger cars. The use of ferrite magnets on the rotor of a synchronous homopolar generator makes it possible to use the stator surface more efficiently, which in turn increases energy efficiency and reduces the dimensions of the generator. At the same time, the excitation winding on the stator provides a reliable brushless design and the ability to control the excitation flux. The problem of long-time calculation of the three-dimensional SHG structure, which is especially relevant when using multi-iterative computer optimization, is solved by using the computationally efficient Nelder-Mead method and a simplified SHG model using two-dimensional finite element analysis. It is also clear that the low torque ripple of SHG with ferrite magnets with two stator-rotor stack combinations (SRSC) is largely provided by the fact that the torque ripples of individual SRSCs are in antiphase. The problem of considering the magnetic properties of magnetic core sections made of structural low-carbon steel is discussed. It has been found that with an increase in both the saturation level of the magnetic circuit and the magnetomotive force (MMF) of the SHG excitation winding, resistance to irreversible demagnetization of ferrite magnets on the rotor can be increased by increasing their height. In addition, it is shown that there is a significant increase in performance when using the hybrid excitation, in comparison with the conventional SHG design without magnets.

Analysis of DC/DC Boost Converter–Full-Bridge Buck Inverter System for AC Generation

This paper presents an analysis and simulation of the mathematical model associated to the DC/DC Boost converter–full-bridge Buck inverter system to regulate the voltage output of the DC/DC Boost converter allowing bipolar voltages higher than the input voltage via the full-bridge Buck inverter. To validate the model, the differential flatness property is applied via the flat outputs of the system (energy for the DC/DC Boost converter and the voltage of the full-bridge Buck inverter) considering the complete dynamics, in conjunction with fixed and time-variant trajectory planning. In the simulation results, it is observed that the error signals of the states versus the reference trajectories are acceptable. Regarding the validation of the model, this is performed with open-loop simulations at the circuit level using the SimPowerSystems Toolbox of Matlab-Simulink. The simulation results validate the good performance of the system under study. In this way, the main contribution of this work is that for the first time in the literature, the analysis of a complete dynamics for a conversion system from DC to AC without the use of a transformer and taking advantage of differential flatness is reported; thus, the system analyzed could be represented as an alternative in applications of renewable energies that require conversion from DC to AC.

Compulsive-like Behaviors in Amyloid-β 1-42–Induced Alzheimer’s Disease in Mice Are Associated With Hippocampo-cortical Neural Circuit Dysfunction

BackgroundIn addition to memory deficits, patients with Alzheimer’s disease (AD) experience neuropsychiatric disturbances. Recent studies have suggested the association of obsessive-compulsive disorder with the early stages of AD. However, there is a lack of understanding of the neurobiological underpinnings of compulsive-like behaviors at the neuronal circuit level and their relationship with AD. MethodsWe have addressed this issue in an amyloid-β 1-42–induced mouse model of AD by studying compulsive-like behaviors. Next, we compared the hippocampal and medial prefrontal cortex (mPFC) local field potential pattern and coherence between these regions of control and AD mice. We also assessed the expression pattern of acetylcholine and glutamatergic signaling in these regions, using quantitative polymerase chain reaction. ResultsOur findings show that AD mice exhibit compulsive-like behaviors, as evidenced by enhanced marble burying, nest building, and burrowing. Furthermore, AD mice exhibited hippocampo-cortical circuit dysfunction demonstrated by decreased power of rhythmic oscillations at the theta (4–12 Hz) and gamma (25–50 Hz) frequencies in the hippocampus and mPFC, two functionally interconnected brain regions involved both in AD and compulsive behaviors. Importantly, coherence between the hippocampus and mPFC in the theta band of AD animals was significantly reduced. Furthermore, we found reduced cholinergic and glutamatergic neurotransmission in the hippocampus and mPFC of AD mice. ConclusionsWe conclude that the hippocampo-cortical functional alterations may play a significant role in mediating the compulsive-like behaviors observed in AD mice. These findings may help in understanding the underlying circuit mechanisms of obsessive-compulsive disorder–like phenotypes associated with AD.

Combined HW/SW Drift and Variability Mitigation for PCM-Based Analog In-Memory Computing for Neural Network Applications

Matrix-Vector Multiplications (MVMs) represent a heavy workload for both training and inference in Deep Neural Networks (DNNs) applications. Analog In-memory Computing (AIMC) systems based on Phase Change Memory (PCM) has been shown to be a valid competitor to enhance the energy efficiency of DNN accelerators. Although DNNs are quite resilient to computation inaccuracies, PCM non-idealities could strongly affect MVM operations precision, and thus the accuracy of DNNs. In this paper, a combined hardware and software solution to mitigate the impact of PCM non-idealities is presented. The drift of PCM cells conductance is compensated at the circuit level through the introduction of a conductance ratio at the core of the MVM computation. A model of the behaviour of PCM cells is employed to develop a device-aware training for DNNs and the accuracy is estimated in a CIFAR-10 classification task. This work is supported by a PCM-based AIMC prototype, designed in a 90-nm STMicroelectronics technology, and conceived to perform Multiply-and-Accumulate (MAC) computations, which are the kernel of MVMs. Results show that the MAC computation accuracy is around 95% even under the effect of cells drift. The use of a device-aware DNN training makes the networks less sensitive to weight variability, with a 15% increase in classification accuracy over a conventionally-trained Lenet-5 DNN, and a 36% gain when drift compensation is applied.

Impact of Scaling on Nanosheet FET and CMOS Circuit Applications

In this paper, the impact of scaling on the gate all around the nanosheet field effect transistor (GAA NSFET) is assessed in detail at sub-5-nm nodes for digital and analog/RF applications. The gate length (LG) is downscaled from 20 nm to 5 nm to analyse the various DC and analog/RF performance metrics by fixing the remaining device design parameters. When LG is downscaled from 20 nm to 5 nm, I ON is improved by 2.1×, I OFF increases by three orders in magnitude, SS increases by 27%, DIBL is increased by 4×, and a Vth roll off of 41 mV is noticed. Further, an enhancement of 3.65× was noticed in cut-off frequency (f T) with downscaling of LG from 20 nm to 5 nm. On top of that, the circuit level performance is analysed with LG scaling. The lookup table based Verilog-A model is used in the Cadence Virtuoso tool to demonstrate the circuit performance. The CMOS inverter and ring oscillator’s performance was studied in detail with LG scaling. With LG scaling from 20 nm to 5 nm, the inverter performance metrics like switching current (I SC) is increased by 3.87×, propagation delay (τP), energy delay product (EDP) and power delay product (PDP) are reduced by 65%, 5.5× and 1.95× respectively. Moreover, the ring oscillator offers superior performance with an oscillation frequency (f OSC) of 98.05 GHz when LG is scaled to 5 nm, which is 157% more than f OSC at LG of 20 nm. Thus, with downscaling DC performance degraded due to the SCEs. However, the RF performance of the device improved with downscaling of LG towards lower nodes. Thus, the analyses reveal the scaling capability of NSFET at both device and circuit levels for sub-5-nm nodes.

High-throughput functional analysis of autism genes in zebrafish identifies convergence in dopaminergic and neuroimmune pathways

Advancing from gene discovery in autism spectrum disorders (ASDs) to the identification of biologically relevant mechanisms remains a central challenge. Here, we perform parallel invivo functional analysis of 10 ASD genes at the behavioral, structural, and circuit levels in zebrafish mutants, revealing both unique and overlapping effects of gene loss of function. Whole-brain mapping identifies the forebrain and cerebellum as the most significant contributors to brain size differences, while regions involved in sensory-motor control, particularly dopaminergic regions, are associated with altered baseline brain activity. Finally, we show a global increase in microglia resulting from ASD gene loss of function in select mutants, implicating neuroimmune dysfunction as a key pathway relevant to ASD biology.

Comparison Study between Using Disposable and Non-Disposable Ventilator Circuits on Ventilator-Associated Pneumonia and Health Care Costs at a Respiratory Care Unit, Siriraj Hospital

Objective: This research aimed to compare the incidence of ventilator-associated pneumonia (VAP) and ventilator circuit costs among patients using disposable ventilator circuits and patients using non-disposable ventilator circuits.&#x0D; Materials and Methods: Observational research was performed consisting of the following: A retrospective chart review of a group of patients who used non-disposable circuits (n=193) and a prospective cohort study of a group of patients using disposable circuits (n=166). The sample was purposively selected based on the following inclusion criteria: patients aged 18 years old and over who were admitted to the Respiratory Care Unit, Siriraj Hospital and ventilated &gt;48 h.&#x0D; Results: VAP incidence in the group non-disposable circuits was 10.41/1,000 ventilator days (n=27, 13.8%) and 10.82 /1,000 ventilator days (n=24, 14.4%) in the group disposable circuits (p=0.871). According to the data analysis using the U-control chart, no statistically significant differences were found. The unit cost of the non-disposable circuit was lower than that of the disposable circuit (THB 295.94), while the work unit personnel satisfaction toward working with disposable circuits was at a good level (Mean=3.83) and medium level (Mean=3.12) in non-disposable circuits (p=0.002).&#x0D; Conclusion: The type of ventilator circuits had no effects on VAP rate. The unit cost of non-disposable circuits was lower than that of disposable circuits, while the work unit personnel had a higher satisfaction working with disposable circuits than non-disposable circuits.

Development and test of a next-generation positron detector

This report is focused on the development and test of a TDC (time to digital converter) and amplifier circuit for a state-of-the-art positron detector with position sensitivity. A newly developed one chip amplifier-shaper-discriminator (ASD) circuit with 16 channels input and a high-resolution TDC with a timing resolution on the order of picoseconds were tested. Silicon photomultipliers (SiPMs) were employed to give electric pulses for the optical input coming from a pulsed laser. We have successfully controlled the threshold level of the ASD circuit and measured the time structure of the SiPMs, as well as their multiple photon response from the pulse height histogram and the time over the threshold (TOT) histogram measured by the sub-nano second TDC. This is a technical basis for the next generation detector system with the positron tracking capability.

Study on Memristor-Based 3-D Convolutional Neural Network Adapting to Non-Ideal Effects

Memristor-based neural network (MNN) has made breakthroughs in image classification, but for complex video recognition, the required deep MNN will inevitably be more sensitive to non-ideal effects. In this work, we evaluate a memristor-based 3-D convolutional neural network (CNN) for action recognition and incorporate various non-ideal effects at the circuit and device level. Hardware-friendly schemes such as time division multiplexing (TDM) and updating with increasing thresholds are also described. Furthermore, a strategy combining forward averaging and mapping back is proposed to alleviate the IR drop effect. By setting the intersection conductance as the differential reference, deep MNNs are able to adapt to the updating asymmetry. Under the above adaptive strategies and in situ training, the network achieves an accuracy of 92.9% higher than the software and requires fewer updating pulses.

HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy

In this article, we propose a “full-stack” solution to designing high-apacity and low-latency on-chip cache hierarchies by starting at the circuit level of the hardware design stack. We propose a novel half V DD precharge 2T Gain Cell (GC) design for the cache hierarchy. The GC has several desirable characteristics, including ~50% higher storage density and ~50% lower dynamic energy as compared to the traditional 6T SRAM, even after accounting for peripheral circuit overheads. We also demonstrate data retention time of 350 us (~17.5× of eDRAM) at 28 nm technology with V DD = 0.9V and temperature = 27°C that, combined with optimizations like staggered refresh, makes it an ideal candidate to architect all levels of on-chip caches. We show that compared to 6T SRAM, for a given area budget, GC-based caches, on average, provide 30% and 36% increase in IPC for single- and multi-programmed workloads, respectively, on contemporary workloads, including SPEC CPU 2017. We also observe dynamic energy savings of 42% and 34% for single- and multi-programmed workloads, respectively. Finally, in a quest to utilize the best of all worlds, we combine GC with STT-RAM to create hybrid hierarchies. We show that a hybrid hierarchy with GC caches at L1 and L2 and an LLC split between GC and STT-RAM is able to provide a 46% benefit in energy-delay product (EDP) as compared to an all-SRAM design, and 13% as compared to an all-GC cache hierarchy, averaged across multi-programmed workloads.

Effect of Electric Vehicle Charging Stations on the Performance of Distance Relay

Distance protection is considered important and essential in power systems. Due to the development of distribution systems and the system's topology change from time to time, integrating electric vehicles into the distribution system leads to an increase in short circuit level and injection of harmonics into the system. Since the vehicles are continuously variable loads, this leads to difficulty in adjusting the protections that depend on the current in the process of adjusting them. As a result, distance protection is used in distribution systems. This paper shows the effect of integrating electric vehicle charging stations on the relay performance of distance protection in the distribution system. Distance protection relay was built based on artificial neural networks adapted to the system conditions. The accuracy of the neural network model used for fault detection was (99.9%), and the error rate in locating the fault was (0.00079%).

Enhanced Protection Coordination for Inverter Interfaced Distributed Generation (IIDG) with a Robust Multi-Loop Controller

Increasing penetration of inverter interfaced distributed generation (IIDG) in distribution networks has severely impacted protection coordination. False tripping, sympathetic tripping, protection blinding, failure of reclosing, and increase in short circuit levels are the critical complications and consequently disturbed the protection setting of the distribution network. This paper presents a novel multiloop current control scheme based on single integrator backstepping with a proportional resonant (PR) controller assisted by the whale optimization algorithm (WOA) to integrate IIDG in the distribution network. This control approach is designed to mitigate the maloperation of the overcurrent protection, due to the IIDG's current contribution during various types of faults. Inner loop backstepping is utilized to track converter side current and in addition, the PR controller is designed to track grid current in an outer loop. Using the proposed methodology, the injected current to the grid is effectively controlled to the rated level during several types of faults or disturbances. The performance of the proposed control strategy is verified by time-domain results and through eigenvalues trajectory and results have been compared with a current state-of-the-art which corroborates the effective control capability of the present controller.

A low‐power charge‐based integrate‐and‐fire circuit for binarized‐spiking neural network

SummaryThis paper presents a charge‐based integrate‐and‐fire (IF) circuit for in‐memory binary spiking neural networks (BSNNs). The proposed IF circuit can mimic both addition and subtraction operations that permit better incorporation with in‐memory XNOR‐based synapses to implement the BSNN processing core. To evaluate the proposed design, we have developed a framework that incorporates the circuit's imperfections effects into the system‐level simulation. The array circuits use 2T‐2J Spin‐Transfer‐Torque Magnetoresistive RAM (STT‐MRAM) based on a 65‐nm commercial CMOS and a fitted magnetic tunnel junction (MTJ). The system model has been described in Pytorch to best fit the extracted parameters from circuit levels, including the cover of device nonidealities and process variations. The simulation results show that the proposed design can achieve a performance of 5.10 fJ/synapse and reaches 82.01% classification accuracy for CIFAR‐10 under process variation.

Implementation and performance analysis of QPSK system using pocket double gate asymmetric JLTFET for satellite communications

This work is intended to design a quadrature phase shift keying (QPSK) system starting from the device design, characterization and optimization which is then followed by the circuit level implementation and finally the system level configuration. Tunnel Field Effect Transistor (TFET) technology came into existence because of the inability of CMOS (Complementary Metal Oxide Semiconductor) to produce reduced leakage current (Ioff) in the subthreshold regime. With the effects of scaling and requirement of high doping concentrations, TFET is not capable to produce stable reduction in Ioff due to the variation in ON and OFF current. To improve the switching ratio of the current and to obtain good subthreshold swing (SS) by overcoming the limitations of junction TFET, a new device design is proposed for the first time in this work. A pocket double gate asymmetric Junction less TFET (poc-DG-AJLTFET) structure has been proposed in which uniform doping is used to eliminate the junctions and a pocket of length 2 nm made of Silicon–Germanium (SiGe) material has been introduced to improve the designed structure performance in the weak inversion region and increase the drive current (ION). The work function has been tuned to produce the best results for poc-DG-AJLTFET and with our proposed poc-DG-AJLTFET, effects of interface traps are eliminated as against conventional JLTFET structures. The notion that low-threshold voltage device yields high IOFF has been proved wrong with our poc-DG-AJLTFET design, as it produced low threshold voltage with lower IOFF which reduced the power dissipation. Numerical results show that drain induced barrier lowering (DIBL) of 2.75 mV/V is achieved which could be less than 35 times required for short channel effects to be minimum. In terms of gate to drain capacitance (Cgd), it is found that ~ 103 reduction which greatly improves device inertia to internal electrical interference. Also, improvement in transconductance is achieved by 104 times, 103 times improvement in ION/IOFF ratio, and 400 times higher unity gain cutoff-frequency (ft) which would be required by all communication systems. The Verilog models of the designed device are used to construct the leaf cells of quadrature phase shift keying (QPSK) system and the implemented QPSK system is taken as a key evaluator in the performance evaluation in terms of propagation delay and power consumption of poc-DG-AJLTFET in modern satellite communication systems.

Chemogenetic rectification of the inhibitory tone onto hippocampal neurons reverts autistic-like traits and normalizes local expression of estrogen receptors in the Ambra1+/- mouse model of female autism

Female, but not male, mice with haploinsufficiency for the proautophagic Ambra1 gene show an autistic-like phenotype associated with hippocampal circuits dysfunctions which include loss of parvalbuminergic interneurons (PV-IN), decrease in the inhibition/excitation ratio, and abundance of immature dendritic spines on CA1 pyramidal neurons. Given the paucity of data relating to female autism, we exploit the Ambra1+/− female model to investigate whether rectifying the inhibitory input onto hippocampal principal neurons (PN) rescues their ASD-like phenotype at both the systems and circuits level. Moreover, being the autistic phenotype exclusively observed in the female mice, we control the effect of the mutation and treatment on hippocampal expression of estrogen receptors (ER). Here we show that excitatory DREADDs injected in PV_Cre Ambra1+/− females augment the inhibitory input onto CA1 principal neurons (PN), rescue their social and attentional impairments, and normalize dendritic spine abnormalities and ER expression in the hippocampus. By providing the first evidence that hippocampal excitability jointly controls autistic-like traits and ER in a model of female autism, our findings identify an autophagy deficiency-related mechanism of hippocampal neural and hormonal dysregulation which opens novel perspectives for treatments specifically designed for autistic females.

Neural mechanisms of social empathy in the anterior cingulate cortex

Empathy is a prosocial behavior that perceives the emotional state of others, expresses similar perceptions that match those of others, and mediates different social behaviors. Empathic behaviors for pain and fear also exist in primates and rodents. In the past decades, the neural mechanisms of empathy have been defined as a result of various sensations and perceptions, such as visual and hearing stimuli, which cause mirror activations in brain regions, such as the insular, the inferior frontal, and the medial frontal cortices, among which the anterior cingulate cortex (ACC) has been identified as a core region of the neural network that is associated with the empathic activity in mammals. Most studies on the neural mechanisms underlying empathy have been based on rodent models, which allowed for single-cell resolution mapping of neuronal activity; moreover, the application of optogenetic techniques in rodent models has led to a deeper delineation of neural circuits. Here, we review the role of the ACC in two behavioral paradigms, pain and fear empathy, in rodents at the neuronal and neural circuit levels. Understanding how the ACC mediates empathic behavior in the brain will provide new targets in the treatment for neuropsychiatric disorders characterized by empathic disorders.