Circuit Leakage Research Articles

Safety for Electric Shower Water Heater installation in Indonesia

Death casualties due to electrocution when showering using electric shower water heater (ESWH) have been reported. The cases included the use of either water heater with storage system or the instantaneous water heater. There are three factors that may contribute to the event, namely, the improper installation including the grounding and wiring systems, the equipment factor, and the human error. The first two factors are the most dominant. This paper presents scenarios when one may experience an electrocution during showering, the current safety regulations in Indonesia regarding the installation of the electric shower water heater, and the mitigations to avoid casualties. The additional of ELCB (Earth Leakage Circuit Breaker) may increase the safety factor as it protects the user from an electrical shock in shorter duration than the common Main Circuit Breaker (MCB). A successful ELCB depends also on the correct installation of protection earth wiring and grounding.

Electromagnetic susceptibility of earth leakage circuit breakers and a countermeasure

Electromagnetic susceptibility of earth leakage circuit breakers and a countermeasure

Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater

Transistor threshold voltage (Vt) scaling causes higher power consumption by increasing the subthreshold leakage and short-circuit currents in CMOS circuits. Leakage currents are significant contributors to the overall power consumption of digital systems-on-chip as threshold voltage, channel length, and gate oxide thickness are reduced with CMOS technology scaling. A new dual-pullup/dual-pulldown (DPU/DPD) repeater is proposed in this paper for higher energy efficiency in low-voltage and low-frequency applications. The standby mode leakage power consumption is reduced by 59.11% with the proposed clock tree as compared to the conventional 3 level H-tree operating with a power supply voltage of 1.0V in a 45 nm CMOS technology. The short-circuit currents are suppressed by selectively employing high-Vt transistors in the repeaters. The clock network with the proposed buffer lowers the active mode energy consumption by up to 24.91% as compared to a conventional clock tree under equal silicon area constraint. Post layout results reveal that the statistical spread of clock skew in the DPU/DPD H-tree is also 20.60% lower than the conventional H-tree network.

THE ANALYSIS OF THE THREE-PHASE INDUCTION MOTOR WITH DEEP ROTOR BARS THROUGH NUMERICAL SIMULATIONS UTILIZING A MODIFIED MATHEMATICAL MODEL

The three-phase induction machine mathematical model presented in the paper, is adequate for applying to the deep rotor bars case. The rotor resistance R’r(r), respectively its leakage inductivity L’r(r), depend upon the rotor currents’ frequency fr because of the skin effect. Following the previous considerations, one developed slip dependent analytical expressions of the rotor circuit resistance R’r(s), respectively rotor circuit leakage reactance L’r (s). A modified space phasor based mathematical model of the deep bar induction motor is tested through simulations to assess the motor’s characteristics. The results are in accordance with the literature.

Measurement of fluid flow rate using nanocomposite silicone rubber sensor

This paper describes the use of an elastic nanocomposite sensor to measure the water flow rate in open and closed hydraulic circuits. A sensor was constructed of multiwalled carbon nanotubes (MWCNTs) dispersed in silicone rubber (SR) and subsequently tested to verify its ability to measure water flow rate. The results reveal that the correlation between the fluid flow rate and the pressure variation across the sensor entails that its electrical resistance can be correlated to the flow rate. The sensor constructed of 2 and 3 wt,% of MWCNTs in SR-based nanocomposite sensors exhibited a low percolation threshold. An electron microscope (HRSEM) was used to characterize the manufactured nanocomposite sensors and confirm the conductive networks. The variation in the electrical resistance of the sensor in terms of both water pressure and flow rate is described. The elastic sensor was calibrated to measure the water flow rate in the range of 0–35 l/min. The results show that an elastic sensor fabricated from MWCNTs dispersed in silicone rubber does exhibit sensitivity to the slight strain levels produced by dynamic water pressure and, as such, can be used to measure flow rate. In addition, the sensor's response to water flow in the presence of bubbles enables pump cavitation monitoring. This paper also investigates the reduction of sensor electrical conductivity in response to water immersion. The findings reveal that the elastic nanocomposite sensor could potentially be used as a liquid sensor to detect water leakage in hydraulic circuits.

Design and Simulation of Reliable Low Power CMOS Logic Gates

In this paper, a circuit-level reliable low leakage design methodology is proposed for integrated circuits (ICs). Low leakage circuit design is the most challenging research area for very large-scale integration (VLSI) circuit designers due to the increased demand of battery-operated portable systems. Leakage power is increasing continuously with each new technology node generation in deep sub-micron (DSM) regime. Large power dissipation harms the device characteristics and affects the overall performance of the circuits. Proposed approach is extensively discussed and verified for the low power operation and reliability. The various logic circuits are simulated and compared with the available leakage minimization techniques at 22 nm technology node using predictive technology model (PTM) bulk CMOS BSIM4 on HSPICE tool. Proposed approach reduces leakage power by ≈81% in XOR2 and XNOR2 gates as compared to conventional CMOS gates. Reliability of the nanoscaled circuits is affected by several device parameters. Process, voltage and temperature (PVT) variations, aging and radiation effects are considered for reliability testing. The reliability of the proposed approach is improved by 77.45% for power delay product (PDP) metric for the ring oscillator as compared to conventional circuit.

A Study of a New Bidirectional Pressure-Regulating Valve for Hydraulically Interconnected Suspension Systems

Abstract Due to inevitable inner leakage in hydraulic circuits and structural limits of a hydraulically interconnected suspension (HIS) system, pressure difference between HIS's two independent hydraulic circuits leads to vehicular unbalance under noncornering driving conditions and deteriorates HIS's performance under steering driving conditions. In order to address this problem, a new bidirectional pressure-regulating valve was designed to balance hydraulic pressures in the two HIS's hydraulic circuits under noncornering driving conditions. Moreover, it separates the two hydraulic circuits and enables HIS's antirollover function under cornering driving conditions. Detailed structure and functions of this valve were introduced first. Systematic and computational fluid dynamics (CFD) simulation results show that the gap between the spool and cylinder is of importance to valve's performance. Experimental results validate that the developed valve satisfies all requirements of the HIS. Furthermore, the valve can distinguish steering and nonsteering conditions and enables HIS's function accurately without any pressure shock.

Aptamer-Braked Multi-hairpin Cascade Circuits for Logic-Controlled Label-Free In Situ Bioimaging.

As a common hairpin-based amplification strategy, catalytic-hairpin assembly (CHA) has been widely used to construct various DNA circuits for biosensing and imaging. However, the hairpin substrates can potentially react without catalysts and result in circuit leakage, which may be quite severe in a CHA reaction consisting of three or four hairpins due to the formation of stable three-/four-way junction product. To circumvent this problem, here we introduce a well-designed ATP aptamer as a DNA brake into a four-hairpin cascade circuit, where the triggering toehold is blocked by the aptamer brake and thus the circuit leakage decreases dramatically. Such an aptamer-braked DNA circuit is then employed to build an AND logic gate in response to multiple external stimuli in acidic cell membrane microenvironments. Induced by a bimolecular i-motif that binds thioflavin T (ThT), the dimerization of a four-way junction in situ assembled on the cell surface is accomplished, enabling the logic-controlled cell membrane imaging in a label-free manner. Our design would be applicable to other hairpin-based amplification strategies and may find more applications in the construction of multiresponsive DNA cascade circuits in complex living systems.

Development and Safety Evaluation of Earth Leakage Alarm Breaker Equipped with Fire Current (IGR) Alarming Function

The purpose of this study is to develop an earth leakage alarm circuit breaker, equipped with a leakage alarming function (JER-E2S, ETECKOREA Co., Korea), and to analyze its characteristics. The developed mechanism is exclusively used for single-phase and 220 V circuits, with a rated current of 32 A, 20 A, 20 A (for restrooms), 16 A, etc. It satisfies all characteristics of existing earth leakage circuit breakers (ELB). If a fire current, which is a resistive leakage current (Igr), flows through an electric line, the device detects the leakage current in real time and warns against the leakage through a blinking LED lamp. Since the developed device displays a tolerance to a capacitative leakage current (Igc) that inevitably occurs in LED lamps, communication devices, etc., it ensures a stable power supply. In addition, the earth leakage alarm circuit breaker protects against power failure due to a momentary ground fault. Therefore, it can supply power without the risk of the circuit breaker malfunctioning due to a momentary ground fault caused by water droplets, leaves, etc. Moreover, with a standby power of less than 0.1 W, the developed earth leakage alarm circuit breaker exhibits a power saving performance that is 3~8 times greater than that of other ELBs. Installation of approximately 10 earth leakage alarm circuit breakers in one apartment household, with an area of 120 m2, can save 2~5 kWh per month. Therefore, the developed earth leakage alarm breaker not only satisfies the characteristics of existing earth leakage breakers, but also exhibits outstanding power supply quality since it has the functions of electric fire prevention and malfunction prevention. Therefore, this device can innovatively contribute to electric fire prevention.

Damage control of ion implantation for advanced doping process by using in-situ temperature control

Most silicon nano-devices use ion implantation doping for electric characteristics due to precise control of concentration and location of the dopants. A consequence of ion implantation is the damage to the silicon caused when injecting dopants into silicon substrate that break the silicon structure. This damage causes leakage or electron trapping in device circuits. Therefore, minimizing implant damage is of high importance. In general, ion implantation uses photoresist coatings, which can endure no more than 200 °C to make selected area doping. We characterized ion implantation damage on bare wafers by optimizing the process temperature during implant. Elevated temperatures during implant induce “self-annealing” which reduces the damage to the silicon structure as the implant occurs. We propose that in-situ temperature control can limit ion implant damage on the transistor well and photo diode steps on advanced Complementary Metal-Oxide Semiconductor (CMOS) image sensor devices.

An insulation diagnosis method for battery pack based on battery model

The collision and components aging of electric vehicles may lead to dramatic decrease of insulation performance in the complex application environment, which will reduce the insulation between battery pack and chassis, and will affect the performance of on-board equipment and electronic control unit, resulting in heat accumulation effect of leakage circuit and even vehicle fire. Therefore, it is critical to develop a real-time, accurate and reliable detection device to monitor the insulation resistance of the high-voltage system of electric vehicles, which is beneficial to the normal operation of electrical equipment, the safe operation of vehicles and the personal safety of passengers. In this work, an online estimation method of insulation resistance based on battery model is proposed.

Leakage circuit characteristics of a bipolar membrane electrodialyzer with 5 BP-A-C units

Leakage currents inevitably exist in all liquid channels of the plate-and-frame membrane stacks in bipolar membrane electrodialysis (BMED) systems. These leakage currents decrease the efficiency of the devices, and may even cause undesirable heat that can affect non-metallic components used in the membrane stack. In this study, a laboratory-scale BMED system was set up for treating high ammonium chloride organic wastewater. An electrical circuit model consisting of three hydraulic circuits in the membrane stack was established, and processed by using the simulation software Multisim. The leakage circuit characteristics of the BMED system with 5 BP-A-C units were monitored during the desalination process. The electrical resistances of the ducts/slots were shown to be influenced by solution conductivity and geometry. The voltages, currents, and thermal effects at the ducts/slots presented a symmetrical distribution in the membrane stack, and were affected by their electrical resistances during the desalination process. Measures were proposed to minimize any negative effects to improve the BMED design.

Heat transfer intensification in emergency cooling heat exchanger and dry cooling towers on nuclear power plant using air-water mist flow

Advanced nuclear power plants are equipped with passive emergency heat removal systems (PEHRS) for removing the decay heat from reactor equipment in accidents accompanied by primary circuit leakage to the final heat absorber (ambient air). Herein, the intensity of heat dissipation to air from the outer surface of the heat exchanger achieved by buoyancy induced natural convection is extremely low, which need to a large heat exchanger surface area, apply different types of heat transfer intensification including (grooves, ribs and extended surfaces, positioning at higher altitudes, etc.). The intensity of heat removal is also strongly dependent on the ambient air temperature (disposable temperature head). Construction of nuclear power plants in countries with high ambient temperatures (Iran, Bangladesh, Egypt, Saudi Arabia, and others) which are characterized by a high level of ambient temperature imposes additional requirements on the increase of the heat exchange surfaces. The experimental investigation results of heat transfer intensification by a low energy ultrasonic which supply a fine liquid droplet (size ~3 µm) in the cooling air are presented in the present paper. In such case, the heat transfer between the surface and cooling flow involves the following three physical effects: convection, conductive heat transfer, and evaporation of water droplets. The last two effects weakly depend on the ambient air temperature and provide an active heat removal in any situation. The investigation was performed using a high-precision calorimeter with a controlled rate of heat supply (between 7800 and 12831 W/m2) imitating heated surface within the range of Reynolds numbers from 2500 to 55000 and liquid (water) flow rates from 23.39 to 111.68 kg·m-2·h-1. The studies demonstrated that the presence of finely dispersed water results in a significant increase in heat transfer compared with the case of using purely air-cooling. With a fixed heat flux, the energy efficiency increases with increasing water concentration, reaching the values over 600 W·m-2·C-1 at 111.68 kg·m-2·h-1, which is 2.8 times higher than for air cooling. With further development of research in order to clarify the optimal areas of intensification, it is possible to use this technology to intensify heat transfer to the air in dry cooling towers of nuclear power plants and thermal power plants used in hot and extreme continental climates.

Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power Efficient Technique for VLSI Circuit Design

This paper presents a novel ultra-low-power Sleepy CMOS-Sleepy Stack (SC-SS) technique for nano scale VLSI technologies. Eight prior techniques are taken for comparison with proposed technique on 65[Formula: see text]nm technology. All the techniques are applied on four benchmark circuits: XOR gate, 1-bit adder, 1-bit comparator and 4-bit up-down counter for measurement of area consumption and total power dissipation. The proposed SC-SS technique achieved very high power efficiency as compared to Complementary CMOS technique (CCT), Dual sleep Technique (DST), Forced stack technique (FST), Sleepy keeper technique (SKT), Sleepy pass gate technique (SPGT), Sleep transistor technique (STT) and VLSI CMOS Circuit Leakage Reduction technique (VCLEARIT). Although Sleepy stack technique (SST) is power efficient as compared to SC-SS technique, this is on the expense of area and delay penalty. Proposed technique has shown the area improvement of 33% for XOR, 10.78 % for 1-bit adder, 14.9% for 1-bit comparator and 9.7% for 4-bit up-down counter over SST technique on 65[Formula: see text]nm technology. At the same time, power-area product of SC-SS is 29.56% and 54.96% less as compared to SST for XOR and 4-bit up-down counter. To obtain the efficiency of proposed technique over SST in terms of delay and power-delay product, basic inverter design is taken into consideration. Delay of SC-SS inverter is 34.8% and power-delay product is 6.9% less as compared to SST inverter on 65[Formula: see text]nm technology.

基于分布式光纤拉曼测温系统的核电一回路泄漏点监测技术

基于分布式光纤拉曼测温系统的核电一回路泄漏点监测技术

Physics-based modeling of TID induced global static leakage in different CMOS circuits

Compact modeling of inter-device radiation-induced leakage underneath the gateless thick STI oxide is presented and validated taking into account CMOS technology and hardness parameters, dose-rate and annealing effects, and dependence on electric modes under irradiation. It was shown that proposed approach can be applied for description of dose dependent static leakage currents in complex FPGA circuits.

An Exploration of Applying Gate-Length-Biasing Techniques to Deeply-Scaled FinFETs Operating in Multiple Voltage Regimes

With the aggressive downscaling of process technologies and the importance of battery-powered systems, reducing leakage power consumption has become a crucial design challenge for IC designers. In addition, the traditional bulk CMOS technologies face significant challenges related to short-channel effects and process variations. FinFET devices have attracted a lot of attention as an alternative to bulk CMOS in sub-32nm technology nodes. This paper presents a device-circuit cross-layer framework to utilize fine-grained gate-length biased FinFETs for circuit leakage power reduction in near- and super-threshold ( $V_T$ ) operation regimes. The impacts of cell-level and transistor-level Gate-Length Biasing (GLB) on circuit speed and leakage power are studied using a 7 nm FinFET technology.

An Ultralow Leakage Synaptic Scaling Homeostatic Plasticity Circuit With Configurable Time Scales up to 100 ks.

Homeostatic plasticity is a stabilizing mechanism commonly observed in real neural systems that allows neurons to maintain their activity around a functional operating point. This phenomenon can be used in neuromorphic systems to compensate for slowly changing conditions or chronic shifts in the system configuration. However, to avoid interference with other adaptation or learning processes active in the neuromorphic system, it is important that the homeostatic plasticity mechanism operates on time scales that are much longer than conventional synaptic plasticity ones. In this paper we present an ultralow leakage circuit, integrated into an automatic gain control scheme, that can implement the synaptic scaling homeostatic process over extremely long time scales. Synaptic scaling consists in globally scaling the synaptic weights of all synapses impinging onto a neuron maintaining their relative differences, to preserve the effects of learning. The scheme we propose controls the global gain of analog log-domain synapse circuits to keep the neuron's average firing rate constant around a set operating point, over extremely long time scales. To validate the proposed scheme, we implemented the ultralow leakage synaptic scaling homeostatic plasticity circuit in a standard 0.18m complementary metal-oxide-semiconductor process, and integrated it in an array of dynamic synapses connected to an adaptive integrate and fire neuron. The circuit occupies a silicon area of 84 m 22m and consumes approximately 10.8nW with a 1.8V supply voltage. We present experimental results from the homeostatic circuit and demonstrate how it can be configured to exhibit time scales of up to 100 ks, thanks to a controllable leakage current that can be scaled down to 0.45aA (2.8 electrons per second).

A Leakage-Tolerant 16 – Bit Comparator using Lector Technique Based Footless Domino Logic Circuit

The continuous scaling has resulted in increased sub-threshold leakage current due to decreased threshold voltage. LECTOR is a technique to decrease the problem of leakage in CMOS circuits, it includes a p-type and n-type leakage controlled transistors (LCTs), which are self-controlled, between supply to ground which offers the extra resistance which will reduce the problem of leakage current in the CMOS circuits. In this paper 16-bit Lector based standard foot-less domino (SFLD) comparator is introduced, which provides 74% efficient reduction in leakage and is also efficient in terms of performance compared to basic 16-bit SFLD comparator. Simulations are performed in gpdk_90 nm CMOS technology using cadence virtuoso tool.

ZigBee를 적용한 누전상태 모니터링시스템 구현

최근 가정이나 산업용 건물에서 컴퓨터, TV, 냉장고, LED 조명 등 가전기기들의 누전전류에 의한 감전사고가 지속적으로 발생하고 있다. 그리고 가정 내 벽면에 설치된 콘센트에 직접 연결되어 제어 하는 누전차단 모듈들은 모듈 후단에 병렬로 연결된 각각의 가전기기들의 누전상태를 확인하기가 쉽지 않다. 또한 전류가 정상적인 전류의 통로 이외로 흐르는 누전전류를 기존의 누전차단기들은 배전함에 설치되어 누전시 전원을 차단해 주는 역할 을 한다. 가전기기의 누전으로 인한 감전, 화재 등 여러 가지 재해가 발생하여 누전전류의 위험성이 심각하게 제시되고 있다. 이에 근거리 무선통신시스템 중에서 저전력과 저가격 면에서 장점이 많은 IEEE 80215.4 기반의 지그비통신을 이용하여 상시 감시할 수 있는 누전상태 모니터링시스템 구현방안을 제시한다. In recent years, electric shock accidents due to electric leakage currents of household appliances such as computers, TVs, refrigerators, and LED lights are continuously occurring in homes and industrial buildings. And it is not easy to check the leakage current of each household appliances connected in parallel at the rear end of the module. In addition, the leakage current flowing through the path of the normal current other than the existing current leakage circuit breakers are installed in the distribution box, only the function to cut off the power when the leakage. Therefore, there are various disasters such as electric shock and fire caused by short circuit of household appliances, and the risk of such leakage current is seriously presented. In this paper, we propose a method to implement a leakage monitoring system that can be monitored at all times using Zigbee communication based on IEEE 80215.4, which has advantages in low power and low cost among short range wireless communication systems.