Circuit Latency Research Articles

A novel technique for eliminating iterative based computation of polarity of micro-rotations in CORDIC based sine–cosine generators

The CORDIC algorithm has been readily used to decimate trigonometric and hyperbolic functions with simple shift and add operations. Despite further refinements in terms of circuit latency and performance of the algorithm with the introduction of redundant arithmetic and higher radix CORDIC techniques, the iterative nature remains to be the major bottleneck for further optimisation. In this paper, a novel approach for the pre-computation of the polarity of micro-rotations has been proposed to eliminate the iterative process during sine/cosine computations. This approach to determine the signed digits lends well towards realising high-speed sine/cosine functions. It relies on a new technique, called Split Decomposition Algorithm, devised for the VLSI efficient implementation of the pre-computation of the polarity of micro-rotations. A ROM less architecture for the pre-computation of the polarity of micro-rotations has been devised with the help of a new algorithm that exploits certain properties of the signed digits. The architectures for 24-bit and 32-bit versions were implemented using VHDL and extensive simulations have been performed to validate the results. The functionally simulated net list has been synthesised with 0.35μ technology library and the area-time measures are provided.

Pipelining flat CORDIC based trigonometric function generators

Despite further refinements of the CORDIC algorithm with the introduction of redundant arithmetic and higher radix CORDIC techniques, in terms of circuit latency and performance, the iterative nature remains to be the major bottleneck for further optimization. A technique known as flat CORDIC, in which the conventional X and Y recurrences are successively substituted to express the final vectors in terms of the initial vectors, can be used to eliminate the iterative process. In this paper, the techniques devised for the VLSI efficient implementation of a pipelined 16-bit flat CORDIC based sine–cosine generator are presented. Three possible schemes to pipeline the 16-bit flat CORDIC design have been presented to demonstrate the suitability of the proposed method to realize high throughput implementations. The 16-bit architecture has been synthesized with 0.35μ CMOS process library using Synopsys. Finally, a detailed comparison with other major contributions show that the flat CORDIC based sine–cosine generators are, on average, 30% faster and occupy some 30% less silicon area.

A self-timed real-time sorting network

High-speed networks are expected to carry traffic classes with diverse quality of service (QoS) guarantees. For efficient utilization of resources, sophisticated scheduling protocols are needed; however, these must be implemented without sacrificing the maximum possible bandwidth. This paper presents the architecture and implementation of a self-timed real-time sorting network to be used in packet switches that support a diverse mix of traffic. The sorting network receives packets with appropriately assigned priorities and schedules the packets for departure in a highest-priority-first manner. The circuit implementation uses zero-overhead, self-timed, and self-precharging domino logic to minimize the circuit latency. An experimental sorting network chip has been designed using the techniques described in this paper to support 10 Gb/s links with ATM-size packets.

Redundant interconnections for fault-tolerant digital optical computing

We show how multilayer optical-interconnect-based digital logic systems can be made fault-tolerant by distributed redundancy tech- niques implementable at the gate level, while incurring the expense of an increased number of gates with greater individual fan-in and fan-out. We demonstrate that braided logical interconnections between redundantly doubled, tripled, and quadrupled NOR gates enable the correction of device and interconnection errors. We present an extrapolated error analysis for the quadding, doubling, and tripling schemes, which shows the quadratic and cubic dependence of the system error on device error rates, in comparison with the linear relationship of a nonredundant sys- tem. Because the interconnections between the braided circuits are quite regular, they appear to be very amenable to optical implementations, and with the appropriate choice of device topology employing sparse device placement they are compatible with the regular, layered structure of conventional shift-invariant digital optical computer interconnects, without a penalty in circuit depth or latency. We show device topologies and interconnection architectures for the optical implementation of a fault-tolerant quadded programmable two-shuffle interconnection system that use holographic shift-invariant interconnects. Using these redundant optical logic schemes with only moderate device error probabilities, ex- tremely low system error rates can be achieved. © 1999 Society of Photo- Optical Instrumentation Engineers. (S0091-3286(99)01303-3) Subject terms: optical interconnects; optical computing.

BEYOND SPICE, A REVIEW OF MODERN ANALOG CIRCUIT SIMULATION TECHNIQUES

We present a review of modern analog simulation techniques based on time- and frequency-domain algorithms. For time-domain techniques, important topics such as circuit decomposition, relaxation methods, latency, multirate integration, continuation methods, parallel algorithms, and finite difference time-domain methods are discussed. Frequency-domain simulation techniques included are harmonic balance, harmonic relaxation, harmonic-Newton, spectral balance, methods for quasiperiodic circuits, and device modeling for frequency domain simulators. Also included are examples of modern simulators.

A systematic methodology for the design of high performance recursive digital filters

A systematic design methodology is described for the rapid derivation of VLSI architectures for implementing high performance recursive digital filters, particularly ones based on most significant digit (msd) first arithmetic. The method has been derived by undertaking theoretical investigations of msd first multiply-accumulate algorithms and by deriving important relationships governing the dependencies between circuit latency, levels of pipelining and the range and number representations of filter operands. The techniques described are general and can be applied to both bit parallel and bit serial circuits, including those based on on-line arithmetic. The method is illustrated by applying it to the design of a number of highly pipelined bit parallel IIR and wave digital filter circuits. It is shown that established architectures, which were previously designed using heuristic techniques, can be derived directly from the equations described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Adaptively controlled explicit simulation

Adaptively Controlled Explicit Simulation (ACES) is a timing simulation methodology for the verification of the transient behavior of integrated circuits. A new adaptively controlled explicit integration approximation is used that overcomes stability problems encountered in earlier explicit techniques. Circuit partitioning is employed, which allows event driven simulation and exploitation of circuit latency. Piecewise linear models are used for nonlinear devices, allowing efficient simulation of MOS, bipolar, and BiMOS circuits. Simulation accuracy in ACES can be varied by controlling the accuracy of either the integration approximation or the piecewise linear device models. With the combination of generality, exploitation of circuit latency, and ability to vary accuracy effectively, ACES provides an efficient environment for transient simulation of integrated circuits and systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>