Circuit Implementation Research Articles

A Spatial‐Based Quantum Graph Convolutional Neural Network and Its Full‐Quantum Circuit Implementation

AbstractWith the rapid advancement of quantum computing, the exploration of quantum graph neural networks is gradually emerging. However, the absence of a circuit framework for quantum implementation and limited physical qubits hinder their realization on real quantum computers. To address these challenges, this paper proposes a spatial‐based quantum graph convolutional neural network and implements it on a superconducting quantum computer. Specifically, this model exclusively consists of quantum circuits, including quantum aggregation circuits in the quantum graph convolutional layer and quantum classification circuits in the quantum dense layer. To meet the requirements of Noisy Intermediate‐Scale Quantum computing, a first‐order extraction method to reduce circuit size is employed. Experimental results in node classification tasks demonstrate that this model achieves comparable or even superior performance compared to classical graph neural networks while utilizing fewer parameters. Therefore, this model can inspire further advancements in quantum graph neural networks and facilitate their implementation on physical quantum devices.

Programming universal unitary transformations on a general-purpose silicon photonic platform

General-purpose programmable photonic processors provide a versatile platform for integrating diverse functionalities on a single chip. Leveraging a two-dimensional hexagonal waveguide mesh of Mach–Zehnder interferometers, these systems have demonstrated significant potential in microwave photonic applications. Additionally, they are a promising platform for creating unitary linear transformations, which are key elements in quantum computing and photonic neural networks. However, a general procedure for implementing these transformations on such systems has not been established yet. This work demonstrates the programming of universal unitary transformations on a general-purpose programmable photonic circuit with a hexagonal topology. We detail the steps to split the light on-chip, demonstrate that an equivalent structure to the Mach–Zehnder interferometer with one internal and one external phase shifter can be built in the hexagonal mesh, and program both the triangular and rectangular architectures for matrix multiplication. We recalibrate the system to account for passive phase deviations. Experimental programming of 3 × 3 and 4 × 4 random unitary matrices yields fidelities >98% and bit precisions over five bits. To the best of our knowledge, this is the first time that random unitary matrices are demonstrated on a general-purpose photonic processor and pave the way for the implementation of programmable photonic circuits in optical computing and signal processing systems.

Strongly perturbed bondorbital attractors for generalized systems.

This paper analyzes a generalized chaotic system of differential equations characterized by attractors with bondorbital structures. Both classical and fractional-order cases are examined analytically and numerically, with convergence and stability analyses provided. The numerical findings confirm the presence of bondorbital attractors in the classical system. In contrast, bondorbital attractors also emerge in the fractional model employing the Caputo-Fabrizio operator, albeit with significant perturbations for specific fractional orders. To validate these results, an electric circuit implementation of the fractional-order system using an field-programmable gate array board was conducted, yielding consistent outcomes. This study highlights the potential of fractional calculus, particularly the Caputo-Fabrizio operator, in capturing the memory effects and complex dynamics of chaotic systems. The work bridges theoretical modeling and practical hardware applications, offering valuable insights for modeling complex systems.

HSPICE simulation and analysis of current reused operational transconductance amplifiers for biomedical applications

The proposed work focuses on the design of a current-reused biomedical amplifier; it is a microwatt-level electrocardiogram (ECG) analog circuit design that addresses low power consumption and noise efficiency. As implantable devices require unobtrusiveness and longevity, the current reuse technique in this circuit effectively enhances power and noise efficiencies. Using 90 nm technology enables efficient circuit implementation, yielding promising simulation results. At 100 Hz, the noise performance reaches 62.095 nV/√Hz, while the power consumption is only 8.3797 µW. These advancements are pivotal for next-generation implantable devices, ensuring reliable operation and reducing frequent battery replacements, improving patient convenience. Moreover, the high noise efficiency ensures that ECG signals are captured with high fidelity, crucial for accurate monitoring and diagnosis. This research addresses the challenges in implantable ECG analog circuit design and sets a benchmark for future developments. The techniques employed can be adapted for other bio signal monitoring devices, broadening the impact on healthcare technology. Ultimately, this advancement contributes to more efficient, reliable, and long-lasting medical devices, enhancing patient monitoring and healthcare on a broader scale.

Chaos Regulation via Complex Nonlinear Feedback and Its Implementation Based on FPAA

Complex nonlinear feedback is a key factor in the generation of chaos. In many cases, complex nonlinear functions have a higher probability for chaos producing, and correspondingly new bifurcations may be triggered in the dynamical system. Due to the difficulty in circuit implementation of complex nonlinear feedback, researchers often introduce simple nonlinear constraints to study the occurrence and evolution of chaos. In fact, the impact of complex nonlinear feedback on chaotic dynamics deserves further investigation. In this work, complex nonlinear feedback is introduced into an offset-boostable chaotic system as an example to observe and analyze its regulatory effect on the dynamics. Complex nonlinear feedback may destroy the property of symmetry of a system; therefore, we examine the evolution of chaotic attractors under the corresponding feedback and the functional transformation between bifurcation and non-bifurcation parameters as well. By fully utilizing the flexible configuration advantages of Field Programmable Analog Array (FPAA), arbitrary complex nonlinear functions are implemented to verify the chaotic dynamics.

Back side power delivery: Revolutionizing chip design

Backside power delivery network technology represents a revolutionary advancement in semiconductor design, addressing critical power distribution challenges in advanced process nodes. This architectural innovation separates power delivery from signal routing through vertical integration, enabling significant improvements in chip performance and efficiency. The approach incorporates nano-Through Silicon Vias for direct power delivery through thinned silicon substrates, dramatically reducing routing congestion and IR drop while enhancing signal integrity. Intel's PowerVia implementation, alongside developments from other major semiconductor manufacturers, demonstrates the technology's potential to transform power delivery architectures. The solution not only improves thermal management and reduces voltage droop but also enables greater design flexibility through simplified routing and optimized circuit implementation. Despite initial manufacturing complexities, the long-term benefits include enhanced yield rates, reduced design cycles, and improved performance metrics. The technology's adoption across the semiconductor industry marks a pivotal shift in power delivery architecture, positioning it as a crucial enabler for future semiconductor scaling and high-performance computing applications.

Optimizing Circuit Reusing and its Application in Randomized Benchmarking

Quantum learning tasks often leverage randomly sampled quantum circuits to characterize unknown systems. An efficient approach known as ``circuit reusing,'' where each circuit is executed multiple times, reduces the cost compared to implementing new circuits. This work investigates the optimal reusing times that minimizes the variance of measurement outcomes for a given experimental cost. We establish a theoretical framework connecting the variance of experimental estimators with the reusing times R. An optimal R is derived when the implemented circuits and their noise characteristics are known. Additionally, we introduce a near-optimal reusing strategy that is applicable even without prior knowledge of circuits or noise, achieving variances close to the theoretical minimum. To validate our framework, we apply it to randomized benchmarking and analyze the optimal R for various typical noise channels. We further conduct experiments on a superconducting platform, revealing a non-linear relationship between R and the cost, contradicting previous assumptions in the literature. Our theoretical framework successfully incorporates this non-linearity and accurately predicts the experimentally observed optimal R. These findings underscore the broad applicability of our approach to experimental realizations of quantum learning protocols.

Design and analysis of circular sheet junctionless double gate vertical nanotube (CSJL-DG-VNT) FET for DC/Analog/RF applications: device to circuit implementation

This paper investigates the influence of geometrical variations on the performance characteristics of a novel circular sheet junctionless double gate vertical nanotube (CSJL-DG-VNT) FET through 3D numerical simulations at sub-5nm technology node. Initially, the proposed device is compared with NWFET and NSFET, and shown favourable performance. The ION/IOFF current ratio is improved to 51.9% when gate length (Lg) is sweeping from 8 nm to 12 nm. The decrease in L g leads to enhanced analog/RF metrics such as gm, gm/Id, and fT. It was observed that opting for the shortest L g may be advantageous for certain parameters, albeit at the expense of others, depending on the specific application requirements. Further, while maintaining a constant L g , variations in the thickness tNT from 5 to 10 nm were carried out to evaluate the analog/RF performance for device optimization. It was observed that lower tNT (5 nm) values yielded improved IOFF current around ∼ 2 order and DIBL is 32.77% when compared with higher tNT (10 nm) due to ameliorated channel control from both inner and out gate of VNT. Subsequently, at an optimal L g and t NT the temperature (T) varied from 250 K to 450 K to analyze the device characteristics, indicating that a lower T should be favoured. Furthermore, the device is used for designing a common-source (CS) amplifier with tNT variations and noticed that at 5 nm of t NT outperforms highest gain (AV) ∼ 6.8 V/V when compared to 7 nm and 10 nm.

Enhancing circuit development and layout implementation of benchmark circuit in 0.18-µm CMOS technology

Power consumption and delay are the most critical factors in circuit development and layout implementation. It is challenging to optimize all aspects simultaneously. This research addresses this challenge by analysing the power consumption and delay effects in benchmark circuit operation, C6288, using 0.18-µm CMOS technology operating at an optimal voltage of 1.6V. Additionally, this research also contributes to developing the initial layout implementation of a benchmark circuit with a 10% area reduction. By utilizing new layout techniques and simulations, the study has proven a significant decrease in power consumption and enhanced area optimization with a moderate increase in delay at 1.6V, all while maintaining acceptable performance standards. In addition, simulation results indicate less than a 10% deviation between pre and post-layout designs. Finally, through the properties of layout design and the research conclusions, it has provided valuable insights for the design of energy-efficient digital circuits in CMOS technology.

Simple Memristive Chaotic Systems with Complex Dynamics

The exploration of memristive chaotic systems (MCSs) has been a prominent area of research due to the inherent richness of their dynamical characteristics. The objective of this paper is to propose two chaotic systems, derived from a common basic system, which also exhibit distinct characteristics such as coexisting attractors and robustness of chaos while maintaining the common attributes of multi-parameter amplitude modulation and large-scale offset boosting. The evolution process of MCSs' dynamical behavior with changes to parameters and initial values is described in detail through the analysis of bifurcation diagrams, Lyapunov exponents (LEs), and phase projections. Furthermore, the findings of the numerical simulations are validated by circuit implementations, thereby providing additional confirmation of the existence of the two memristive chaotic systems constructed and their potential for practical applications.

Heterogeneous integration of amorphous silicon carbide on thin film lithium niobate

In the past decade, lithium niobate (LiNbO3 or LN) photonics, thanks to its heat-free and fast electro-optical modulation, second-order non-linearities, and low-loss, has been extensively investigated. Despite numerous demonstrations of high-performance LN photonics, processing lithium niobate remains challenging and suffers from incompatibilities with standard complementary metal–oxide–semiconductor (CMOS) fabrication lines, limiting its scalability. Silicon carbide (SiC) is an emerging material platform with a high refractive index, a large non-linear Kerr coefficient, and a promising candidate for heterogeneous integration with LN photonics. Current approaches of SiC/LN integration require transfer-bonding techniques, which are time-consuming, expensive, and lack precision in layer thickness. Here, we show that amorphous silicon carbide (a-SiC), deposited using inductively coupled plasma enhanced chemical vapor deposition at low temperatures (<165 °C), can be conveniently integrated with LiNbO3 and processed to form high-performance photonics. Most importantly, the fabrication only involves a standard, silicon-compatible, reactive ion etching step and leaves the LiNbO3 intact, hence its compatibility with standard foundry processes. As a proof-of-principle, we fabricated waveguides and ring resonators on the developed a-SiC/LN platform and achieved intrinsic quality factors higher than 1.06 × 105 and a resonance electro-optic tunability of 3.4 pm/V with a 3 mm tuning length. We showcase the possibility of dense integration by fabricating and testing ring resonators with a 40 μm radius without a noticeable loss penalty. Our platform offers a CMOS-compatible and scalable approach for the implementation of future fast electro-optic modulators and reconfigurable photonic circuits, as well as nonlinear processes that can benefit from involving both second- and third-order nonlinearities.

Analysis, Formulation, and Implementation of a Nonlinear Equivalent Circuit for High-Frequency Semiconductor Diodes

Analysis, Formulation, and Implementation of a Nonlinear Equivalent Circuit for High-Frequency Semiconductor Diodes

Advanced Circuit Design and Implementation of a Highly Digitalized Third-Order VCO-based Sigma-Delta Modulator with Enhanced Noise Transfer Function

Advanced Circuit Design and Implementation of a Highly Digitalized Third-Order VCO-based Sigma-Delta Modulator with Enhanced Noise Transfer Function

An Investigation on the Three-Dimensional Memristive Morris–Lecar Model With Magnetic Induction Effects: Simulation of Biological Behaviors and Cost-Effective Digital Circuit Implementation

An Investigation on the Three-Dimensional Memristive Morris–Lecar Model With Magnetic Induction Effects: Simulation of Biological Behaviors and Cost-Effective Digital Circuit Implementation

Shallow Quantum Circuit Implementation of Symmetric Functions With Limited Ancillary Qubits

Shallow Quantum Circuit Implementation of Symmetric Functions With Limited Ancillary Qubits

Review and analysis on digital filter design in digital signal processing

This paper provides an extensive examination of recent advancements in designing finite impulse response (FIR) filters and infinite impulse response (IIR) filters, and techniques used in the designing of the digital filter as applied to digital signal processing. It concentrates on three primary categories of FIR filter design techniques: frequency sampling approaches, window-based strategies, and Fourier series methods. The paper evaluates the effectiveness of various FIR and IIR design methodologies, offering insights into the application of nature-inspired optimization algorithms of the designing of digital filters. Additionally, the paper also discusses the neural network techniques used for linear phase FIR filter designs, found to have better performance compared to conventional design methods. The paper also highlights the critical importance of methodical selection when it comes to implementation methodologies and design specifications to achieve efficient circuit implementation.

Nonautonomous Single Inertial Neuron Model: Coexisting Patterns, Hamilton Energy, and Analog Circuit Implementation

The main objective of this study is to investigate the chaotic dynamics and analog circuit implementation of a nonautonomous single inertial neuron. First, the dimensionless mathematical model of such neuron is established. The equilibria with three kinds of stabilities are then depicted, and system symmetry and Hamilton energy function are analyzed, respectively. In numerical simulations, by using the two-dimensional/one-dimensional bifurcation diagrams, Lyapunov exponent spectra, phase plots, and basins of attraction, bifurcation of coexisting bubbles as well as bi-stable patterns are revealed, where the generated coexisting attractors are symmetric about the origin. In addition, we confirm that the complexity of the basins of attraction deteriorates with the increase of the frequency parameter. Finally, analog circuit experiments with few analog circuit elements are deployed, via which the bi-stable patterns of the model are well verified.

Analysis and circuit implementation of fractional-order memristive hyperchaotic system with enhanced memory

Abstract In this paper, based on the memory characteristics of fractional calculus, a new fractional-order memristor is proposed. Fractional-order memristor is a more accurate description of memristor, which has richer dynamic behavior and better memory performance. Which has a stronger memorizability compared to other fractional-order memristor by analyzing the pinched hysteresis loop area. Based on the above fractional-order memristor, a fractional-order memristive hyperchaotic circuit is designed, such system is analyzed by using the Lyapunov Exponents and the bifurcation diagrams. With the change of system parameters, the phase trajectory of the system expands and narrows, and the amplitude of the chaotic attractor also changes. In addition, double chaotic attractors and coexisting attractors are found under different parameters and initial values. Finally, the fractional order memristor and the fractional order memristor hyperchaos circuit are realized by analog circuit in Multisim.

Single inertial neuron with forced bipolar pulse: chaotic dynamics, circuit implementation, and color image encryption

Abstract The bipolar pulse current can effectively mimic the external time-varying stimulus of neurons, and its effect of neuronal dynamics has rarely been reported. To this end, this paper reports the effects of bipolar pulses on a two-dimensional single inertial neuron model, showcasing the chaotic dynamics of hidden attractors and coexisting symmetric attractors, which is of significant importance for understanding the complex behaviors of neuron dynamics under time-varying external stimuli and its application. Firstly, the mathematical model of the single intertial neuron model with forced bipolar pulse is presented, and then the equilibrium states behaving as unstable saddle point (USP), stable node-focus (SNF), and stable node point (SNP) are analyzed. Additionally, by using multiple dynamical methods including bifurcation plots, basins of attraction, and phase plots, complex dynamics of interesting bifurcation behaviors and coexisting attractors are revealed, which are induced by the forced bipolar pulse current as well as initial values, both. In addition, such effets are well valideted via a simple multiplerless electronic neuron circuit. The implementation circuit of presented model is constructed on the analog level and executed using PSIM circuit platform. The measurement results verified the double-scroll chaotic attractors and the coexisting period/chaos behaviors. Finally, the chaotic sequences of the model are applied to color image encryption for the benefit of requirements on modern security field. The encryption effectiveness is demonstrated through various evaluation indexes, including histogram analysis, information entropy, correlation coefficient, plaintext sensitivity, and resistance to noise attacks.

Electronic circuit and image encryption using a novel simple 4D hyperchaotic system

Abstract A new simple 4D autonomous hyperchaotic system with seven terms is introduced. This system was inspired by an unusual 3D chaotic Liu system with six terms. The proposed system has two unstable saddle and saddle-foci points. Theoretical and numerical analyses are conducted to investigate various dynamical features of the system, including its equilibria, Jacobian matrix, Lyapunov exponents, Lyapunov dimension (Kaplan-Yorke), and multistability. The proposed system demonstrates multistability, enhancing its potential for various applications. An electronic circuit implementation using NI Multisim software 14.3 validates the system’s practical feasibility. A novel image encryption algorithm has been developed based on the system’s hyperchaotic properties. Experimental results confirm the algorithm’s robustness in both encryption accuracy and computational efficiency compared to existing methods. As well as, correlation analysis of adjacent pixels in encrypted images yields near-zero or negative values, indicating adequate randomization. The NIST SP800–22 statistical tests confirm the randomness of generated sequences with p-values consistently above 0.01. Information entropy analysis of encrypted images approaches the ideal value. These results demonstrate the proposed system’s effectiveness in secure image encryption, offering a promising solution for multimedia security applications.