Circuit Design Verification Research Articles

Automatic verification of sequential circuit designs

Temporal logic model checking is a method for automatically deciding if a sequential circuit satisfies its specifications. In this approach, the circuit is modelled as a state transition system, and specifications are given by temporal logic formulas. Efficient search algorithms are used to determine if the specifications are satisfied or not. The procedure has been used successfully in the past to find subtle errors in a number of non trivial circuit designs. Recently, the size of the circuits that can be handled by this technique has increased dramatically. It is now possible to verify transition systems that are many orders of magnitude larger than was previously the case. In this paper, we describe some of the techniques that have made this increase possible. These techniques are based on the use of binary decision diagrams to represent transition systems and sets of states.

Distributing gate-level digital timing simulation over arrays of transputers

Continuing advances in VLSI fabrication technology are allowing circuit designs to become more and more complex and are thereby fuelling the need for ever-faster digital simulators. In this paper, we investigate a multi-transputer-based method for speeding up gate-level digital timing simulation, the acknowledged 'workhorse' of the digital circuit design verification process. In particular, we describe a variant of the basic conservative method for distributed discrete-event simulation and we present PARSIM, a gate-level digital timing simulator which is based on this method and which runs on arrays of transputers. Preliminary results on small transputer arrays demonstrate good speed-ups for bitslice partitions of circuits with regular structure, including supralinear speed-ups for a large (1664-gate) circuit. Although these results are encouraging, poor results for less-than-ideal partitions of our test circuits suggest that we require an improvement in the efficiency of deadlock resolution and/or a means of automated optimized partitioning before PARSIM can be used as a practical tool for speeding up gate-level simulation.

Interfacing slave designs to FASTBUS: practical experience

The authors have designed a number of FASTBUS slave modules, using a standard interface circuit and standard design-verification tools based on computer-aided-engineering (CAE) techniques. They describe the standard interface and the design and verification methodology. The interface logic for FASTBUS slaves is divided into three blocks: the slave control logic, slave address/data logic, and slave support logic. The control logic is a hybrid chip that handles the protocol portion of the interface. The slave address/data logic includes the functions performed by the address/data interface chip and additional data-path related components, i.e. registers, buffers, and level shifters. The support logic is additional logic necessary to glue the other blocks and application logic together. >

Fast Methods for Switch-Level Verification of MOS Circuits

Simulation of hardware is a commonly-used method for demonstrating that a circuit design will work for a restricted set of inputs. Verification is a method of proving a circuit design will work for all combinations of input values. Switch-level verification works directly from the circuit netlist. The performance of existing switch-level verifiers has been improved through a combination of techniques. First, efficient methods of finding paths in the switch-graph are developed. Secondly, static analysis of the switch-graph is proposed to accelerate verification of sequential logic. Thirdly, cell replication is exploited in a safe way to make possible the verification of large hierarchical circuit designs. These ideas have been implemented in a program called V, which is part of the Penn State Design System. Experimental results are presented.

Integrated circuit design verification tools: L Szanto Microelectron. Reliab.24, 259 (1984)

Integrated circuit design verification tools: L Szanto Microelectron. Reliab.24, 259 (1984)

Integrated circuit design verification tools : L. Szanto. Microelectron. Reliab.24, 259 (1984)

Integrated circuit design verification tools : L. Szanto. Microelectron. Reliab.24, 259 (1984)

Integrated circuit design verification tools

Integrated circuit design results in two main data files: data defining a set of masks (D1), which are the final goal of the design, and data defining the schematic drawing (D2), which is a convenient form of the circuit function description. In an overview fashion a design verification system is treated in the first part of this paper. It consists of design rule checking and circuit reconstruction from D1, data file D2 translation to schematic diagram description, logic simulation of the two extracted diagrams, and mutual comparison of their topology. In the second part of this paper the following items are discussed in more detail: graphic description language - an extension of CIF for schematic drawing definition, the KOS subsystem for schematic diagram extraction from D2, and the mixed level diagram logic simulator LOMACH-MIXED.

Circuit analysis, logic simulation, and design verification for VLSI

In this paper, we consider computer-aided design techniques for VLSI. Specifically, the areas of circuit analysis, logic simulation and design verification are discussed with an emphasis on time domain techniques. Recently, researchers have concentrated on two general problem areas. One important problem discussed is the efficient, exact-time analysis of large-scale circuits. The other area is the unification of these techniques with logic simulation and design verification technique in so called multimode or multilevel systems.

Circuit analysis, logic simulation and design verification for VLSI : Albert E. Ruehli and Gary S. Ditlow. Proc. IEEE71 (1), 34 (1983)

Circuit analysis, logic simulation and design verification for VLSI : Albert E. Ruehli and Gary S. Ditlow. Proc. IEEE71 (1), 34 (1983)